soc design for dsp applications
TRANSCRIPT
P V KRISHNA MOHAN
GUPTA
Lab Assistant, ECE
department
1. SoC Design
2. System Generator for DSP applications
3. DIP Lab software
Contents
Technological Advances
today’s chip can contains billions of transistors .
transistor gate lengths are now in term of nano meters .
approximately every 18 months the number of transistors on a chip
doubles – Moore’s law .
The Consequences
components connected on a Printed Circuit Board can now be
integrated onto single chip .
hence the development of System-On-Chip design .
SOC DesignIntroduction
SoC stands for System on a Chip. Its not just an ASIC!
Other closer definitions are System in Package (SIP), System on
Silicon, System on a Board, System on a Programmable Chip
(SoPC)
System here refers to Hardware and Software
Hardware:
Analog : ADC/DAC, PLL, TxRx,RF
Digital : Processor, Interface, Accelerator
Storage: SRAM, DRAM, Flash, ROM
Software:
RTOS,IP Device Driver, Application
An SoC contains: Portable/Reusable IP, Embedded CPU,
Embedded memory, Real World Interfaces(USB, PCI, Ethernet)
Software(both on-chip and off)
An SoC may Contain: Programmable HW (FPGAs, Flash), Mixed
Signal Blocks, Sensors
What is Soc ?
Evolution of Microelectronics: the SoC Paradigm
Silicon Process Technology
• 0.13μm CMOS
• ~100 millions of devices, 3 GHz internal Clock
A system-on-chip architecture integrates several
heterogeneous components on a single chip
A key challenge is to design the communication or integrated
between the different entities of a SoC….
Typical SoC Architecture
Constituents of SoC
A processor core
GPP core, DSP core, ASIP core
On chip memory
ROM,RAM, EEPROM and Flash
Peripheral systems and on chip bus interface
Analog interfaces including ADCs and DACs
Timing reference including Oscillators and PLLs
External interfaces
USB, FireWire, Ethernet, USART, SPI, I2C
Voltage regulators and power management circuits
On chip communication protocols
SoC Design Challenges
Smaller device geometries, new processing (e.g., SOI)
Higher density integration
Low Power requirement
Higher frequencies
Design Complexity
Verification, at different levels
Time-to-market pressure
SoC Design GAP
SoC Design Challenges ! !
Source : On-Chip Communication Architectures
Use a known real entity
A pre-designed component (IP reuse) or IP based
design
A platform (architecture reuse) or Platform based
design
Partition
Based on functionality
Hardware and software
Modeling
At different level
Consistent and accurate
Conquer the complexity
Intellectual Property Categories
Intellectual Property Cores
Parameterized components with standard interfaces
facilitating high level synthesis
Cores available in three forms
Hard
Black-box in optimized layout form and encrypted
simulation model. Example: microprocessors
Firm
Synthesized netlist which can be simulated and changed
if needed
Soft
Register transfer level (RTL) HDLs; user is responsible for
synthesis and layout
Trade-offs among soft, firm, and hard cores
Reusability
portability
flexibility
Predictability, performance, time to market
Soft
core
Firm
core
Hard
core
Speech Signal Processing .
Image and Video Signal Processing .
Information Technologies
PC interface (USB, PCI,PCI-Express, IDE,..etc) Computer peripheries
(printer control, LCD monitor controller, DVD controller,.etc) .
Data Communication
Wireline Communication: 10/100 Based-T, xDSL, Gigabit Ethernet,..
Etc
Wireless communication: BlueTooth, WLAN, 2G/3G/4G, WiMax,
UWB, …,etcData Communication
Mobile phone/Smart phone
Smart Home Appliances
Major Applications
Merits and demerits of soc
DEMERITS:
Extremely high design cost (for the actual chip)
Large silicon space may be required
Component testing may be difficult
Intellectual property (IP) issues (cores)
MERITS:
Small size, reduction in chip count, Reduce over all system cost
Increase performance
Low power consumption
Faster circuit operation
Greater Design freedom
Lower memory requirements
1. SoC Design
2. System Generator for DSP applications
3. DIP Lab software
Contents
System Generator for DSP Platform Designs
System Generator is a DSP design tool from Xilinx that enable the use of the
Math Works Model-based Simulink design environment of FPGA design
Setup System Generator
Invoke Simulink library browser
To open the Simulink library
browser,
click the Simulink library
browser
button
or type “Simulink” in MATLAB
console
The library browser contains all
the
blocks available to designers
Start a new design by clicking
the
new sheet button
Creating a System Generator Design
Build the design by dragging and
dropping blocks from the Xilinx blockset
onto your new sheet.
Design Entry is similar to a schematic
editorConnect up blocks by
pulling the arrows on the
sides of each block
System Generator Design Flow
SysGen blocks
realizable in Hardware
I/O blocks used as interface between the Xilinx
Blockset and other Simulink blocks
Simulink sinks and
library functionsSimulink sources
Creating a System Generator Design
Once complete, double-click
the System Generator token
Select the target device
Select to generate the testbench
Set the System clock period desired
Generate the VHDL
Generate the VHDL/Verilog code
Design files
.VHD : VHDL design files
.EDN : Core implementation file
.XCF : Xilinx constraints file for timing constraints
Project files
.NPL : Project Navigator project file
.TCL : Scripts for Simplify and Leonardo project creation
Simulation files
.DO : Simulation scripts for MTI (Model Technology Information)
.DAT : Data files containing the test vectors from System Generator
.VHD : Simulation testbench
System Generator Output Files
1. SoC Design
2. System Generator for DSP application
3. DIP Lab software
Contents
Setup for DIP Lab
Block Diagram
Typical Applications of DIP Lab
Video security system
Visual inspection systems
Medical Electronic systems
Video analytics
Image processing Laboratory
Hardware platform for Hardware development
Single camera object tracking
Motion tracking
Tripwire
Single camera object tracking
