solutions to problems from essentials of electronic testing

7/22/2019 Solutions to Problems from Essentials of Electronic Testing

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Solutions to Problemsfrom Essentials of Electronic Testing

cM. L. Bushnell and V. D. Agrawal, 2002

February 10, 2006

Please Read This

This manual contains solutions to all problems that appear at the end of the chaptersin the book. At the end of the manual we have included the solutions to problemswe used for the examinations in the Spring 2002 course at Rutgers University, andSpring 2004 and Spring 2005 courses at Auburn University.

In spite of all the care taken to ensure accuracy, we caution the user that someanswers may contain errors as it is the first release of this manual. We will appreciateif any errors or comments are forwarded to us by email: [email protected] [email protected].

This manual has been created as teaching material that accompanies the book.To preserve its effectiveness, it should not be distributed. If necessary, only a verysmall set of solutions can be copied for distribution in the class. Please do not passyour copy on to others and ask any one requesting it to contact the authors.

Teachers can also use the presentation slides for 31 lectures (or an alternativesequence of 23-lectures), based on the book and available at the following websites:

http://www.eng.auburn.edu/vagrawal/COURSE/lectures.htmlhttp://www.caip.rutgers.edu/bushnell/rutgers.htmlWe hope the readers of our book, both teachers and students, will benefit from

this work. We acknowledge the help from colleagues and students in completing

this solution manual and the assistance of the University of Wisconsin-Madison inits initial distribution.

Solution Manual V1.4 cM. L. Bushnell and V. D. Agrawal For Teachers only Page 1


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Chapter 1: Introduction

1.1 Chip testing

The events of Example 1.1 are redefined as follows:

PQ: chip is good P: chip passes the testFQ: chip is bad F: chip fails the test

A 70% yield means, P rob(P Q) = 0.7 and P rob(F Q) = 0.3. Following the analysisof Example 1.1, P rob(P) = 0.68. Then,

Defect level = Bad chips that pass tests

All chips that pass tests

= Prob(F Q

|P)

= Prob(P|F Q)Prob(F Q)

Prob(P)

= 0.05 0.3

0.68 = 0.022

The defect level is 22, 000 ppm (parts per million).

1.2 Chip testing

Letx denote the escape probability, P rob(P|F Q). Referring to the formula derivedin Problem 1.1, a defect level of 500 ppm means,

Prob(P|F Q)Prob(F Q)Prob(P)

= x 0.30.95 0.7 + x 0.3 = 0.0005

This gives,

x=0.0003325

0.29985

Next, we obtain,

Defect coverage = Prob(F|F Q) = 1 Prob(P|F Q)= 1 x= 0.99889

The required defect coverage is 99.889%. This represents the capability of thetest in detecting the actual defects that occur and should not be confused withthe fault coverage, which is defined for the single stuck-at fault model.

1.3 Test cost

Assuming that one vector is applied per clock cycle during the digital test, the rateof test application is 200 million vectors per second. Therefore,

Digital test time = 1000 106

200 106 = 5s



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Adding the analog test time, we get

Total test time = 1.5 + 5.0 = 6.5 s

The testing cost for a 500 M Hz, 1,024 pin tester was obtained as 4.56 cents inExample 1.2 (see page 11 of the book.) Thus,

Cost of testing a chip = 6.5 4.56 = 29.64 centsThe cost of testing bad chips should also be recovered from the price of good chips.Since the yield of good chips is 70%, we obtain

Test cost in the price of a chip = 29.64

0.7 42 cents

41.8 cents should be included as the cost of testing while figuring out theprice of chips.

1.4 Test cost and self-test

Following Example 1.2 of the book (pp. 10-11), we obtain

ATE purchase price = $1.2M+ 256 $3, 000 = $1.968MAssuming a 20% per year linear rate of depreciation, a maintenance cost of 2% ofthe price, and an annual operating cost of $0.5M,

Running cost = $1.968M 0.2 + $1.968M 0.02 + $0.5M= $932, 960/year

Testing cost = $932, 960

365 24 3600 = 2.96 cents/second

Testing cost of the self-test design is 2.96 cents per second, down from4.56 cents per second calculated in Example 1.2

1.5 Test complexity

Consider a cube of side d. The number of transistors (Nt) is proportional to thevolume d3, and the number of pins (Np) is proportional to the surface area 6d

2.

Thus, the Rents rule for the cube can be expressed as,

Np = K Nt2/3

where Kis a constant, which depends on such technology parameters as the mini-mum feature spacing. For simplicity, we will assume that this constant is the samefor the flat and cubic chips. Following Example 1.3 (pp. 12-13 of book), we definethe test complexity, T C, as transistors per pin, or T C=Nt/Np. For the cube,

T Ccube = NtNp

= Nt

KNt2/3

= 1

KNt

1/3



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Using the Rents rule for a flat chip (Equation 1.5 on page 13 of book), we obtain

T Csquare= NtKNt

1/2 = 1

KNt1/2

Therefore,

T CsquareT Ccube

=Nt1/6

This ratio of test complexities continues to increase as the number of transistors ( Nt)on the VLSI device grows. For example, forNt = 1 million, the square-chip testcomplexity is ten times greater than that of the cubic-device. The test problemof the cubic configuration is less complex than that for the flat chip.

Note: Although chips at present are not designed as three-dimensional objects,three-dimensional packages and interconnects are in use. An interested reader maysee the article: H. Goldstein, Packages Go Vertical, IEEE Spectrum, vol. 38,no. 8, pp. 46-51, August 2001. Recently, Matrix Semiconductor announced plansto produce a three-dimensional memory chip. See, Adding a Third Dimension toChips,Computer, vol. 35, no. 3, p. 29, March 2002.



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Chapter 2: VLSI Testing Process and Test Equipment

2.1 Test types

To reduce the warranty and product liability costs, the manufacturer must adopt athorough but cost-effective test plan. A low failure rate, which may be as low as 100parts per million, means that among one million chips shipped by the manufacturerthere should be no more than 100 defective chips. A suitable test strategy requiresadjustments to tests as the production ramps up. A realistic plan is as follows:

Initial production: The manufacturer uses parametric tests and vector tests,the latter with coverage in the 95-100% stuck-at fault range. For high-speedmicroprocessor chips, at-speed critical path tests are run. The chips shouldbe subjected to burn-in test for infant mortality.

Matured production: If burn-in failures are lower than the required defect levelthen that test is eliminated or reduced to a sample basis. Any field returnsare re-tested by the manufacturing tests. If these pass then the manufacturingtests are augmented, when necessary, by customer-supplied tests.

Test optimization: Tests are optimized to reduce the manufacturing cost.First, test sequences that fail a larger number of devices are moved to thebeginning. Second, test sequences that do not fail any devices are dropped.Such modifications change the emphasis from detection of modeled faults todetection of actual defects.

Process monitoring: Once the chip goes into high-volume production, themanufacturing process and the outgoing product (chips) should be moni-tored to keep any variations within statistical limits. This means that var-ious parameters, such as metal resistivity, polysilicon conductivity, transistorparameters, etc., should be within their three-sigma range (average 3 standard deviation). Any excursions outside such a range are immediatelydiagnosed and the causes remedied.

2.2 Contact test

Assume a diode drop of 0.7V. Then, the pin voltage range for contact test is givenby:

Upper range : Vpin = 0V 0.7V 100A 2000= 0.9V

Lower range : Vpin = 0V 0.7V 250A 2000= 1.2V

2.3 Set-up time test

To test a set-up time, tsetup = 360ps, apply the following waveforms to the chip (aclock-to-Q delay of 400ps is assumed):



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ps

MC

Q

CLK

D

400

360ps

450ps

Measure Q

Inputs

Output

At an interval of 450ps after the rising CLK edge, measure Q on the ATE.

If Q = 1, the device passes, otherwise it fails. Using M S instead of M C, repeatthe above waveform sequence, but with D inverted and the expected Q signal alsoinverted. At an interval of 450s after the rising CLKedge, again measure Q onthe ATE. IfQ = 0, the device passes, otherwise it fails. The same waveforms areapplied simultaneously to all five D lines, and five simultaneous measurements aremade on the five Q lines.

2.4 Hold time test

To test a hold time, thold = 120ps, apply the following waveforms to the chip (aclock-to-Q delay of 400ps is assumed):

400ps

MC

Q

CLK

D

Output

120ps

400ps

Inputs

Measure Q

ps450

At an interval of 120psafter the rising C LKedge, we lower theD line. IfQ = 1450ps after the rising CLK edge, the device passes, otherwise it fails. UsingM Sinstead ofM C, repeat the above waveform sequence, but with D inverted and theexpected Q signal also inverted. At an interval of 450safter the rising C LKedge,again measure Q on the ATE. IfQ = 0, the device passes, otherwise it fails. Thesame waveforms are applied simultaneously to all fiveD lines, and five simultaneousmeasurements are made on the five Q lines.



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2.5 Threshold test

Perform the threshold test as given on page 32 of the book, but with the followingchanges: Assume a 5V supply, and perform binary search to findVIL and VIH. Thefollowing procedure determines VIL :

Incorrect

Incorrect

Incorrect

Incorrect

Incorrect

Incorrect

Incorrect

Incorrect

Read output pin.

Correct

Correct

Correct

Correct

Correct

Correct

Correct

Correct

input pin and a propagating pattern.

Read input voltage as V

If it is 0.8V or greater,the chip passes.

IL

Read the expected output

Correct

Incorrect

Write a 1.25V signal to the

Subtract 0.6V to input pin.Read output pin.

Subtract 0.3V to input pin.Read output pin.

Read output pin.Subtract 0.1V to input pin.

Read output pin.Subtract 0.15V to input pin.

Add 0.6V to input pin.

.

Read output pin.

Read output pin.




Read output pin.

The advantage of this procedure is that it greatly speeds up the test. The testfor VIHis analogous.



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Chapter 3: Test Economics and Product Quality

3.1 Economic decision

We start with the following formula for the price of the car deriven by John (Equa-tion 3.2 on page 38 of the book):

P = 20, 000 +20, 000

n dollars

where n is the number of breakdowns per 15,000 miles since Johns car is driven15,000 miles in a year. Because Laura drives only 5,000 miles per year, her car isexpected to have n/3 breakdowns per year. Assuming a linear depreciation to zerovalue over 20 years and an average repair cost of $250 per breakdown, the annual

cost of driving is

C = P

20+ K+ 250n/3 dollars

= 1, 000 +1, 000

n + K+ 250n/3 dollars

where K is the cost of gasoline and regular maintenance, assumed to be the samefor all models. To minimize this cost, we write

dC

dn =1, 000

n2 +

250

3 = 0 or n=

12

This is a minimum because d2Cdn2 >0. The price of a car for minimum transportationcost is,

P = 20, 000 +20, 000

12= 25, 774 dollars

Laura should invest in a car priced around 25,774 dollars.

3.2 Economic decision

(a) Let x be the daily wages of a technician and c be the cost of components on aboard. When n technicians work in the assembly shop, the cost of one board is,

C(n) = W arehouse cost

n + technicians wages + component cost

+workspace cost

= 10, 000

n + x + c +

500n2

n

To minimize this cost, we write

dC(n)

dn =10, 000

n2 + 1, 000n= 0 or n=

20 = 4.47



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This is a minimum since d2C(n)dn2

>0. We obtain the minimum cost as,

C(4) =C(5) = $4, 500 + x + c

To minimize the cost we should either hire four technicians, or reducethe workforce to five if more than five technicians were already employed.

(b) Substituting x = 200 andc = 10, 000 in the last equation, we get

C(4 or 5) = $4, 500 + 200 + 10, 000 = $14, 700

The minimum cost of a single-board system is $14,700.

3.3 Benefit-cost analysis

Please note a correction in the statement of this problem. The part (a) should read:Show that this scheme is beneficial for chips whose total cost is less than ten timesthe burn-in cost when the burn-in yield is 90%.

(a)Complete elimination of burn-in: LetCtbe the total cost of a chip in the presentscheme where burn-in test is applied to every chip that passes the conventional test.LetCbbe the per chip cost of burn-in. CtincludesCb, as well as another component,Cf, which accounts for the costs of fabrication, conventional test, etc. It is given by,

Ct = Cf+ ycCb

ycyb

whereyc is the yield with the conventional test and yb is the yield reduction due to

burn-in. Since the cost ofIDDQ test is 10% of the burn-in cost and there is a 10%yield loss, the cost of a chip when burn-in is replaced by IDDQ test is given by,

Ct=Cf+ 0.1ycCb

0.9ycyb

For the new scheme to be beneficial, we must have

Ct < Ct or Ct 19

Burn-in yield should be greater than 1/9 or 11.1%.



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3.4 Yield and cost

Let Cw be the cost of processing a wafer having Nchips and let y(A) be the yieldof chips, where A is the chip area. Then the cost per good chip is obtained as,

Cc= CwN y(A)

DFT changes the chip area to (1 + )A. The number of chips on a wafer of areaN A is now given by, N A/(A+ A) = N/(1 + ). The cost of a good chip withDFT is given by,

Cc(DF T) = Cw

N1+ y(A + A)

Therefore, the cost increase due to DFT is,

Cost increase = Cc(DF T) Cc

Cc 100 percent

=

(1 + )y(A)

y(A + A) 1

100 percent

Using the yield formula of Equation 3.12 (p. 46 in the book), we get

Cost increase =

(1 + )

(1 + Ad/)

(1 + (1 + )Ad/)

percent

=

(1 + )

1 + Ad + Ad

1

100 percent

which is the required result.For the given data, d = 1.25 defects/cm2, = 0.5, = 0.1, and A = 1 cm2,

we obtain

Cost increase =

1.1

1 +

1.25 0.10.5 1.25

0.5 1

100 percent

= 13.86%

There is a 13.86% increase in the chip cost due to DFT.

3.5 Defect level and fault coverage

Defect level, DL, is given by Equation 3.20 (p. 50 of the book), as follows:

DL= 1

+ T Af

+ Af

where Tis the fault coverage, Af is the average number of faults on a chip of areaA, and is a fault clustering parameter. Further manipulation of this equation



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leads to the following result:

(1 DL)1/ = + T Af+ Af

or T = (+ Af)(1 DL)1/

Af 100 percent

which is the required result.

3.6 Defect level and fault coverage

Substituting the given fault density, f = 1.45 faults/cm2, the fault clustering pa-rameter, = 0.11, and the fault coverage, T = 0.95, in Equation 3.20 (page 50 ofthe book), we obtain the defect level as,

DL(T) = 1

+ T Af

+ Af

= 1

0.11 + 0.95 1.0 1.450.11 + 1.0 1.45

0.11= 0.00522 or 5, 220 parts per million

The defect level is 5,220 parts per million (ppm).

(a) To obtain the fault coverage T for a required defect level of 1,000 ppm, wesubstituteDL= 0.001 in the formula derived in Problem 3.5. Thus,

T = (0.11 + 1.45) 0.9991/0.11

0.111.45

100 = 0.990

The required fault coverage is 99%.

(b) For a defect level of 500 ppm (DL= 0.0005), we get

T =(0.11 + 1.45) 0.99951/0.11 0.11

1.45 100 = 0.995

The required fault coverage is 99.5%.

3.7 Defect level

Defect level, DL(T), given by Equation 3.20 (p. 50 of the book), can be written as:

DL(T) = 1 (1 + TAf/)

(1 + Af/)

= 1 eT Af

eAf = 1 eAf(1T), as

Also, as , Equation 3.19 (p. 50 of the book) gives the yield,

Y =

1 +

Af

=eAf



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Substituting this expression for yield in the defect level, we get

DL(T) = 1 (eAf)1T = 1 Y1Twhich is the required result.



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Chapter 4: Fault Modeling

4.1 Boolean functions

An n-variable Boolean function is completely specified by its truth-table. The outputcolumn in this table is a 2n-bit vector that can be in 22

ndistinct states, each

specifying a different Boolean function.

4.2 Initialization faults

In the circuit of Figure 4.1 (p. 62 of the book), let Qp denote the present state atthe output of the F F. Let the next state, i.e., the output of the AND gate, be Q n.We can write the next state function, as

Qn= (Qp+ A)(A + B)

If we set A = 1, the next state function, Qn = B, becomes independent of thepresent state. That is, irrespective of the present state, the next state can be set toa value, which is uniquely determined by primary inputs. This makes the fault-freecircuit initializable. When the faultAs-a-0 is present, the above equation reduces toQn = Qp. Thus, starting with Qp= X,Qn can never be changed to any value otherthan X and, therefore, the circuit will remain uninitialized in the presenceof this fault.

Using the next-state expression, we can easily determine that no other singlestuck-at fault in this circuit will prevent initialization. For example, consider the

s-a-0 fault on the top branch of the fanout ofA. The faulty next state function isQn = Qp(A + B), which can be set to 0, when Qp= X, by applying A = 1, B = 0.

4.3 Fault counting

See Section 4.5 (last paragraph on p. 70 of the book.)

4.4 Fault counting

For the circuit of Figure 4.6 (p. 72 of book), we have

Number of fault sites = PIs + gates + fanout branches

= 2 + 4 + 6 = 12

Therefore,

Number of single and multiple faults = 3number of fault sites 1= 312 1 = 531, 440

The circuit has 531,440 single and multiple stuck-at faults.



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Ground

DDV

N2

N1

P2

Circuit for Problem 4.5.

CMOS NAND gate.

A

B

C

P1

Logic NAND gate.

A

BC

4.5 CMOS faults

(a) A two-input NAND gate is shown in the above figure. The following table givestests for transistor stuck-open (sop) faults:

Test No. Fault Test: Vector 1, Vector 2

1 P1 sop 11, 012 P2 sop 11, 103 N1 sop 01, 11 or 10, 11 or 00, 114 N2 sop 01, 11 or 10, 11 or 00, 11

Notice that the sop faults of N1 and N2 have exactly the same tests. These twofaults are equivalent. Equivalence of transistor faults is discussed in the followingpaper:M.-L Flottes, C. Landrault and S. Provossoudovitch, Fault Modeling and FaultEquivalence in CMOS Technology,J. Electronic Testing: Theory and Applications,vol. 2, pp. 229-241, August 1991.(b) The following sequence of four vectors contains one vector pair for each fault inthe above table:

11, 01, 11, 10

Notice that this sequence also detects all single stuck-at faults in the logic model ofthe NAND gate.(c) A stuck-at fault in a signal affects two transistors in the two-input NAND gate.For example, the fault A s-a-1 will mean that N1 remains permanently shorted(N1-ssh) and P1 remains permanently open (P1-sop). The following table gives allequivalences:



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Stuck-at fault Equivalent transistor faults

A s-a-1 N1-ssh and P1-sopB s-a-1 N1-ssh and P2-sopC s-a-1 (P1-ssh or P2-ssh) and (N1-sop or N2-sop)A s-a-0 N1-sop and P1-sshB s-a-0 N2-sop and P2-sshC s-a-0 N1-ssh, N2-ssh, P1-sop and P2-sop

Notice that the three equivalent faults, A s-a-0, B s-a-0 and C s-a-0, are actuallycaused by different faulty transistors. They are detected by the same test (11).

4.6 Fault models

See Section 4.4 in the book.

4.7 Fault indistinguishability

Without loss of information we will write a function f(V) as f. Thus, the left handside of Equation 4.3 is:

[f0 f1] [f0 f2]= [f0f1+ f0f1] [f0f2+ f0f2]= (f0f1+ f0f1)(f0f2+ f0f2) + (f0f1+ f0f1)(f0f2+ f0f2)

= (f0f1+ f0f1)(f0f2)(f0f2) + (f0f1)(f0f1)(f0f2+ f0f2)

= (f0f1+ f0f1)(f0+ f2)(f0+ f2) + (f0+ f1)(f0+ f1)(f0f2+ f0f2)

= (f0f1+ f0f1)(f0 f2+ f0f2) + (f0 f1+ f0f1)(f0f2+ f0f2)

= f0f1f2+ f0f1f2+ f0 f1f2+ f0f1f2

= (f1f2)(f0+ f0) + f1f2(f0+ f0)

= f1f2+ f1f2

= f1 f2= Left hand side of Equation 4.4

This completes the derivation of Equation 4.4 from Equation 4.3.

4.8 Functional equivalence

Faulty functions for the circuit of Figure 4.12 corresponding to the two faults are:

i(c s a 0) = b(ab) =abi(f s a 1) = (a + b)a= ab

The two faulty functions are indistinguishable and hence the two faults are equiv-alent.



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4.9 Functional equivalence

Faulty functions for the circuit of Figure 4.6 corresponding to the two faults are:

z(c s a 1) = ab.(ab.b)= ab.(ab + b) =ab

z(f s a 1) = abThe two faulty functions are indistinguishable and hence the faults are equiva-lent.

4.10 Fault collapsing for test generation

The circuit of Figure 4.9 has 18 single stuck-at faults. Gate-level fault equivalence,

as shown in the following figure, reduces the number to 12. The faults in shadedboxes have been collapsed as shown by arrows. Many ATPG and fault simulation

B

A1sa0 sa1

sa0

sa1

sa0

sa1sa0

sa0

sa1

sa0

sa1 sa0 sa1

sa1sa1

sa0

sa0 sa1C

B2

A2

B1

A

programs will collapse faults as shown above. However, functional fault collapsingcan further reduce the number of faults to 10. As shown in Example 4.11 (see page75 of the book), the s-a-1 faults on A1 and B 1 are equivalent, and so are the s-a-1faults on A2 and B 2.

Whether we take the set of 12 faults or the set of 10 faults, theirdetection requires all four input vectors.

4.11 Equivalence and dominance fault collapsing

(a) The given circuit is shown below with fault sites marked by numbers. Thenumber of potential fault sites is 18. The total number of faults is 36.

(b) The figure shows deletion of equivalent faults using an output to input pass.Of the 36 faults, 20 remain, giving a collapse ratio 20/36 = 0.56.

(c) Checkpoint lines are shown by boldface numbers. These are three PIs and sevenfanout branches. Line 2 fans out to 4 and 5. Line 3 fans out to 6, 7 and 8.Line 10 fans out to 12 and 13. There are ten checkpoints and 20 checkpointfaults. Further, s-a-0 faults on lines 6 and 12 are equivalent and any one ofthem can be chosen. Similarly, s-a-0 faults on 7 and 13 are equivalent, and soare s-a-0 on 5 and s-a-1 on 8. Thus, the size of the fault set is reduced to 17,giving a collapse ratio 17/36 = 0.47.



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sa0

sa1

sa0

sa1

sa0

sa1

sa1

sa0

sa1

sa0

sa018

sa1 410

7

11

15

16

14

17

9

2

sa0

sa1

sa1

sa0

5

12

13

6

8

Circuit for Problem 4.11: (b) Equivalence collapse ratio = 20/36 = 0.56

Deleted due toequivalence

1

3

sa1

sa0

sa0

sa1

sa0

sa1

sa0

sa1

sa0

sa0

sa1

sa1

sa0

sa1

sa0

sa1

sa0

sa1

sa0

sa1

Checkpoints are shown in boldface

(c) Dominance (uncollapsed faults at checkpoints) collapse ratio = 17/36 = 0.47

4.12 Dominance fault collapsing

(a) Checkpoints are defined for the signals in a combinational circuit. These signalsare the interconnects between Boolean gates, a fact not always explicitly stated. Toavoid ambiguity, the definition on page 78 of the book should read as:

Definition 4.7 Checkpoints. Primary inputs and fanout branches of a combina-tional circuit consisting only of Boolean gates are called the checkpoints.

To find checkpoints of the circuit of Figure 4.12, we must replace the exclusive-

OR (XOR) function by a primitive Boolean gate implementation. AND, OR, NAND,NOR and NOT are called the primitiveBoolean gates. Functions such as XOR aresometimes referred to as complex gates. In the following figure, we have assumedone such implementation. Our result is, therefore, based on this assumption. Otherimplementations of the XOR function are possible and can give a different set ofcheckpoints.

c

a

b

d

e

e1

e2

d1

d2

h

i

k

XOR

f

g

There are nine checkpoints in this circuit. These include three primary inputs,a, b and c, and six fanout branches, d1, d2, f, e1, e2 and g. The checkpoint faultset consists of eighteen faults s-a-0 and s-a-1 faults on the nine lines.

Notice that lines d and e of the original circuit are not checkpoints. If we did



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not model the XOR block with Boolean gates, then those lines will appear to becheckpoints, whose number will be fourteen. However, detection of those faults will

not guarantee detection of faults on the fanouts that are internal to the XOR block.Considering the Boolean gate structure, a fault on d corresponds to a simultaneous(multiple) fault ond1 andd2 and, in general, the detection of a multiple fault is notequivalent to detection of the component faults.

(b) We evaluate the output function k corresponding to the two faults:

k(d s a 0) = c + b + a + b= c + b + ab

k(g s a 1) = c + ab + ab + a= c + ab + a

The two faulty functions are shown by Karnaugh maps below. In both cases, thefunctions have exactly one false minterm, abc. Since the two faulty functionsare identical the corresponding faults are equivalent.

a

false minterm

k with d s-a-0

b

c

ab

b

k with g s-a-1

cc

b

c

a

ab

false minterm

a

Note: this type of fault equivalence is functional and is often difficult to find bytypical fault analysis tools, which rely on structurally identifiable equivalences.



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Chapter 5: Logic and Fault Simulation

5.1

The eight vectors of Table 5.1 apply all possible inputs to each stage of the 4-bitripple-carry adder. The longest path is from the carry input C0 to carry outputC4. The delay of this path is tested by two vector pairs. Vector 2 followed byvector 6 applies a rising transition at C0, which ripples through the circuit to theC4 output. Similarly, vector 7 followed by vector 3, propagates a falling transition.The rearranged vectors are given in the following table. This vector set still appliesall input states to all stages of the adder and hence is a better verification sequence.

Vec. no. C0A0B0A1B1A2B2A3B3 Path test

2 0010101016 101010101 Rising transition through path C0C47 1101010103 010101010 Falling transition through path C0C41 0000000004 0110011005 1001100118 111111111

5.2The following figure shows a two-bit shift register. Initially, both flip-flops are in the0 state. The first two 0 inputs initialize the flip-flops to the 00 state. Subsequentinputs, outputs and state transitions are shown in the figure.

0/0

0/1

00

01

11

10

1/0 1/0

1/1

0/1

1/1

State diagram of 2bit shift register.

00111010 00

Input Output

FF2FF1

State transitionsInitialization

XX 0X 00 00 10 01 10 11 11 01 00

0/0

111010000 XX



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5.3

The following figure shows a two-bit shift register with a Clearinput and the statediagram.

00

01

11

10

FF2FF1

10/0

10/1

00/1

10/0

X1/0

00/1

X1/0

Shift

Clear

Output

Edge label: Shift,Clear/Output

00/0

X1/0

00/0

10/1

X1/0

State diagram of 2bit shift register with clear input.

A necessary condition for an Eulerian path that will cover all edges traversing

each edge exactly once is that the indegree must equal outdegree at each vertex.Since the state diagram does not satisfy this condition, an Eulerian path is notpossible.

Notice that the above is only a necessary (not a sufficient) condition. Anothercondition, which is satisfied in this case, is that the graph should be strongly con-nected.

5.4

The longest path in the circuit (see Figure 5.2) is C0 to C4. The delay of this pathshould be tested for both rising and falling transitions. As shown in Example 5.3, the

path delay for a rising transition is tested by vector 2 followed by 6, which causesthe transition to ripple through the path. Similarly, the path delay for a fallingtransition can be tested by vector-pair, 6 followed by 2. From Table 5.2, vectors 1through 6 cover all stuck-at faults. Since the circuit is combinational, these vectorscan be applied in any order. We construct a sequence of seven vectors using thesesix vectors that contains the two delay test vector-pairs. The sequence is 1, 2, 6, 2,3, 4, 5.

Note: If we use the result of Table 5.3, another sequence of six vectors, 6, 2, 6,5, 4, 3, for all stuck-at faults and two path delay faults can be constructed.



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5.5

In a combinational circuit, the fault activity is completely determined by the presentvector irrespective of the previous vectors. Therefore, the faults detected by a vectorremain the same irrespective of the position of the vector in the sequence. Moreimportantly, the reverse order cannot reduce the overall fault coverage of any set ofvectors. In a sequential circuit, the fault activity caused by a vector also dependson the circuit state caused by the previous vectors. The set of faults detected by avector, therefore, varies depending on which vectors precede it. The total coverageof a sequence of vectors, applied to a sequential circuit in the reverse order, canbe quite different from their original coverage. Although it can increase sometimes,mostly the overall coverage is found to decrease.

5.6(a) Behavioral simulator: VHDL or Verilog circuit model, clock cycle accurate tim-ing.(b) Circuit-level simulator: e.g., Spice.(c) Switch-level, or mixed-mode logic (with MOS capability), or circuit-level simu-lator.(d) Multiple-delay logic, or circuit-level simulator.(e) Unit-delay logic simulator.

5.7

When the two control inputs are changed to 0, the bus will be in the floating stateand will retain its previous state, which is 1. Thus, the output of the inverter willremain 0.

In the logic model of Figure 5.7, initially all four inputs to the bus driver (shadedblock) may be 1. That will set the bus node to 1 and the output to 0 states. Whenthe two control inputs (top and bottom inputs to AND gates in the shaded block)are changed to 0, the bus output will change to 0 and the output will change to 1.Thus, the logic model gives incorrect values.

5.8

The following circuit models an AND bus. This is a combinational model, whichdoes not have memory. When both controls are off,C1 =C2 = 0, andunknown(X)value appears at the output. Logic simulators are often designed to supply the Xvalue. The circuit can be modified to produce a 0 or a 1, instead ofX. The buswill be set to a 0 if the X input of the OR gate is removed. It will produce a 1 ifthe three-input OR gate is omitted.

When only one control, C1 or C2, is turned on, the corresponding data, eitherD1 orD2, appears at the output. When both controls are on, the output isD1 D2.

Besides the lack of memory, this model does not also have the bidirectionalbehavior that is usually present in MOS circuits.



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bus output

C1D1

C2D2

Unknown (X)

5.9

The following schematic shows a logic model for a bus with memory. When bothdrivers feed data to the bus, i.e., C1 = C2 = 1, D1D2 appears at the output,assuming a 0-dominance. When both drivers are turned off, i.e., C1 = C2 = 0,the output retains its value through feedback. When only one driver is on, thecorresponding data input appears at the output.

bus output

C1D1

D2C2

This model represents most of the characteristics of a MOS bus, with the excep-tion of bidirectionality. One problem with it is that it is an asynchronous sequentialcircuit and cannot be correctly simulated by some simulators. An event-driven logicsimulator can simulate it, but will be inefficient in comparison with synchronouscircuit simulation.

5.10

With the given inputs, 00, and output X, when the clock is applied the circuit willnot be initialized. The reason is that in a three-state logic system the inversion ofX is alsoX.

The circuit can be initialized to a 1 output by clocking the flip-flop when a 11input is applied. Then, if we change the input to 10 and clock the flip-flop, theoutput will become 0. These two vectors can be correctly simulated by a three-statelogic simulator.

5.11

The two cases are sketched below. The rise and fall delays of the OR gate aredenoted by tr and tf, respectively. In (a) the output pulse width is 8 units and in(b) it is 4 units.



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6

tr=3 tf=5

tf=3tr=5

time units(b) Output

(a) Output

Input

0

5.12

The two cases are sketched below. The rise and fall delays of the OR gate aredenoted bytr and tf, respectively. In (a), a rise is first scheduled to occur at 3 timeunits after the rising edge of the input. Before this rise takes place, the input fallsat 1 unit, and reschedules a falling output at time 6 units. A conservative simulatorproduces an unknown (X) output between 3 and 6 units of time. This is shown asa level between logic 0 and 1 in the following figure.

0

tr=5

time units(b) Output

(a) Output

Input

tf=5tr=3

1

tf=3

In (b), the output cannot rise until 5 units of time. Meanwhile, at time unit 1, afall is scheduled to be completed at time unit 4. Thus, the output does not changeat all.

Case (b) is an example of a pulse being filtered by a slow gate. In simulators,this phenomenon is referred to as spike suppression. The actual waveform producedby the simulator depends upon the specific assumptions made. In pessimistic sim-ulation, a pulse of ambiguous height may be produced as in case (a) above. Inoptimistic simulation, the output may remain unchanged if the input pulse width issmaller than the gate delay.

5.13

Upon the evaluation of a zero-delay gate, if the output changes then the new eventis added to the current event list. Thus, all zero-delay events would be processedbefore the current event list becomes empty and the time is advanced.

5.14

For unit-delay simulation only two time slots are needed: current-time and next-time. When the current-time event list becomes empty, the time pointer is moved



24/215

to the next-time slot, which then becomes the new current-time. The old current-time slot has no use now and it used as the next-time. Thus, the circular time-wheel

contains only two slots.

5.15

Let us assume that the circuit has Ffaults andVvectors detect all faults. Accordingto the given information, the coverage rises linearly from 0 toFfaults as the numberof simulated vectors increases from 0 to V. This is shown in the figure below.Assuming to be the CPU time required to simulate one vector in the true-value

F

00

Faultsde

tected

VVectors simulated

mode, simulation time for the fault-free circuit is V. When no fault-dropping isdone, each faulty circuit is simulated for all V vectors. Therefore, the simulationtime is given by,

T(no f ault dropping) = V + F V = V(1 + F)Since faults are uniformly detected, each vector detects F /Vnew faults not detectedby the previous vectors. Thus, the fault simulator divides the fault set intoV equalsubsets, each containing F/V faults. The F /Vfaulty circuits corresponding to thefaults detected on the first vector are simulated through just one vector requiringa time F/V. The F /V faulty circuits corresponding to the faults detected on thesecond vector are simulated through two vectors requiring a time 2F/V. Similarly,the F/V faulty circuits corresponding to the faults detected on the ith vector aresimulated through i vectors requiring a time iF/V. When we include the simulationtime for the fault-free circuit, the total CPU time for simulation with fault droppingis given by,

T(fault dropping) = V +

Vi=1

i F

V = V(1 +

F

21 + V

V )

For large F and V , we find

T(fault dropping)

T(no f ault dropping)0.5

5.16

Since no fault dropping is used, the serial fault simulator must simulate the entirecircuit n+ 1 times. Assuming the CPU time for one simulation with all vectors is



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t, total time of serial fault simulation is given by,

T(serial) =t(n + 1)

Using CPU timet, the parallel simulator processes w 1 faults. Thus, it will maken/(w 1) such passes, requiring total time,

T(parallel) = tn

w 1Therefore,

T(serial)

T(parallel)=

(n + 1)(w 1)n

5.17

The circuit of Figure 5.22 is shown below. The bits of the four-bit word are assignedas follows:

Bit 0: G, good circuit

Bit 1: Faulty circuit with fault F1, second input s-a-1

Bit 2: Faulty circuit with fault F2, input to inverter s-a-1

Bit 3: Faulty circuit with fault F3, second input of first AND gate s-a-1

sa1 0

1

1

1

1

1111

1

1

1

1

0 0

0

0

0

1

0

0

01

0 1 0

10

0 1

1 1 0

1

1 1 1 110

11 0

F1

F2sa1

sa1F3

G F1 F2 F3

bit0(G)

bit1(F1)

bit2(F2)

bit3(F3)

The figure shows the good and faulty circuit values for each signal by a four-bitword. A comparison among bits of the word at the primary output indicates thatonly the bit corresponding to F2 differs with the good circuit output. Hence, thevector 101 detects F2 but does not detect F1 and F3.



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5.18

The following table shows how the fault effect (D or D) propagates through anexclusive-OR gate c = a b. For a fault to affect the value ofc, it should affect thevalue ofa, or that ofb, but not those of both. Therefore, for a fault to be includedin Lc, it should be either in La or in Lb, but not in both. Thus,

Lc = (La Lb) (La Lb) c1, if c= 0or Lc = (La Lb) (La Lb) c0, if c= 1.

One input Other input Output, c

D D 0D D 0

D D 1D 0 DD 0 DD 1 DD 1 D

5.19

The two simulators differ in the dynamic memory usage. The major part of thememory used by each simulator consists of the lists that are stored for each lineof the circuit. These lists are dynamic and continuously change as the simulationprogresses. In a deductive fault simulator, the list for a line contains the faultsthat affect the value of that line. In a concurrent fault simulator, the list for a linecontains all faults that affect the gate producing the signal on the line. Thus, thelist may contain some faults that do not affect the output line but only affect theinputs of the gate. Since such faults will not be included in the fault list of that linein a deductive fault simulator, the corresponding list will be shorter.

Having a complete picture of faulty-circuit gates (i.e., its input and output signalvalues) allows the concurrent simulator to accurately simulate the events occurringat gates. In general, when gates have different rise and fall delays, the good-circuitevents and various faulty-circuit events on a line can occur at different times. Thetiming in a deductive fault simulator basically follows the events of the good-circuit.

The other advantage that the expanded data-structure provides to the cuncur-rent fault simulator is the ability to simulate a variety of non-Boolean and high-levelgates.

5.20

(a) Though all four types of simulators can be used, deductive and parallel algo-rithms will experience significant slow down due to embedded memory blocksthat are usually simulated at the functional level. Complexity of the parallelalgorithm will also increase due to the non-Boolean signal states, X and Z. In



27/215

the deductive algorithm, the fault list propagation for these signal states willbe complex and sometimes approximate.

(b) The best choice will be a concurrent fault simulator.

5.21

(a) When the tests can detect both single faults, there is high probability of de-tecting the multiple fault. Only in the rare case that the two faults mask eachother (two-way masking) will the multiple fault go undetected.

(b) The test will not detect the multiple fault only if f2 masks the effect of f1produced by the test. Usually, the probability of this one-way masking issmall, but it is higher than the two-way masking in (a).

(c) In the majority of cases where single faults f1 and f2 are not detectable by thetests, the multiple fault (f1,f2) may also go undetected. However, in a specialcase where a test activates both single faults but fails to propagate the faulteffect to a primary output, the two fault effects may cooperatively propagateto the output, detecting the fault.

5.22

For N faults, we effectively simulate the good circuit and N faulty copies of thecircuit, each containing one fault. Suppose the circuit has G gates. At any time

about half of the faulty circuit gates are identical to the good circuit gates becausethe corresponding faults are not active. Gates in these circuits are not explicitlysimulated by the concurrent fault simulator. For the remaining N/2 circuits inwhich some signals differ from the good circuit, only a fraction of gates actuallydiffer from their counterparts in the good circuit. Taking all this into account, theconcurrent fault simulator will only evaluate G + GN/2 gates, which is 1 + N/2times the gates simulated in a true-value simulation.

5.23

The following figure shows the TEST-DETECT procedure. First, true-value simu-lation determines the values for all lines. These are the binary values shown in thefigure. Next, we start at the fault site. The value 0 activates the s-a-1 fault asD.

0

1

1sa1

0(D)0(D)

1 D

1(D)

1

Fault not

detected

So, we temporarily replace 0 with a D . This is shown as 0(D). Now D fans out to



28/215

the upper AND gate and the NOT gate. For the present signal states, the outputsof these gates are written as 0(D) and 1(D), respectively. TheD at the output of

the NOT gate propagates through the lower AND gate whose output is written as1(D). Inputs D and D at the inputs of the OR gate leave the output unchanged as1. Thus, the given fault is not detected.

5.24

Differential fault simulation of two faults requires three steps illustrated in the figure:

0

1

1

1

0

1

1

1

0

1

1

1

sa1

0

11

1

1

1

0 0

0 0 1

0 1

1

Saved output

detected

Fault not

sa1

1 0

0 1

1 0

0

0

Saved outputvalue is 1

value is 1

detected

Fault0

Step 1: Truevalue simulation.

Step 2: Simulation of first fault.

Step 3: Simulation of second fault.

Step 1: True-value simulation. All line values are determined for the given inputvector, 101, using logic simulation. The primary output value, 1 in this case,is saved.

Step 2: Simulation of first fault. Since the existing value at the site of the s-a-1 faultis 0, we place a 01 event there. Event-driven logic simulation propagatesevents until no more events exist. If the new output value differs from thesaved true-value output, then the fault will be detected. In this case it is notdetected.

Step 3: Simulation of second fault. We simultaneously restore the values to fault-free states and compute the values corresponding to the second fault. This isdone by placing a 10 event at the site of the first fault and a 01 event at



29/215

the site of the second fault. Event-driven logic simulation now determines theoutput of the second faulty circuit, which is 0 in this case. Since this differs

from the saved good circuit output value of 1, this fault is detected.

The following comments are relevant here:

It is possible that the first fault changes the value at the site of the secondfault. In that case, Step 3 will begin with just one event, because the secondfault will be inactive for the signal states at the end of Step 2. However, asthe simulation proceeds in Step 3, the second fault will become active and thesecond event will be placed.

If there are no more faults to be simulated and another vector is to be simu-lated, then corresponding primary input changes are placed as events. True-

value and fault simulation steps are successively repeated.

5.25 Fault sampling

Since the size of fault population (Np = 105) is very large compared to the sample

size (Ns= 4, 000), we use the approximation of Equation 5.5 (page 123 in the book.)

Sample coverage, x= 3, 900

4, 000 = 0.975

Using Equation 5.8 (see page 123 in the book), we get

3 coverage estimate = x 4.5Ns

1 + 0.44Nsx(1 x)

= 0.975 4.54, 000

1 + 0.44 4, 000 0.975 0.025

= 0.975 0.0075 or 97.50 0.75 percent

5.26 Fault sampling

Assuming that the fault sample size is much smaller than the total fault population,i.e., NsNp, we use the result of Equation 5.9 (page 124 in the book), which canbe written as,

Sample size, Ns = 4.52

20.44x(1 x)

where is the 3 range of the coverage estimate and x is the sample coverage.Using the given data, = 0.02 and x= 0.70, we obtain

Ns = 4.52 0.44 0.7 0.3

0.022 = 4, 678 faults



30/215

Chapter 6: Testability Measures

6.1 SCOAP

(2,3)4

(6,2)0

(CC0,CC1)CO

IN2

IN1

IN0

OUT0

(2,3)4

Circuit of Figure 6.1 with combinational SCOAP measures.

6

6

5

(1,1)6

(1,1)5

(1,1)6

6.2 SCOAP

G

(1,1)5

(1,1)5

(1,1)6F (CC0,CC1)CO

A

C

B5

D (2,3)3(5,4)0


(3,2)5

5

7

7

(2,4)3

E

6.3 SCOAP

x

4x

5

(1,1)11

x6

x

x

2w

3

(CC0,CC1)CO

w

2

x1

1

(1,1)10

(1,1)9

(4,2)8

(4,2)6

(4,2)6


(8,5)0

(5,5)3

(4,2)6

9

(3,2)8

(1,1)9

(1,1)9

(1,1)10

11

8

9

8

10



31/215

6.4 SCOAP

x

x

f

5

4x

3x

2x

1

(1,1)5

(1,1)7

(1,1)6

(1,1)5

(1,1)6 6

5

5

6F2

F1

(5,5)0

(5,4)0z

2

z3

z4

(4,2)3

e

(4,2)3

(3,2)3

3

3

5a

c

d

z1

(3,2)5

b

7

7

(CC0,CC1)CO


6.5 SCOAP

(3,2)6

(1,1)7

(1,1)8

(1,1)8

8(8,2)0

(4,4)4

(2,3)6(1,1)8

B

C

D


A

(1,1)7

8

J

(CC0,CC1)CO

E

6.6 High-level testability

The data flow graph (DFG) of the given circuit shown below. The table gives thesequential depth testability measures for all input-output pairs of signals.

YIN loady

C15 C10 C9

m3

REGO

XIN m1 m2 loadx

OUTPUT

0

0

0

0

0

0

m4 loado

Data flow graph (DFG) for the circuit of Figure 6.24.

ZERO

0

0

REGYREGX



32/215

Input Output signalsignal OU T P UT C 9 C15 C10 RE GX RE GY RE GO

XIN 2 1 1 2 1 2 2m1 2 1 1 2 1 2 2m2 2 1 1 2 1 2 2loadx 2 1 1 2 1 2 2m3 3 2 1 1 2 1 3Y IN 3 2 1 1 2 1 3loady 3 2 1 1 2 1 3m4 1 1loado 1 1ZERO 1 0 0 1REGX 1 0 0 1 1 1 1REGO 0REGY 2 1 0 0 1 2 2

6.7 SCOAP

The steps of calculation for SCOAP testability measures are shown in the three

figures that follow. Combinational measures are shown as (CC0, CC1)CO andsequential measures as [SC0, SC1]SO.

[0,0](1,1)

[0,0]

[0,0]

(1,1)e

[0,0](1,1)

[0,0](2,4)

[0,0]

[0, ]

(2, )

(4,2)

8

(2,4)0

[0,0]0

8

[0,0]

8

8

8

8( , )

8

Circuit of Figure 6.25: PI and PO initialization and first controllability pass.

8

88

8

8

8 8

8

8

[ , ]

8

8

8

8

f

8

b

a

g

8

(1,1)

(1,1)88

c

RESET

CK

dQ D

FFMC



33/215

[0,0]

(1,1) [0,0]

e

8 8

88

(1,1)

(2,4)0

[0,0]0

[0,0]

[0,0]

(2,4)

[0,0](1,1)

[0,0]

[0,0] 8

8

(2,9)

[0,1]

8

[1,1]

(3,7)

Circuit of Figure 6.25: Converged controllability values.

8

8

8

8

8 8

8

8

8

8

8

(4,2)

d

c

g

a

f

(1,1)

(1,1)

b

Q

RESET

DFF

MC CK

(2,4)0

e

[0,0]0(1,1)3

(1,1)5 [0,0]0 [0,0]0

d

c

g

a

b f

(1,1)12

[0,1]0

[0,0]2(1,1)16

(1,1)16 [0,0]2

Circuit of Figure 6.25: All controllability and observability values.

(2,9)4

[0,0]1

(3,7)6

[1,1]0

(2,4)9

[0,0]1

(4,2)2

[0,0]0

Q

RESET

CKMC

FFD

6.8 SCOAP

The steps of calculation for SCOAP testability measures are shown in the threefigures that follow. Combinational measures are shown as (CC0, CC1)CO and

sequential measures as [SC0, SC1]SO.

[0,0]

[0,0]

[0,0]

(2,3)

3

3

6

1

2

[0,0]

(1,1) [0,0]

[0,0](1,1)

(2,4)

(2,3)

[0,0]

(2,4)

[0,0]

[0,0]

2

G

G

G

O

G

G

G

G

G

O

5

7

8

14

O

4

1

2

3

8

8 8

(2, )8

8

8 8

(4, )

[0, ]

8

8

(1,1)

(1,1)

(1,1)

8

8[0, ]8

Circuit of Figure 6.26: PI and PO initialization and first controllability pass.

8

( , ) 8 8

8 8

8

8

88

8

8

8

8 88 8[ , ]

8

8

8

8

I

MC

FFDQ

RESET

CLOCK

I

I

I

(5,11)0

[0,0]0(2,4)0

[0,0]0

[0,0]0(2,4)0



34/215

3

6

1

2

2

5

7

8

1

3

[1,1]

(2,3)

[0,0]

(2,3)

(3,7)


[0,0]

[0,0]

[0,0]

4

G

G

G

G

G

I

I

I

I

G

4

1

2

3

O

G

G

O

O[0,0]

8

8 8

8

8

8

8

8

8

8

8

(1,1)

(1,1)

(1,1)

8

8

8

8

8

8

[0,1]

[0,0](2,4)

(1,1)

(4,6)

(2,5)

[0,1]

(2,4)

[0,0]

[0,0]

8 8

8

8

8

[0,0](1,1)

8

8

CLOCKMC

FF

[0,0]0

[0,0]0(2,4)0

(5,11)0

(2,4)0

RESET

[0,0]0

DQ

8

7

5

4

4

1

2

3

1

3

(1,1)4

(1,1)3

(1,1)32

2

3

6

1

O

I

I

I

I

[0,0]0(2,4)0

(5,11)0

CLOCK

G

G

G

O

O

G

G

G

G

G

[0,0]0

3

4

6

13

(1,1)14

4

4

13

12

0


11

11

9

10

30

9

[0,0]2

[0,0]0

(2,3)11

[0,0]0

(2,3)2

[0,0]0

[0,0]0

(3,7)4 [1,1]0

(2,5)2

(2,4)7 [0,0]1

(1,1)14 [0,0]2

[0,1]0

[0,1]0

(2,4)9

[0,0]0

(4,6)7

[0,0]0

RESET

[0,0]0(2,4)0

MC

FFDQ



35/215

6.9 SCOAP

The steps of calculation for SCOAP testability measures are shown in the threefigures that follow. Combinational measures are shown as (CC0, CC1)CO andsequential measures as [SC0, SC1]SO.

8

8

8

8 8

(3, )

8

8

[0,0]

(1,1)

8

[0,0](1,1)

B(x)V(x)

[0,0]

8

88

8

(1,1)

[1, ]

[2,2]

8[2, ]

8

(9,9)

Circuit of Figure 6.27: Initialization and first controllability pass.

8

8 8

8

8[1, ]

(7, )

(3, )(3, )

[1, ]

8

8

8

88

[2,2]0Q D

FFQ

MR

(9,9)0D(x)

RESET

CLOCK

MR

DFF

(1,1) [0,0]

[0,0](1,1)

(3,12) (9,9)

[2,4]

(7,16)

[1,3][1,3] [2,2]0

(9,9)0D(x)

RESET

V(x)

(3,12)

[1,4](3,15)B(x)

[2,2]8

8 8

8

(1,1)


8

8

[0,0]8

8

88

8

8

888

8

CLOCK

Q DFF FF

MRMR

Q D

[0,0]5

[0,0]5(1,1)21

24 521

21

6(1,1)21

Q

MR MR

CLOCK

21

5

D(x)

RESET

5

(1,1)8V(x)

(7,16)2

[2,4]0


(3,15)6 [1,4]1B(x)

[0,0]2

[1,3]2

(3,12)9 (3,12)6

[1,3]1 [2,2]0

(9,9)0(9,9)9

[2,2]2D

FFQ D

FF



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6.10 SCOAP


CLOCK

QD D Q

RESET


1 2

Q1Q2

(1,1) [0,0]

(1,1) [0,0]8 8

8 8

8

88(7, ) [2, ] 8

(7, ) [2, ] 8

8[ ,1]( ,4)

(3, )0 [1, ]0 (3, )0 [1, ]08 8 8

8888

8

8

8

CLOCK

QD D Q

RESET


1 2

Q1 (3,7)0 [1,2]0 (3,14)0 [1,4]0Q2

(7,11) [2,3](7,11) [2,3]

[7,1]

(1,1) [0,0]

(1,1) [0,0]8 8

8 8

8

8

8 888

(26,4)

CLOCK

QD D Q

RESET


1 2

22 6

7

2

17

5510 3

3

23 6

(1,1)10 [0,0]3

(1,1)10 [0,0]3Q1 (3,7)0 [1,2]0

[7,1]1

(7,11)18 [2,3]5

15

610

17

7 4(7,11)3 [2,3]1

(3,14)0 [1,4]0Q2

(26,4)3



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6.11 SCOAP


QD D Q

CLOCK

RESET


MR

MS

Q Q21

8

( ,7) [ ,2]8 8 8

(1,1) [0,0]8 8

(1,1) [0,0]8 8

8

88 8 8 88(3, ) [1, ] 8( ,3) [ ,1]

h1

QD D Q

CLOCK

RESET


MR

MS

Q Q21

(1,1) [0,0]8 8

(1,1) [0,0]8 8

8

8 8

h1

(10,7) [3,2] 8

(3,10) [1,3] 8 (6,3) [2,1] 8

QD D Q

CLOCK

RESET


MR

MS

Q Q21

h1

3

134 13

48

3

1

3

9(10,7)3 [3,2]1

(1,1)9 [0,0]3

(1,1)8 [0,0]3

(3,10)0 [1,3]0 (6,3)0 [2,1]0



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6.12 SCOAP


CLOCK

QD D Q

RESET


8(7, ) [2, ] 888(5,5) [1,1]8 8

(3, )0 [1, ]08 8

(1,1) [0,0]8 8

(1,1) [0,0]8 8

(3, )0 [1, ]0881X 2X

MR MR

C C

Z

8 8(1,1) [0,0]

CLOCK

QD D Q

RESET

Circuit of Figure 6.30: Continuation of controllability calculations.

8(5,5) [1,1]8 8

(3, )0 [1, ]08 8

(1,1) [0,0]8 8

(1,1) [0,0]8 8

1X 2X

MR MR

C C

Z

(7,12) [2,3] 8

8 8(1,1) [0,0] (3,8)0 [1,2]0

CLOCK

QD D Q

RESET

Circuit of Figure 6.30: Stabilized controllability and observability values.

1X 2X

MR MR

C C

Z

(3,8)0 [1,2]0

(1,1)11 [0,0]3

(1,1)11 [0,0]3

(5,5)3 [1,1]1 (7,12)3 [2,3]1

(3,15)0 [1,4]0

(1,1)7 [0,0]2

311

35

18

5

11 18



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6.13 SCOAP

The steps of calculation for SCOAP testability measures are shown in the four figuresthat follow. Combinational measures are shown as (CC0, CC1)CO and sequentialmeasures as [SC0, SC1]SO.

QD D Q

RESET

CLOCK


8 8

Z

MR MR

(1,1) [0,0]8 8

A1 2A

(3, )0 [1, ]08 8(3, )0 [1, ]08 8

(1,1) [0,0]8 8

(1,1) [0,0]8 8

(2, ) [0, ]8 8 8 8 ( ,4) [ ,1]88

QD D Q

RESET

CLOCK

Circuit of Figure 6.31: Continuation of controllability calculation.

8 8

Z

MR MR

(1,1) [0,0]8 8

A1 2A

(3, )0 [1, ]08 8

(1,1) [0,0]8 8

(1,1) [0,0]8 8

8 ( ,4) [ ,1]88(2,9) [0,2] 8

(3,7)0 [1,2]0

QD D Q

RESET

CLOCK

Circuit of Figure 6.31: Stabilized controllability values.

8

Z

MR MR

(1,1) [0,0]8 8

A1 2A

(1,1) [0,0]8 8

(1,1) [0,0]8 8

8(2,9) [0,2] 8

(3,7)0 [1,2]0(3,12)0 [1,3]0

(20,4) [5,1] 8

QD D Q

RESET

CLOCK


Z

MR MR

A1 2A

(3,7)0 [1,2]0(3,12)0 [1,3]0

43 10

3

(2,9)3 [0,2]1 (20,4)3 [5,1]1

(1,1)11 [0,0]3

(1,1)10 [0,0]3

(1,1)10 [0,0]3

10

15

15

4



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Chapter 7: Combinational Circuit ATPG

7.1 Cubes

AND gate:

a

bc

Singular cover:

a b c

0 X 0

X 0 01 1 1

Propagation D cubes(last two cubes arenot propagation D-cubes since they do notpropagate D or D):

a b c

1 D DD 1 DD D D

1 D DD 1 D

D D 0D D 0

PrimitiveD cube of failure for a sa1:a b c

0 1 D

Exclusive-OR gate:

a

b c

Singular cover:

a b c

0 1 11 0 11 1 00 0 0

Propagation D cubes(last four cubes arenot propagation D-cubes since they do notpapagate D or D):

a b c

0 D DD 0 DD 1 D1 D D0 D DD 0 D1 D DD 1 D

D D 0D D 1D D 1D D 0

PrimitiveD cubes of failure for a sa1:

a b c

0 0 D0 1 D



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7.2 Stuck-at fault testing

(a) Three tests for a two-input OR gate:

a

bc

Vector number a b c Collapsed faults tested

1 0 0 D a sa1, b sa1, c sa12 0 1 D b sa0, c sa03 1 0 D a sa0, c sa0

(b) Gate replacements:

OR replaced Test resultsby: Vector 1 Vector 2 Vector 3

AND pass fail failNAND fail pass passNOR fail fail fail

The three-vector test will detect the error if the OR gate were to bereplaced by an AND, NAND or NOR gate.

(c) OR gate replaced by an exclusive-OR gate: All three vectors will produce thesame output as that of the OR gate. Therefore, this error will not be detected. Itis necessary to include a fourth vector 11 to detect this error. The addition of the

a

bc

1

10 (1 for OR gate)

fourth vector makes the vector set exhaustive, which completely verifies the truthtable of the gate.

Note: In a simulation-based comparison of two circuits to establish logic equiv-

alence, a good (though not complete) heuristic is to use a vector set that covers allsingle stuck-at faults in both circuits. See the paper: V. D. Agrawal, Choice ofTests for Logic Verification and Equivalence Checking and the Use of Fault Simula-tion, Proc. 13th Int. Conf. VLSI Design, 2000, pp. 306-311.



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7.3 D-ALG

We level order the signals and proceed as follows:

Step Action Signals D Impl.no. A B C d e f g Y h k Z front. stack

1 Fault Activation 0 0 D k g= 0Immediate impl. 0 0 0 0 D k g= 0Immediate impl. 1 1 0 0 0 0 D k g= 0Immediate impl. 1 1 0 0 0 0 0 D k g= 0Immediate impl. 1 1 0 0 0 0 0 D 0 g= 0Immediate impl. 1 1 0 0 0 0 0 D 0 1 g= 0

The fault is redundant, because the D-frontier disappeared. No backtracks.Signals are shown in the following figure.

h

A

BC

1

1

d 0

0

e

f

0

D

g 0Y

Z

sa1

k

0

7.4 D-ALG

We level order the signals and proceed as follows:

Step Action Signals D Impl.no. A B C d e f g Y h k Z front. stack

1 Fault activation 1 1 D k g= 1

2 D-drive hk 1 1 1 D D Z f = 1g= 1

3 D-drive kZ 0 1 1 1 D D D P O B = 0f= 1g= 1

Immediate Impl. 0 0 1 1 1 D D D P O Immediate Impl. 0 0 1 1 1 1 D D D P O Immediate impl. 0 1 0 1 1 1 1 D D D P O

The test is: A= X, B = 0, C= 1 as shown in the following figure; 0 backtracks.



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h

A

BC

1

d 0

e

f

gY

Z

sa0

0

1

1

1D

k

DD

7.5 PODEM

The figure below shows the SCOAP testability measures used for guiding PODEM.

h

A

BC

d

e

f

gY

Z

sa16

(1,1)6

(1,1)5(1,1)5

(1,1)8

(1,1)8

1 1 5

(3,3)6

(6,9)0

k(4,7)2

(6,3)0

5

5

(6,3)0

(6,3)6

(3,2)3

(2,3)4SCOAP values: (CC0,CC1)CO

The steps of the PODEM algorithm are recorded in the following table:

Step Objec- Action Imp. Implied signal values D XNo. tive stack A B C d e f g h k Y Z front. path

1 g= 0 Backtrace B = 1 1 ok

2 g= 0 Backtrace C= 1 1 1 0 0 0 1 noneB = 1

3 g= 0 Backtrack C= 0 1 0 1 1 1 1 1 1 0 noneB = 1

4 g= 0 Backtrack B = 0 0 0 1 1 1 1 none

5 g= 0 Backtrack EmptyAlgorithm termination: Objective g=0 is impossible; fault h s-a-1 is redundant.

Explanation: An X-path is a path from the fault site to a PO, such that thesignals on it are either faulty states (D or D) or undetermined. An ok for X-pathin the table means that one or more such paths exist. Having no X-path is areason for backup because its existence is a necessary condition for the detection ofthe fault. When a series of backups leads to an empty stack, it indicates that theobjective g = 0 is impossible. As a result, the fault h s-a-1 cannot be activatedand, hence, it is redundant. Three backtracks.



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7.6 PODEM


AB

CD

EF

GH

k

m

o

s

q

r

p

1 1 9

(1,1)9

(1,1)13

(1,1)13

(1,1)13

(1,1)13

(1,1)13

(1,1)13(3,2)11

(3,2)11

(3,2)11

(3,2)7

(9,10)0

(5,4)8

(5,4)8

sa0(9,6)3

117

SCOAP values: (CC0,CC1)CO

Z

The steps of the PODEM algorithms are recorded in the following table:

Step Objec- Action Imp. Implied signal values D XNo. tive stack ABCDEFGHkmopqsrZ front. path

1 r= 1 Backtrace E= 0 E= 0, o= 1 ok

2 r= 1 Backtrace G= 0 E= 0, G= 0, o= 1, p= 1 PO okE= 0 q= 0, r= 1, Z= D

Algorithm termination: Fault detected with 0 backtracks.

Test is{ABCDEFGH}={XXXX0X0X}Explanation: See the explanation in Problem 7.5.

7.7 PODEM and FAN

The following figure shows the SCOAP testability measures used for guiding PO-DEM and FAN.

A

g

ls

Z

r

u

wq

p

h

k

m 10

B

C

D

E

F

(1,1)12

(1,1)16

(1,1)14

(1,1)16

(1,1)12

1 1 12

17

17

(3,2)15

15

15

16

(2,4)13

(5,5)10

(2,4)13

10

14

12

17

13

(2,8)1014

17(2,10)8

(2,7)8

(6,5)5

(11,10)0

sa1

(3,3)10(5,2)8

(7,2)8

17

16



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Step Ob jec- Action Imp. Implied signal values D XNo. tive stack ABCDEFghklmpqsruwZ f ront. path

1 r= 0 Backtrace A= 0 r= 0(D), u= 0 Z ok2 w= 1 Backtrace B = 1 A= 0, B = 1, p= 0, q= 1, s= 1 PO ok

(D-drive) A= 0 r= 0(D), u= 0, w= 1, Z= D

Algorithm termination: Fault detected with 0 backtracks. Test is{ABCDEF} = {01XXXX}

The following table gives the steps that PODEM takes:For an explanation ofX-path, see Problem 7.5.

(a) FAN ATPG. Step 1 is the same as for PODEM.

Step 2. Goal: propagate D fromr to Z.Goal: setw = 1, 1 vote for 1, set q= 1, 1 vote for 1, set s = 1, 1 vote for 1,

setB = 1, 2 votes for 1, no votes for 0. Rest of step 2 is exactly the same asPODEM.Headlines are m and l.Initial objective: set r = 0.Final objective: set B = 1.Fanout objectives: set B = 1.Head objectives: not used. 0 backtracks.

(b) The following lists dominators for all signals.

Gate Dominators Gate Dominators Gate Dominators

Z p r, Z h m, Z r Z q w, Z k m, Z u Z s w, Z g m, Z w Z m Z l s, w, Z

7.8 PODEM


A

ls

Z

r

u

wq

p

k

m 10

B

C

D

E

F

(1,1)12

(1,1)16

(1,1)14

(1,1)16

(1,1)12

1,1 12

17

17

(3,2)15

15

15

16

(5,5)10 10

14

12

17

13

(2,8)1014

17(2,10)8

(2,7)8

(6,5)5

(11,10)0

(3,3)10(5,2)8

(7,2)8

17

16

sa1

g

h(2,4)13

(2,4)13

0

0

0

0

D



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The following table gives the steps of PODEM (see Problem 7.5 for an explanationofX-path):

Step Objec- Action Imp. Implied signal values D XNo. tive stack ABCDEFghklmpqsruwZ front. path

1 g= 0(D) Backtrace C= 0 C= 0, h= 0 ok

2 g= 0(D) Backtrace D= 0 C= 0, D= 0, g = 0(D) noneC= 0 h= 0, k = 0, m= 0, u= 0

3 g= 0(D) Backtrack D= 1 C= 0, D= 1, g = 1, h= 0 noneC= 0 k = 1, m= 1, p= 0, q= 1, r= 0

4 g= 0(D) Backtrack C= 1 C= 1, g= 1, h= 1, m= 1 nonep= 0, q= 1, r= 0

5 g= 0(D) Backtrack Empty

Algorithm termination: g= 0(D) with X-path impossible; fault g s-a-1 is redundant.3 backtracks.

7.9 PODEM

The following figure and table show the SCOAP testability measures and the stepsof PODEM. See Problem 7.5 for an explanation ofX-path.

A

ls

Z

r

u

wq

p

k

m 10

B

C

D

E

F

(1,1)12

(1,1)16

(1,1)14

(1,1)16

(1,1)12

1,1 12

17

17

(3,2)15

15

15

16

(5,5)10 10

14

12

17

13(2,8)10 14

17(2,10)8

(2,7)8

(6,5)5

(11,10)0

(3,3)10(5,2)8

(7,2)8

17

16

g

h(2,4)13

(2,4)13

0

sa1

D

0

1

1

1

1

0

D

Step Objec- Action Imp. Implied signal values D XNo. tive stack ABCDEFghklmpqsruwZ front. path

1 C h= 0(D) Backtrace C= 0 C= 0, C h= D h ok

2 h= 0(D) Backtrace D = 1 C= 0, D= 1, C h= D, g = 1, k= 1 none

C= 0 h= D, m= 1, p= 0, q = 1, r = 0

3 h= 0(D) Backtrack D = 0 C= 0, D= 0, C h= D, g = 0, h= 0 noneC= 0 k= 0, m= 0, u= 0

4 C h= 0(D) Backtrack C= 1 C= 1, g= 1, h= 1, m= 1, p= 0 noneq = 1, s= 1, r= 0, w= 1

5 C h= 0(D) Backtrack Empty

Algorithm termination: C h= 0(D) with X-path impossible; faultC h s-a-1 is redundant.3 backtracks.



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7.10 FAN

The following figure showsthe SCOAP testability measures used for FAN. The head-lines are m and l .

A

ls

Z

r

u

wq

p

k

10

B

C

D

E

F

(1,1)12

(1,1)16

(1,1)14

(1,1)16

(1,1)12

1 1 12

17

17

(3,2)15

15

15

16

(5,5)10 10

14

12

17

(2,8)1014

17(2,10)8

(2,7)8

(6,5)5

(11,10)0

(3,3)10(5,2)8

(7,2)8

17

16

g

h(2,4)13

(2,4)13

13

m

0

sa0

D

1

0

0

Step 1: Goal set r = 1set A = p = 1set A = m = B = 0D-frontier =.Conflict at stem A, choose A = 1Forward implyA = 1, B = 0, p= 0, r= 0, fault r s-a-0 cannot be sensitizedisredundant (0 backtracks).

7.11 SOCRATES

The following figure shows the SCOAP testability measures used for SOCRATES.

A

ls

Z

r

u

wq

p

k

10

B

C

D

E

F

(1,1)12

(1,1)16

(1,1)14

(1,1)16

(1,1)12

1 1 12

17

17

(3,2)15

15

15

16

(5,5)10 10

14

12

17

(2,8)1014

17(2,10)8

(2,7)8

(6,5)5

(11,10)0

(3,3)10(5,2)8

(7,2)8

17

16

g

h(2,4)13

(2,4)13

m

13sa0

D

0

0

0

1

1

1

1

1



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Static learning

Signal Learned implication

B = 1 (w= 0)(B = 0)g= 0 (m= 1)(g= 1)C= 1 (h= 0)(C= 0)D= 1 (k= 0)(D= 0)

Step 1: Objective set m = 1Implication stack C= 1Assignments C= 1, g= 1, h= 1, m= 1, q= 1D-frontier pDynamic learning (k= 0)

(D= 0), (w= 0)

(l= 0)

Step 2: Objective set A = 0Implication stack A = 0, C= 1Assignments C= 1, g= 1, h= 1, m= 1, q= 1, A= 0, r= 0, u= 0X-path check fault propagation path blocked alternative assignment A = 1infeasibleFaultm p s-a-0 is redundant (no backtracks).No applications of Modus Tollens or constructive dilemma.

7.12 SOCRATES

The following figure shows the SCOAP testability measures used for SOCRATES.

A

ls

Z

r

u

wq

p

k

10

B

C

D

E

F

(1,1)12

(1,1)16

(1,1)14

(1,1)16

(1,1)12

1 1 12

17

17

(3,2)15

15

15

16

(5,5)10 10

14

12

17

(2,8)1014

17(2,10)8

(2,7)8

(6,5)5

(11,10)0

(3,3)10(5,2)8

(7,2)8

17

16

g

h(2,4)13

(2,4)13

m

13

0

1

1

sa0 D

1

1

D

D

D

1

1

D

0

0

0



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Static learning

Signal Learned implication

B = 1 (w= 0)(B = 0)g= 0 (m= 1)(g= 1)C= 1 (h= 0)(C= 0)D= 1 (k= 0)(D= 0)

Step 1: Objective set g = 1Implication stack C= 1Assignments C= 1, g= D, h= DD-frontier k, mDynamic learning (D= 0)

(m= D)

Step 2: Objective set D = 0Implication stack D = 0, C= 1Assignments C= 1, D= 0, g = D, h= D, k= 0, m= DD-frontier p,q, u

Step 3: Objective Propagate D to u, set A = 1Implication stack A = 1, D= 0, C= 1Assignments C = 1, D = 0, A = 1, g = D, h = D, k = 0, m = D, p = 0,r= 0, u= DD-frontier Z

Dynamic learning (B = 0)(q= D), (B = 1)(w= 1)(Z= D)Step 4: Objective Propagate D to Z, set w = 1

Implication stack B = 1, A= 1, D= 0, C= 1Assignments C = 1, D = 0, A = 1, B = 1, g = D, h = D, k = 0, m = D,

p= 0, r= 0, u= D, q= 1, s= 1, w= 1, Z=DUse learned implication (w= 0)(B = 0)Fault tested, no backtracks.No applications of Modus Tollens or constructive dilemma.



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7.13 D-ALG

Step Action Impl. stack Forward implications D-frontier

1 Fault act. h= 0 h= 0, h1 =D, i2 = 0 i1

2 D-prop. g1 = 1, h= 0 g1 = 1, h= 0, h1 =D POi1 =D, i2 = 0

3 Justify e1 = 1, g1 = 1 e1 = 1, g1 = 1, h= 0 POh= 0 h1 =D, i1 =D, i2 = 0

4 Justify a= 1, b= 1 a= 1, b= 1, e1 = 1, g1 = 1 POe1 = 1, g1 = 1 e2 = 1, g1 = 1, g2 = 1

h= 0 h= 0, h1 =D, i1 =Di2 = 0

Test found: (a,b,c,d,h,k) = (1, 1,X ,X , 0, X); i1 =D

The following figure shows the circuit and the signal values specified by D-algorithm.

1

1

0

1

0

11

Da2

i2

a

b

cd

h

k

a1

b1

c1

d1

b2

c2

d2

e2

f2

e1

f1

1

h2

g2

g1

h1Di1

j

sa1

This test is found without any backtracks.



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7.14 PODEM

Step Objective Impl. Forward implications D X(goal) stack frontier path

1 Fault act. h= 0 h= 0, h1 =D, i2 = 0 i1 ok

2 Fault prop. h= 0, a= 1 a= 1, h= 0, h1 =D i1 okg1 = 1 i2 = 0

3 Fault prop. h= 0, a= 1 a= 1, b= 1, e1 = 1 PO okg1 = 1 b= 1 e2 = 1, g1 = 1, g2 = 1

h= 0, h1 =D, i1 =Di2 = 0

Test found: (a,b,c,d,h,k) = (1, 1,X ,X , 0, X); i1 =D

The following figure shows the SCOAP testability measures used to guide thePODEM algorithm, and the signal values detremined.

1

1

0

1

1

Da2

a

b

c

d

h

k

b1

c1

d1

b2

c2

d2f2

f1

h2

g2

g1

h1Di1

j

(1,1)7

9

(1,1)7

(1,1)7

(1,1)7

(5,4)2e1 1

(2,3)5

(2,3)5

(1,1)5

1e2

(2,3)7

(2,3)7

(5,4)40

(2,6)2

i2

5

7

(2,6)0

(4,2)0

7

9

9

9

(1,1)3

7

7

7a

(CC0,CC1)CO

sa1

This test is found without any backtracks.



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7.15 FAN

The following figure shows the SCOAP testability measures used to guide the ATPG.The signal velues are those determined by the steps described below.

sa1

(2,3)8

(7,7)4 4(11,3)0

(14,6)0

(16,2)012

(5,5,)9

9

8

12

(4,4)7

11 6

D

DD

D

D

(1,1)10

(1,1)10

10

11

(1,1)15

0

0

7D

1

1

11

(8,8)6

(10,10)6

(2,3)8

h

e

f

m

p

lu

v

A

B

C

d

9g

kq

r

s

X

Y

Z

10

7

n

t

q

(CC0,CC1)CO

There are no headlines.

Step 1: Goal sensitize faultImplication stack B = 0

Implied signals B = 0, d = e = f = g = 0, h = l = 0, k = D, m = n = p=D, q= D, r= D, s= t = u = D, v= D, X= 1, Y = 1D-frontier Z

Step 2: Goal propagate fault to ZImplication stack B = 0, C= 1Implied signals B = 0, C = 0, d = e = f = g = 0, h = l = 0, k = D,m= n = p = D, q= D, r= D, s= t = u = D, v= D, X= 1, Y = 1, Z= 1D-frontier emptySensitization and propagation conditions do not intersect. Hence, the fault isproved redundant in two steps without any backtracks.



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7.16 FAN

The signal values determined by FAN are shown below. The figure also shows theSCOAP testability measures. In this case there are no headlines.

1

1

0

1

1

Da2

a

b

c

d

h

k

b1

c1

d1

b2

c2

d2f2

f1

h2

g2

g1

h1Di1

j

(1,1)7

9

(1,1)7

(1,1)7

(1,1)7

(5,4)2e1 1

(2,3)5

(2,3)5

(1,1)5

1e2

(2,3)7

(2,3)7

(5,4)40

(2,6)2

i2

5

7

(2,6)0

(4,2)0

7

9

9

9

(1,1)3

7

7

7a

(CC0,CC1)CO

sa1

Steps 1 and 2: Goal sensitize fault and propagate it to i1

Implication stack h = 0, g1 = 1Implied signals g1 = 1, h= 0, i1 =D, i2 = 0D-frontier (fault effect at PO)

Step 3: Goal set e1 = 1a = 1 and b = 1Implication stack h = 0, g1 = 1, a= 1, b= 1Implied signals a = 1, b = 1, e1 = 1, e2 = 1, g1 = 1, g2 = 1, h = 0, i1 =D, i2 = 0D-frontier (fault effect at PO)

Goal satisfied, test for fault h1 s-a-1 is (a,b,c,d,h,k) = ( 1, 1,X ,X , 0, X),i1 =D; no backtracks were required.



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7.17 SOCRATES

To obtain a test for the fault n s-a-1 in the circuit of Figure 7.24 (see page 190 ofthe book and the figure below), we perform static learning:

Signal Learned implications Signal Learned implications

B = 0 (m= 0)(B = 1) X= 0 (r= 1)(X= 1)(q= 1)(B = 1) (Y = 1)(X= 1)(r= 1)(B = 1) (v= 1)(X= 1)(s= 0)(B = 1) (q= 1)(X= 1)(v= 1)(B = 1) (s= 1)(X= 1)

(m= 0)(X= 1)d= 1 (m= 0)(d= 0) Y = 0 (X= 1)(Y = 1)

(q= 1)(d= 0) (v= 1)(Y = 1)(r= 0)(d= 0) (r= 0)(Y = 1)(s= 1)(d= 0) (d= 0)(Y = 1)

(X= 1)(d= 0) (m= 0)(Y = 1)(Y = 1)(d= 0)(v= 1)(d= 0)(Z= 0)(d= 0)

Z= 1 (q= 1)(Z= 1)

Step 1: Goal sensitize fault, m = 0

Static learning B = 1Implications d = 0, X = 1, Y = 1, A = 0, r = D, q = 1, m = 0, s = D,v= D, Z= 1D-frontier (null)Redundant fault, because D-frontier vanishes at gate Z, no decision alterna-tives. No need for dynamic learning, no use of the constructive dilemma orModus Tollens. No backtracks.

(2,3)8

(7,7)4 4(11,3)0

(14,6)0

(16,2)012

(5,5,)9

solutions to problems from essentials of electronic testing

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