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VHDL

VHDL stands of VHSIC (Very High Speed Integrated Circuit) Hardware Description Language.It was designed with the principles of structured programming. It allows you to define theinterface of a hardware module and hide its internal details. VHDL Entity is the declarationof module’s inputs and outputs. VHDL Architecture is a detailed description of the module’sinternal structure of behavior.

Program Structure

The structure of a typical VHDL program is listed below. It begins with a library declara-tion followed by ENTITY and ARCHITECTURE sections. Entity defines the interface whileArchitecture defines the real hardware.

LIBRARY ;Package ;

ENTITY Entity_name IS −− I n t e r f a c e o f ModulePORT ( input1 , input2 : IN type ; −− Read onlyio1 , i o2 : INOUT type ; −− Both input and ouput . Read and Writebuf1 , buf2 : BUFFER type ; −− Output , a l s o can be read i n s i d e a r c h i t e c t u r eouput1 , output2 : OUT type ) ; −− Write only

END Entity_name ;

ARCHITECTURE Arch_name OF Entity_name IS −− Module ’ s I n t e r an l St ruc ture

TYPE de c l a r a t i o n s ; −− You can de f i n e your own data typesSIGNAL de c l a r a t i o n s ; −− Used to in t e r connec t b/w componentsCONSTANT de c l a r a t i o n s ; −− Constant . Can ’ t be changedFUNCTION d e f i n i t i o n s ; −− Takes many inputs and re tu rn s a s i n g l e va luePROCEDURE d e f i n i t i o n s ; −− Takes many inputs and r e t u r e s many va luesCOMPONENT de c l a r a t i o n s ; −− Sub Module whom you gonna c a l l from th i s module

BEGIN

assignment o f Boolean eqns or c ond i t i o na l statements ; −− Data Flow Designi n s t a n t i a t i o n o f components ; −− St ruc tu ra l Designproce s s d e f i n i t i o n −− Behaviora l Desc r ip t i on

END Arch_name ;

TYPES

All signals, variables, and constants in a VHDL program must have an associated “type”. Thetype specifies the set or range of values that the object can take on, and there is also typically aset of operators associated with a given type. The predefined types are listed below.

• BIT : single binary data, can take value 0 or 1

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• BIT_VECTOR: multiple bit binary data. BIT_VECTOR(N-1 downto 0) / BIT_VECTOR(1to N) specifies an N-bit binary data.

• BOOLEAN: single bit, can take value TRUE or FALSE

• INTEGER: can specify integer data types. Its value-range depends upon the compiler ie.−2N−1 + 1 to 2N−1

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• CHARACTER: 8-bit character set

The most commonly used types in typical VHDL programs are user-defined types, and the mostcommon of these are enumerated types, which are defined by listing their values. Among theabove specified predefined types, BOOLEAN and CHARACTER are enumerated types. Foran enumerated type, the value-list may be user identifiers or 8-bit characters. The format forenumerated type declaration is below.TYPE my_enum_type is (value-list);Value-list is a comma-separated list of all possible values of the type. The values may be

user-defined identifiers or characters.In standard library, BOOLEAN and STD_ULOGIC are defined as

BOOLEAN STD_ULOGIC

TYPE BOOLEAN IS (’TRUE’, ’FALSE’); TYPE STD_ULOGIC IS (’U’, ’X’,’0’,’1’,’Z’,’W’,’L’,’H’,-’);example for enumerated type: type traffic_light_state is (reset, stop, wait, go);

Subtypes

VHDL allows users to create subtypes of a type. The values in the subtype must be a contiguousrange of values of the base type. Natural and positive are predefined integer subtypes.

subtype subtype_name is type_name start to end; subtype subtype_name is type_name start downto end;

subtype twoval_logic is std_logic range ’0’ to ’1’; subtype fourval_logic is std_logic range ’X’ to ’Z’;subtype negint is integer range -2147483647 to -1; subtype bitnum is integer range 31 downto 0;subtype natural is integer range 0 to highest-integer; subtype positive is integer range 1 to highest-integer;

Arrays

Array is an ordered set of elements of the same type, where each element is selected by an arrayindex.

Syntax Example

type type_name is array (start to end)of element-type;

type monthy_count is array (1 to 12) of integer;

type type_name is array (start downtoend) of element-type;

type byte is array (7 downto 0) of integer;

type type_name is array (range_type)of element-type;

constant WORD_LEN: integer:=32; type bus isarray (WORD_LEN-1 downto 0) of integer;

type type_name is array (range_typerange start to end) of element-type;

type myarr is array (integer range 0 to 15) ofinteger;

type type_name is array (rang_typerange start downto end) of

element-type;

type myarr is arry (integer 31 downto 0) of integer;

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Programming Styles

VHDL is having three different styles of coding.

Dataflow Model

In this style, concurrent signal assignment statement or conditional statement are used to realizea logic function. All assignments are executed in parallel.

Syntax Example: Full Adder

Arch i t e c tu re My_Arch o f My_Ent i ss i g n a l d e c l a r a t i o n s ;beginconcurrent statements ;x<= l o g i c funt i on ( inputs , s i g n a l s ) ;end My_Arch ;

Ent ity FA i s port (A,B, Cin : in STD_LOGIC;S , Cout : out STD_LOGIC) ;end FA;Arch i t e c tu re Arch_FA of FA i sbeginS<= A xor B xor Cin ;Cout<= (A and B) or(B and Cin ) or (A and Cin ) ;end Arch_FA;

Syntax Examples

Arch i t e c tu re Arch_name o f Ent_name i sbeginsignal_name<= expr when boolean expr e l s e

expr when boolean expr e l s e. . . . . . . . . . .. . . . . . . e l s e

expr ;End Arch_anme ;

Entity MUX4to1 i s port(A,B,C,D : in s td_log i c ;S : in std_log ic_vector (1 downto 0 ) ;Y: out s td_log i c ) ;End MUX4to1 ;Arch i t e c tu re Arch_MUX of MUX4to1 i sbeginy<= A when S="00" e l s e

B when S="01" e l s eC when S="10" e l s eD;

end Arch_MUX;

Arch i t e c tu re Arch_name o f Ent_name i sbeginwith exp r e s s i on s e l e c tsignal_name<= signa l_va lue when choice1 ,

s igna l_va lue when choice2 ,. . . . . . . . . .s inga l_va lue when othe r s ;

End Arch_anme ;

Entity MUX4to1 i s port(A,B,C,D : in s td_log i c ;S : in std_log ic_vector (1 downto 0 ) ;Y: out s td_log i c ) ;End MUX4to1 ;Arch i t e c tu re Arch_MUX of MUX4to1 i sbeginwith S s e l e c tY<= A when "00" ,

B when "01" ,C when "10" ,D when othe r s ;

end Arch_MUX;

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Structural Model

In this model, the sub-modules are instantiated from the architecture body of the main module.Port map, Generate and Generic are the important design elements in this style.

• Port map is used to instantiate a sub-module. You can use either implicit (positional) orexplicit (using =>) port mapping. For positional port mapping the order of signals in thecomponent definition should be followed. For explicit mapping you can take any order.

• Generate is used to instantiate multiple copies of same structure.

• Generic : using Generic you can compile an entity and its architecture while leaving someparameters like bus width, array size etc.

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syntax example: Three Bit Adder

Arch i t e c tu re Arch_name o fEnt_name i scomponent d e c l a r a t i o n s ;s i g n a l d e c l a r a t i o n s ;begin− − d i r e c t mapingl ab e l 1 : component_nameport map(a , b , c ) ;− − p o s i t i n a l mapingl ab e l 2 : component_name portmap( a=>a , b=>b , c=>c ) ;End Arch_name ;

Entity TB_adder i s port (A,B : in std_log ic_vector (2 downto 0 ) ;Y: out std_log ic_vector (3 downto 0 ) ) ;End TB_adder ;

Arch i t e c tu re Arch_TB of TB adder i scomponent FA i s port (A,B, Cin : in s td_log i c ;S , Cout : out s td_log i c ) ; end component ;s i g n a l C : std_log ic_vector (2 downto 1 ) ;begin

IN1 : FA port map(A=>A(0 ) ,B=>B(0 ) ,Cin=>’0 ’ ,S=>Y(0 ) , Cout=>C( 1 ) ) ;

IN2 : FA port map(A=>A(1 ) ,B=>B(1 ) ,Cin=>C(1 ) , S=>Y(1 ) , Cout=>C( 2 ) ) ;

IN3 : FA port map(A=>A(2 ) ,B=>B(2 ) ,Cin=>C(2 ) , S=>Y(2 ) , Cout=>S ( 3 ) ) ;

end Arch_TB;−− or you can do l i k e t h i s a l s o .− −Both g ive same c i r c u i tINST1 : FA port map(A(0 ) ,B( 0 ) , ’ 0 ’ ,Y(0 ) ,C( 1 ) ) ;INST2 : FA port map(A(1 ) ,B(1 ) ,C(1 ) ,Y(1 ) ,C( 2 ) ) ;INST3 : FA port map(A(2 ) ,B(2 ) ,C(2 ) ,Y(2 ) , S ( 3 ) ) ;

Syntax f o r Generate

Arch i t e c tu re Arch_name o fEnt_name i scomponent d e c l a r a t i o n s ;s i g n a l d e c l a r a t i o n s ;beginLabel : f o r i d e n t i f i e r in range

generateconcurrent−statement ;end generate ;

End Arch_name ;

Entity TB_adder i s port (A,B : in std_log ic_vector (2 downto 0 ) ;Y: out std_log ic_vector (3 downto 0 ) ) ;End TB_adder ;

Arch i t e c tu re Arch_TB of TB adder i scomponent FA i s port (A,B, Cin : in s td_log i c ;S , Cout : out s td_log i c ) ; end component ;s i g n a l C : std_log ic_vector (3 downto 0 ) ;begin

C(0) <= ’0 ’;GEN: f o r i in 0 to 2 generateINT : FA port map(A( i ) ,B( i ) ,C( i ) ,Y( i ) ,C( i +1)) ;end generate ;Y(3)<= C( 3 ) ;end Arch_TB;

− −OR you can use cond i t i on s i n s i d e generate

GEN: f o r i in 0 to 2 generatei f ( i=0 or i =1) thenINT : FA port map(A( i ) ,B( i ) ,C( i ) ,Y( i ) ,C( i +1)) ;e l s e− − Y(3)<= C( 3 ) ;INT : FA port map(A( i ) ,B( i ) ,C( i ) ,Y( i ) ,Y( i +1)) ;end generate ;