some trends in high-level synthesis research tools tanguy risset compsys, lip, ens-lyon
TRANSCRIPT
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Some Trends in High-level Synthesis Research Tools
Tanguy Risset
Compsys, Lip, ENS-Lyonhttp://www.ens-lyon.fr/COMPSYS
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Outline
• Context: Why High level synthesis?
• HLS Hard problems
• Some solution in existing tools
• Some on-going projects
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Context: Embedded Computing Systems design
• SoC or MPSoC for multimedia application will soon includes: Network on chip dozens of initiators (CPU, DMA,…) Mbytes of code Operating systems Shared memory coherency protocols …
• SoC Design problems: Time to market Design space exploration Software complexity
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Some envisaged solutions
• Time to market IP re-use High level design
• Design space exploration Fast prototyping and performance evaluation, refinement
methodology (specification, algorithm, TLM, CABA)
• Software complexity Tools for embedded code generation/embedded OS
• High level synthesis is only a small part of the « High level Design » process
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Definition of High Level Synthesis
• HLS: Generates register-transfer level description from behavioral specification, in an automatic or semi-automatic way.
• Input: A behavioral specification Design constraints Library of available RTL components
• Output: RTL description Performance evaluations
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IP block design
System application design
Refinement : from algorithm to hardware• MatlabMatlab• CC
block implementation • RTL SynthesisRTL Synthesisblock implementation • RTL SynthesisRTL Synthesis, VHDL, Verilog, VHDL, Verilog
block specification
algorithmic explorationalgorithmdomain
SoC platform design
abstract architecture
virtual prototype
TransactionLevel
Modeling
• SoC Intermediate RepresentationSoC Intermediate Representation
ArchitectureDescriptionLanguage
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Abstraction levels for HLS
• AL = Algorithm prior to HW/SW partition
• TLM = Transaction-Level Model after HW/SW partition models bit-true behavior, register bank, data transfers, system synchronisation no timing needed
• T-TLM= Timed TLM (also PVT) TLM + timing annotation refined communication model
• CABA = Cycle Accurate-Bit Accurate models state at each clock edge
• RT = Register Transfer (ASIC flow entry point) synthesisable model
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Pro’s and Cons
• « Traditional » motivations: Fast design Safe design : formal refinement approach « Must be used » to cope with Moore’s law
• But! Commercial tools are not here A new tool is a big investment Designers have managed without it
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New motivations ?
• IP-reuse Slightly change design parameter for re-using IP
• New target technologies and languages (FPGA, SystemC, etc.) Tools can easily re-target the designs
• CAD tools companies are investing a lot in « high level-like » synthesis tools Monet, Behavioural compiler, VCC, …
• Technological advantage Traditional RTL design will be de-localized to Asia
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Outline
• Context: Why High level synthesis?
• HLS Hard problems
• Some solution in existing tools
• Some on-going projects
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HLS Hard Problems
• Huge design space Complex design space exploration Multi-criteria optimization techniques
• Integration into a design environment Lack of standard interchange format SoC simulation time is a crucial issue
• Acceptance by the designers Find a language common to SoC designers and tools designer
• Refinement technical problems (detailed hereafter)
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HLS technical problems
• Compilation occurs when the target architecture is precisely known
• In HLS, target architecture is only partially specified, Examples: Data-flow architecture/systolic arrays : pure RTL description FSM+data path : closer to processor description
• HLS technical problems : Initial specification format / language Specification refinement : fixed point arithmetic Scheduling/Mapping refinement: resource constraints Technological Mapping refinement
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Initial specification format
• Restriction on the input language expressivity are necessary
• … but designers hate new languages
• C-like language (handel-C, silicon-C,hardware-C, etc…) are actually hardware description languages
• Main problems: How to express parallelism/sequentially
- Data-flow, CSP-like, process network, event-driven
How to express both algorithmic and RTL description How much expressivity
- Dynamic control, loops
How to introduce constraints/hints
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Fixed point arithmetic
• Problem: translate a floating point computation to fixed point computation
• Most of the tools start with an initial fixed point specification found by extensive simulation.
• Automatic techniques are not handling loops
• In the case of signal processing application the signal processing theory can help (transfer function used to compute signal-to-noise ratio).
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Scheduling/Mapping
• For a « basic bloc », resource constraints scheduling is NP-Hard, but widely studied.
• Computations Currently, two way to handle loops:
- Unroll them- Keep them sequential
Other solutions:- Use software pipelining theory- Use the polyhedral model
• Memory and communication Memory mapping is usually strongly guided by the user
- Highly active research field (Catthoor, Darte) Communication refinement is also an important issue
- Highly dependent on the chosen computation model (Gajski, Kenhuis)
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Technological mapping refinement
• Fine technological mapping are very target-dependent
• Predefined libraries are not precise enough Delays on wires Power consumption
• VLSI designers « tricks » are difficult to integrate in tools
• Sub-Micronics technologies constraints are changing too fast for high level tools Cross talk Capacitance
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Outline
• Context: Why High level synthesis?
• HLS Hard problems
• Some solution in existing tools
• Some on-going projects
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Some solution in existing tools
• Digital signal processing circuits: Gaut: http://lester.univ-ubs.fr:8080 Source: signal processing (one infinite loop) Target: RTL + FSM
• FSM+datapath Ugh: http://www-asim.lip6.fr/recherche/disydent/ Source: restricted C Target: FSM+data path
• Regular computation and polyhedral Model MMAlpha: http://www.irisa.fr/cosi/ALPHA/ Source : functional specification Systolic like architectures
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GAUT:Génération Automatic d’Unité de Traitement
• Developed first at LASTI (Lannion) and then LESTER (Lorient): free• Generate RTL description from behavioral description for signal
processing algorithm• Kernel technology: highly optimized ressource constraint scheduling• Inputs are
- a behavioral VHDL description (one process repeated infinitely)
- Libraries of operators pre-characterized- Some design constraints
• Outputs are - a synthesizable RTL VHDL description (data path, memory,
and communication units)- Gantt chart for I/O specification
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Compiling-analyzing-loop unrolling
Synthesis-selection-SchedulingMapping
Behavioral descriptionVHDL
Operator library
RTL description(data path+control)
graph
Memory and IO specifications
.src .lib
.gc
.vhd .mem
Gaut design flow
User constraints:Latency, clock frequency
Operators, Alloc,etc.
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Gaut : VHDL Input code
• Sequential instruction in one single process (no clock, no reset, no sensitivity list)
ENTITY fir ISPORT (xn:IN INTEGER; yn:OUT INTEGER);
END fir;
ARCHITECTURE behavioral OF fir IS...
BEGINPROCESS
VARIABLE H,x: vecteur;VARIABLE tmp: INTEGER;VARIABLE i: CONTROL;
BEGINtmp := xn * H(0);FOR i IN 1 TO N-1 LOOP
tmp := tmp + x(i) * H(i);END LOOP;yn <= tmp;FOR i IN N-1 DOWNTO 2 LOOP
x(i) := x(i-1);END LOOP;x(1) := xn;WAIT FOR cadence;
END PROCESS;END behavioral;
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Gaut : Input code
• Types Bit, boolean, std_logic, Integer (single size), Bit_Vector,
Std_Logic_Vector Arrays (to be inlined)
• Sequential instructions Signal and variables assignment Only one level of if For and While loops (to be inlined) Procedure calls (to be inlined) Function calls corresponding to library elements
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Gaut step1: Source code transformation
• Control dependence elimination Loop unrolling
y ( 0 ) := x ( 0 ) * h ( 0 ) ; y ( 0 ) := x ( 0 ) * h ( 0 ) ;
for i in 1 to n - 1 loop y ( 1 ) := y ( 1 - 1 ) + x ( 1 ) * h ( 1 );
y ( i ) := y ( i - 1 ) + x ( i ) * h ( i ) ; y ( 2 ) := y ( 2 - 1 ) + x ( 2 ) * h ( 2 ) ;
end loop ; y ( 3 ) := y ( 3 - 1 ) + x ( 3 ) * h ( 3 ) ;
Procedure inlining
Static single assignmentb := x + z ; b := x + z ;a := b + c ; a := b + c ; b := e + f ; b0001 := e + f ;y := b; y := b0001;
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Gaut step1: Source code transformation
• Simple expression generationb := x + z * u ; tmp := z * u ;
b := x + tmp ;
• Constant propagation • Generation of GC Graph (Data-Flow Graph Format of Synchronous
Programming)
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GAUT step 2: Scheduling/Mapping
• In addition to throughput and clock cycle, the user can give: Ressource constraints and mapping constraints Memory constraints I/O constraints Optimization type
• The result is an architecture and a GANTT charts For computations For I/O For memory
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Gaut step 3: memory and communication synthesis
• Optimizing memory layout and minimizing busesA
SIC
I/O
Communication unit
Datapath Memory unit
Control
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Gaut: summary
• Advantages Advanced development status (still research tool) User guided synthesis Open library Active research team: memory optimization, communication
synthesis
• Drawbacks Loop flattening (complexity problem) Predefined timing characteristics Hard to get out of 1D signal processing
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Ugh: User Guided High Level Synthesis
• Developed at LIP6 (Paris), as part of the Disydent project (Digital System Design Environment): open source
• Behavioral level synthesis tool for control dominated coprocessor• Emphasis on precise timing estimation• Kernel technology: ressource constraint scheduling and (GNU-like) compiler
construction technology• Inputs are
- a C or VHDL behavioral description with KPN communication primitives
- a draft data-path- a cycle time constraint TC
• Outputs are - a synthesizable RTL VHDL model- a cycle accurate simulation model
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Coprocessor System Environment
Bus
unit
Coprocessor
Processor
R3000
ICache DCache
PI-BUS
RAM
Controller
M/S Interface
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UGH Structure
AnnotationsTiming
Caba simulationData-Path + FSM Model
Synthesis +Characterization
UGH-FGSUGH-CGS
Data-Path
Draft
VHDL
Ugh C
FSM/CVHDL
Data-Path
CellLibrary
Depends on theSynthesis tool
VHDL
CK
Coarse grain scheduler
Fine grain scheduler
(Synopsys)
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Input 1 : UGH-C
•Library IEEE;•Useieee.std_logic_arith.all;•entity HCF is •port (CK : in bit;• DINA : in integer;• READA : out bit;• ROKA : in bit;• DINB : in integer;• READA : out bit;• ROKA : in bit;• DOUT : out integer;• WRITE : out bit;• WOK : int bit);•end HCF;
#include <ughc.h>ugh_inChannel32 work2hcfa;ugh_inChannel32 work2hcfb;ugh_outChannel32 hcf2work;uint32 a,b;void hcf(void){
while (a != b)if (a < b) b = b - a;else a = a - b;
}int ugh_main(){
while (1) {channelRead(work2hcfa,&a);
channelRead(work2hcfb,&b);hcf();channelWrite(hcf2work,&a);
}}
C Description
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Input 2 : Draft Data-path
S
b
QD
a
D Q
Subst
A
B
work2hcfa
model Hcf(sofifo hcf2work; sififo work2hcfa, work2hcfa)
{DFFl a, b;SUB subst;
subst.A = a.Q, b.Q;subst.B = a.Q, b.Q;
a.D = subst.S, work2hcfa;b.D = subst.S, work2hcfb;
hcf2work= subst.S;} w
ork2hcfb
hcf2work
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OUTPUT 1 : Refined Data path
zi0
i1d
i1
i0
qdzi0
i1z
i1
i0a
s
b
z
q z op
coRegA
RegB
M2
M1
M3
M4 Subst
sel_m1 we_ra sel_m4 inf zero
op_substsel_m3we_rbsel_m2ck
dinb
dina
dout
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OUTPUT 2 : FSM for control
IF
S1 S2
RESET
READY
READA
READB
START
ROKA
ROKB
START
RESET
RESET
ROKA ROKB
WRITE
WOK
WOK
WHILE
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Ugh summary
• Advantages Precise timing information Multi cycle operation Almost a compiler approach (restricted target architecture) Interfacing (Integrated in a SoC design environment)
• Drawbacks Development status (research tool) Low level information given by the user Highly dependent on commercial tool (synopsys) Dedicated to control oriented applications
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MMAlpha
• Developed in Irisa (Rennes): open source
• High level synthesis of highly pipelined accelerators
• Kernel technology: polyhedral model and systolic design methodology
• Emphasis on loop transformations
• Input : functional specification (Alpha langage)
• Output : RTL description of systolic-like architecture (Alpha or VHDL)
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C
For i=1:1:NFor j=1:1:N
Alpha
FPGA
host
busUniformization
RTL derivation
SchedulingVHDL
VHDL
C
C
C
MMAlpha design flow
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What is polyhedral model?
• Abstract a loop nest by the polyhedron described by the loop indices during execution of the loop
• Can be used for any index-based structure : memory (arrays), communications (accesses), etc…
• example: convolution (FIR filter)
1
0
)()()(N
n
nixnHiy
for (i=N; i<=M; i++) { y(i)=0; for (n =0; n<=N-1; j++)) {
y(i)=y(i)+H(n)x(i-n)}}
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FIR: iteration space
H(N-1)
H(0)
y(N)
y(N+1)
0 0
x(N) x(N+1)
i
n
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FIR polyhedral representation (MMAlpha input language)
H(N-1)
H(0)
y(N)
y(N+1)
0 0
x(N) x(N+1)
i
n
]H[n]*x[i-n]Y[i,nY[i,n]NnMiNni 1 10 ;,
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MMAlpha polyhedral scheduling
H(N-1)
H(0)
y(N)
y(N+1)
0 0
x(N) x(N+1)
t=4 5 6
i
n
]H[n]*x[i-n]Y[i,nY[i,n]NnMiNni 1 10 ;,
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MMAlpha space time transformation
p]H[p]*x[t-],pY[tY[t,p]NpMNptppt 211 10 ;,
H(N-1)
H(0)
y(N)
0 0
x(N) x(N+1)t=4 5 6
t
p
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MMAlpha mapping p]H[p]*x[t-],pY[tY[t,p]NpMNptppt 211 10 ;,
H(N-1)
H(0)
y(N)
0 0
x(N) x(N+1)t=4 5 6
t
p
H
0
y
x
i
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MMAlpha resulting architecture
x(n-2N+D+1)
w w1 2
y(n)
x(n-2N+2)
w
w N-1
p=1 p=N-1
0w
y(n)
d(n)
p=0
x(n+D-1)
D-1 x(n)
e(n-N+1)
+-
e(n)
N-1
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MMAlpha current features
• Tool box for designers: Powerful analyze tools Pipelining, Change of basis, multi-dimensionnal scheduling,
control signal generation. Code generation (C, VHDL) Hierarchical design methodology
• Work in progress: Ressource constraint scheduling (extention to Z-polyhedra) Multi-dimensionnal scheduling and memory synthesys
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MMAlpha summary
• Advantages Design tool integrating loop transformation Parameterised design (N: size of the filter not fixed until VHDL
generation) Formal approach for refinement (functional to operational) A real language that syntactically captures HLS input restriction
• Drawbacks Does not yet handle resource constraints A language (Alpha) and design methodology very different from
designer’s habits Implementation status (research tool)
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Some Design results
• Ugh compares IDCT with CoWare and Gaut but the results are highly dependent upon design parameters
• MMAlpha demonstrates real implementation on FPGA co-processor board (DLMS algorithm)
Ck period (ns) #cycle execution
Exec time (µs)
Area (mm^2) Area (#inverter)
Manual (time optimised)
10.41 118 1.228 N-A 242.1
CoWare 21 1 645 34.545 19.94 165.6
Gaut 17.5 526 9.2 19 123.5
Ugh 17 1 466 25.922 10.9 70.9
8 tap DLMS filter Area Clk cycle Synthesis time
MMAlpha 2600 slices 35MHz 112 s
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Outline
• Context: Why High level synthesis?
• HLS Hard problems
• Some solution in existing tools
• Conclusion and on-going projects
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HLS conclusion
• HLS tools are not mature enough to produce the famous « C-to-VHDL » magic tool
• Most tool designer agree that a highly « user guided » approach is mandatory
• CAD tools are still actively developping tools (Mentor: Catapult-C, CoWare: Cocentric….)
• Some progress have been made Domain specific constraints are more clearly identified (control
oriented or data flow) Interfacing is studied together with the synthesis Fast simulation is an important issue addressed by HLS tools
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On-going project: Data-Flow IP interface
• Gaut (Lester) and MMAlpha (Irisa, Lip) are developing a common interface for their IPs (data-flow Ips)
VCI
I_FIFO 1
I_FIFO 2
O_FIFO1
O_FIFO2
CTRL
CTRL
IN
OUT
inputpatterns
patternsoutput
Dat
aflo
w H
ardw
are A
ccel
erat
or
Net
wor
kG
ener
ic
VCI
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On-going project: SocLib
• SocLib environment Public domain systemC simulation models for SoC IP:
- Cycle-accurate hardware simulation
- TLM Simulation
VCI interconnection standard French open academic initiative (should become European through
EuroSoc):http://soclib.lip6.fr/
• Typical platform:
prog
VCI Cache
MIPS
RAM TTY DMA
prog.c
GCC-MIPS
MIPS exec
prog boot
VCI Cache
MIPS
VCI Cache
MIPS
VCI VCI
ASIC
VCI Cache
MIPS
Bus / Network on chip (SPIN)
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On-going project: Loop transformation for compilation
• Unified loop nest transformation framework for optimization of compute/data intensive programs (Alchemy Inria project: http://www-rocq.inria.fr/~acohen/software.html).
• WRaP-IT: and Open-64/ORC Interface tool
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Thanks• Slides with Help from Lester, LIP6
• Here are some tools I did not talk about: Amical, Cathedral, High2, RapidPath, Flash, A/RT, Compaan, Syndex, Phideo, Bach, SPARK, CriticalBlue, Chinook, SCE, CodeSign, Esterel, precisionC, Polis, Atomium, Ptolemy, Handel-
C, Cyber, Bridge, MCSE, Madeo, SpecC, and many more….
Any Questions ?