southampton: oct 99asynchronous circuit compilation- 1 amulet3-h n asynchronous macrocell arm...
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Southampton: Oct 99 Asynchronous Circuit Compilation- 1
AMULET3-H
Asynchronous macrocell• ARM compatible processor core• Full custom RAM• Compiled ROM• Balsa compiled DMA controller• Test I/F, synchronous and off-chip bus
bridges Synchronous peripherals
• Designed by commercial partner ...
Southampton: Oct 99 Asynchronous Circuit Compilation- 2
AMULET3 System
CPU / RAM
ROM DMAC
Periph1Periph1 Periph1Periph1 Periph1Periph1
Syn
c br
idge
MARBLE SOCB
Southampton: Oct 99 Asynchronous Circuit Compilation- 3
DMA Local RAM Access
CPU / RAM
ROM DMAC
Periph1Periph1 Periph1Periph1 Periph1Periph1
Syn
c br
idge
MARBLE SOCB
Southampton: Oct 99 Asynchronous Circuit Compilation- 4
DMA Peripheral Accesses
CPU / RAM
ROM DMAC
Periph1Periph1 Periph1Periph1 Periph1Periph1
Syn
c br
idge
MARBLE SOCB
DMA requests
Southampton: Oct 99 Asynchronous Circuit Compilation- 5
Requirements / Specification
16 clients, 32 channels 3 channel types - complicated register
structure Programmable client channel
1 many mapping Support synchronous requests Transfers mostly between synchronous
clients
Southampton: Oct 99 Asynchronous Circuit Compilation- 6
Controller Structure
Target (Slave)
DMAregisters
Transferengine
MARBLE bus
DMA_rq[n]
MARBLE domain
interface
Arbitration
async control
Address
Data
AddressData
synchronousisland
self timedregion
Channel
DMA_irq/DMA_fiq
DMA controller
Initiator (Master)interface
Address Data
SOCB clock
Client Requests
request reset
Requests
DMA SPI(sync control)
Transferengine
Southampton: Oct 99 Asynchronous Circuit Compilation- 7
TI mem
RB Regs
R W
W R
+ R W +
R W
client req client req
Target (Sla ve)
DMAregisters
Transferengine
DMA_rq[n]
interf ace
Arbitration
async control
Address
Data
AddressData
synchronousisland
self timedregion
Channel
DMA_irq/DMA_fiq
DMA controller
Initiator (Master)interf ace
Address Data
SOCB cloc k
Client Requests
request reset
Requests
DMA SPI(sync control)
Transferengine
Operation
Request arrives
Southampton: Oct 99 Asynchronous Circuit Compilation- 8
TI mem
RB Regs
R W
W R
+ R W +
R W
client req client req
Target (Sla ve)
DMAregisters
Transferengine
DMA_rq[n]
interf ace
Arbitration
async control
Address
Data
AddressData
synchronousisland
self timedregion
Channel
DMA_irq/DMA_fiq
DMA controller
Initiator (Master)interf ace
Address Data
SOCB cloc k
Client Requests
request reset
Requests
DMA SPI(sync control)
Transferengine
Operation
TE signals RB
Southampton: Oct 99 Asynchronous Circuit Compilation- 9
TI mem
RB Regs
R W
W R
+ R W +
R W
client req client req
Target (Sla ve)
DMAregisters
Transferengine
DMA_rq[n]
interf ace
Arbitration
async control
Address
Data
AddressData
synchronousisland
self timedregion
Channel
DMA_irq/DMA_fiq
DMA controller
Initiator (Master)interf ace
Address Data
SOCB cloc k
Client Requests
request reset
Requests
DMA SPI(sync control)
Transferengine
Operation
RB returns address/count
Southampton: Oct 99 Asynchronous Circuit Compilation- 10
TI mem
RB Regs
R W
W R
+ R W +
R W
client req client req
Target (Sla ve)
DMAregisters
Transferengine
DMA_rq[n]
interf ace
Arbitration
async control
Address
Data
AddressData
synchronousisland
self timedregion
Channel
DMA_irq/DMA_fiq
DMA controller
Initiator (Master)interf ace
Address Data
SOCB cloc k
Client Requests
request reset
Requests
DMA SPI(sync control)
Transferengine
Operation
TE performs transfer
Southampton: Oct 99 Asynchronous Circuit Compilation- 11
TI mem
RB Regs
R W
W R
+ R W +
R W
client req client req
Target (Sla ve)
DMAregisters
Transferengine
DMA_rq[n]
interf ace
Arbitration
async control
Address
Data
AddressData
synchronousisland
self timedregion
Channel
DMA_irq/DMA_fiq
DMA controller
Initiator (Master)interf ace
Address Data
SOCB cloc k
Client Requests
request reset
Requests
DMA SPI(sync control)
Transferengine
Operation
Addresses are incremented
Southampton: Oct 99 Asynchronous Circuit Compilation- 12
TI mem
RB Regs
R W
W R
+ R W +
R W
client req client req
Target (Sla ve)
DMAregisters
Transferengine
DMA_rq[n]
interf ace
Arbitration
async control
Address
Data
AddressData
synchronousisland
self timedregion
Channel
DMA_irq/DMA_fiq
DMA controller
Initiator (Master)interf ace
Address Data
SOCB cloc k
Client Requests
request reset
Requests
DMA SPI(sync control)
Transferengine
Operation
TE returns count/addr to RBRB resets request signals
Southampton: Oct 99 Asynchronous Circuit Compilation- 13
Two Controller Descriptions
Sequential (previous slides)• Very simple control flow• Requires two passes through register bank• Slow!, Only memory decoupling helps
Parallel (next slides)• Decouple TE actions from memory R/W
with a new unit: Transfer Interface• Interrupt the register bank on end of
transfer
Southampton: Oct 99 Asynchronous Circuit Compilation- 14
Controller Structure
Target (Slave)
DMAregisters
Transferengine
MARBLE bus
DMA_rq[n]
MARBLE domain
interface
Arbitration
async control
Address
Data
AddressData
synchronousisland
self timedregion
Channel
DMA_irq/DMA_fiq
DMA controller
Initiator (Master)interface
Address Data
SOCB clock
Client Requests
request reset
Requests
DMA SPI(sync control)
Transferengine
Southampton: Oct 99 Asynchronous Circuit Compilation- 15
“Parallel” Design
Target (Slave)
DMAregisters
Transferengine
MARBLE bus
DMA_rq[n]
MARBLE domain
interface
Arbitration
async control
Address
Data
AddressData
synchronousisland
self timedregion
Channel
DMA_irq/DMA_fiq
DMA controller
Initiator (Master)interface
Address Data
SOCB clock
Client Requests
request reset
Requests
DMA SPI(sync control)
TETransferinterface
Addr
end of run
Southampton: Oct 99 Asynchronous Circuit Compilation- 16
Operation
Request arrives
Target (Slave)
DMAregisters
Transferengine
DMA_rq[n]
interface
Arbitration
async control
Address
Data
AddressData
synchronousisland
self timedregion
Channel
DMA_irq/DMA_fiq
DMA controller
Initiator (Master)interface
Address Data
SOCB clock
Client Requests
request reset
Requests
DMA SPI(sync control)
TETransferinterf ace
Addr
end of run
TI mem
RB Regs
R
RR
client req client req
+ W
W
+ W
R W
client req
Southampton: Oct 99 Asynchronous Circuit Compilation- 17
Operation
TE signals RB
Target (Sla ve)
DMAregisters
Transferengine
DMA_rq[n]
interf ace
Arbitration
async control
Address
Data
AddressData
synchronousisland
self timedregion
Channel
DMA_irq/DMA_fiq
DMA controller
Initiator (Master)interf ace
Address Data
SOCB cloc k
Client Requests
request reset
Requests
DMA SPI(sync control)
TETransferinterf ace
Addr
end of run
TI mem
RB Regs
R
RR
client req client req
+ W
W
+ W
R W
client req
Southampton: Oct 99 Asynchronous Circuit Compilation- 18
Operation
RB responds ||incrementing counter
Target (Sla ve)
DMAregisters
Transferengine
DMA_rq[n]
interf ace
Arbitration
async control
Address
Data
AddressData
synchronousisland
self timedregion
Channel
DMA_irq/DMA_fiq
DMA controller
Initiator (Master)interf ace
Address Data
SOCB cloc k
Client Requests
request reset
Requests
DMA SPI(sync control)
TETransferinterf ace
Addr
end of run
TI mem
RB Regs
R
RR
client req client req
+ W
W
+ W
R W
client req
Increment in reg bank
Southampton: Oct 99 Asynchronous Circuit Compilation- 19
Operation
TE sends addr to TI ||RB reg writes
Target (Sla ve)
DMAregisters
Transferengine
DMA_rq[n]
interf ace
Arbitration
async control
Address
Data
AddressData
synchronousisland
self timedregion
Channel
DMA_irq/DMA_fiq
DMA controller
Initiator (Master)interf ace
Address Data
SOCB cloc k
Client Requests
request reset
Requests
DMA SPI(sync control)
TETransferinterf ace
Addr
end of run
TI mem
RB Regs
R
RR
client req client req
+ W
W
+ W
R W
client req
Southampton: Oct 99 Asynchronous Circuit Compilation- 20
Operation
TI performs transfer
Target (Slave)
DMAregisters
Transferengine
DMA_rq[n]
interface
Arbitration
async control
Address
Data
AddressData
synchronousisland
self timedregion
Channel
DMA_irq/DMA_fiq
DMA controller
Initiator (Master)interface
Address Data
SOCB clock
Client Requests
request reset
Requests
DMA SPI(sync control)
TETransferinterface
Addr
end of run
TI mem
RB Regs
R
RR
client req client req
+ W
W
+ W
R W
client req
Southampton: Oct 99 Asynchronous Circuit Compilation- 21
Operation
TI signals RB ifLast transfer completed
Target (Slave)
DMAregisters
Transferengine
DMA_rq[n]
interface
Arbitration
async control
Address
Data
AddressData
synchronousisland
self timedregion
Channel
DMA_irq/DMA_fiq
DMA controller
Initiator (Master)interface
Address Data
SOCB clock
Client Requests
request reset
Requests
DMA SPI(sync control)
TETransferinterface
Addr
end of run
TI mem
RB Regs
R
RR
client req client req
+ W
W
+ W
R W
client req
Southampton: Oct 99 Asynchronous Circuit Compilation- 22
The Design
919 lines of Balsa describing register bank control, TE and TI.
Custom register banks and Synchronous Peripheral Interface
Miscellaneous glue standard cells• Register bank controllers• MARBLE interfaces
Compass Design Automation CAD
Southampton: Oct 99 Asynchronous Circuit Compilation- 23
Design Partitioning
Target (Slave)
Transferengine
MARBLE bus
DMA_rq[n]
MARBLE domain
interface
ArbitrationAddress
Data
AddressData
synchronousisland
self timedregion
Channel
DMA_irq/DMA_fiq
DMA controller
Initiator (Master)interface
Address Data
SOCB clock
Client Requests
request reset
Requests
DMA SPI(sync control)
TETransferinterface
Addr
end of run
RB Control
commonregs
headregs
longregs
Marble BUS: outsideof DMA controller
Southampton: Oct 99 Asynchronous Circuit Compilation- 24
Design Partitioning
Balsa synthesisedstandard cells
Target (Slave)
Transferengine
MARBLE bus
DMA_rq[n]
MARBLE domain
interface
ArbitrationAddress
Data
AddressData
synchronousisland
self timedregion
Channel
DMA_irq/DMA_fiq
DMA controller
Initiator (Master)interface
Address Data
SOCB clock
Client Requests
request reset
Requests
DMA SPI(sync control)
TETransferinterface
Addr
end of run
RB Control
commonregs
headregs
longregs
Southampton: Oct 99 Asynchronous Circuit Compilation- 25
Design Partitioning
Custom“regular” layout
Target (Slave)
Transferengine
MARBLE bus
DMA_rq[n]
MARBLE domain
interface
ArbitrationAddress
Data
AddressData
synchronousisland
self timedregion
Channel
DMA_irq/DMA_fiq
DMA controller
Initiator (Master)interface
Address Data
SOCB clock
Client Requests
request reset
Requests
DMA SPI(sync control)
TETransferinterface
Addr
end of run
RB Control
commonregs
headregs
longregs
Southampton: Oct 99 Asynchronous Circuit Compilation- 26
Design Partitioning
Hand designedstandard cells
Target (Slave)
Transferengine
MARBLE bus
DMA_rq[n]
MARBLE domain
interface
ArbitrationAddress
Data
AddressData
synchronousisland
self timedregion
Channel
DMA_irq/DMA_fiq
DMA controller
Initiator (Master)interface
Address Data
SOCB clock
Client Requests
request reset
Requests
DMA SPI(sync control)
TETransferinterface
Addr
end of run
RB Control
commonregs
headregs
longregs
Southampton: Oct 99 Asynchronous Circuit Compilation- 27
DMA Controller Floor-Plan
Southampton: Oct 99 Asynchronous Circuit Compilation- 28
Implementation Technology
0.35m, 3LM CMOS Standard cells from ARM Ltd. Locally designed complex gates and
asynchronous elements/gates. Automated standard cell P&R Only “essential” and simple gate level
optimisation (by hand)
Southampton: Oct 99 Asynchronous Circuit Compilation- 29
Simulation
LARD behavioural modelling EPIC TimeMill transistor level simulation
• on schematic• on cap. Extracted netlist
TimeMill is calibrated using SPICE, claims to be within a few % of SPICE
Results measured for run of 16 mem To mem transfers.
Southampton: Oct 99 Asynchronous Circuit Compilation- 30
Comparing Performance
Cycle time vs. Memory latency
020406080
100120140160180200220240
0 10 20 30 40 50 60 70 80 90 100 110 120
Memory latency (ns)
DM
A t
fr. c
yc
le (
ns
)
Parallel Serial