spd dcs status report ivan amos calì università degli studi di bari / cern 15 th alice dcs...
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SPD DCS Status Report
Ivan Amos Calì
Università degli studi di Bari / CERN
15th ALICE DCS Workshop
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Outlook
SPD DCS scheme FSM hierarchy FE DCS scheme and status report Cooling, HV/LV PS control status report Configuration DB status report SPD DCS outlook
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SPD DCS People
FE & FSM: I.A.Calì, S.Ceresa, C.Torcato De Matos
Cooling system: G.Guaglio, A.Tauro
HV/LV PSs: M.Caselle, L.Vinogradov
Configuration DB: P.Chochula, S.Kapusta
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SPD DCS I
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SPD DCS IISPD DCS
Infra
FED
FED
Power
HV LV
Cooling
Cooling
LV (HSn) 0-1
HV (HSn)
Device U
CU
LU
Sect0-9
HSect0-1
HS0-5
Legend:FED (HSn)
Cooling (Sect n)
HSnPower
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SPD Data and FE Control flux
Data & Ctl
FED Control(PVSS)
FED Server
Com
man
ds &
Stat
us
Analysis Tool CDT(ROOT)
Com
mands &
Status
Data
Config. DB
Data
to D
AQ
Optical
VME
Ethernet (DIM)
PVSS Archive
Shuttle to Cond. DB
FED Servers(x2 Side A & C)
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FED Server I
DIM Server
Application Layer
Driver Layer
Com
m &
Sta
tus
Com
m. &
Ctl
DIM Server:
•Allow communication with higher level software
•Receive commands (string)
•Update status information, alarms and Data
Application Layer:
•Detector control and monitoring agents
•Automatic calibration routines
•Configuration DB interfaceDriver Layer:
•VME access drivers
•Resource control agents
Conf DB connection
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FED Server II
FED Server version 2.2.7 released DIM server fully operative & full compliance with
ALICE API definition On-detector and Off-detector electronics manual
control fully operative Automatic detector configuration developed
(configuration files) Automatic temperature and voltage Alarm
handling developed Automatic uniformity matrix and threshold scans
implemented VME Driver layer operative
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FED PVSS Layer I
Manual and automatic detector configuration panels
Calibration control panels Temperatures, voltages and
electronics status monitoring panels
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FED PVSS Layer II
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Analysis tool
Interface to PVSS and FED server fully operative
Uniformity of response and noisy scans analysis operative
Results recorded to files
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HV/LV PS I
Hardware: SY1527 mainframe, A1676 branch controller,
EASY3000 crate 1 x A1519B HV module (12 channels) 2 x A3009B LV (12 channels) modules Cooling – PS System hardware interlock
Software: PVSS control panel prototype SPD channel (HS) Power up – Power down
sequence HV-LV Software interlock
1st SPD Sector operative at the DSF
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HV/LV PS II
V/I monitoring values
half-sector status
First prototype HV/LV PS PVSS control panel
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Cooling System I
SPD cooling plant installed at DSF with 10 cooling lines
PVSS control panel fwCoolingAndVentilation 0.14 integrated in the JCOP framework (not yet officially released)
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Cooling System II
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CHARACTERIZATION
CONFIGURATION Pixel chip DACs 52 800 bytes API-DPI-GOL configuration 2 400 bytes API conversions 1 920 000 bytes Mask & Dead pixel (1% & data compr) 393 216 bytes HV, LV settings 2 880 bytes
MeanTH & RMS noise 4800 bytes MinimumTH 1200 bytes Uniformity matrix scan 19 660 800 bytes
S-curves (10 DAC values) ? 196 608 000 bytes
See S.Kapusta talk for more details
Configuration DB
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SPD DCS Summary
Full system running in DFS and used for test sector0 HV/LV PS control system Cooling control system FE control system Analysis Tool
Performance tests demonstrated adherence with requirements
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Temp. locationof HV/LV PS
Router crate 1
Trigger crate
DAQ/DATE
FEDServer 1
CoolingPVSS
HV/LVPVSS
FEDPVSS
Analysis PC (CDT)
DSF “Control Room”Controlling sector 0
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SPD DCS Outlook
HV/LV, Cooling and FED FSM Finalize FED Server Import FED control into JCOP
framework Configuration DB integration SPD FSM and ALICE DCS/ECS
integration
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BACKUP
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FE Characterization
Define working parameter: Noisy and dead Pixels Uniformity of response Minimum and Mean TH Fast-OR Reference Voltages parameterization
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FE Configuration and Monitoring
HSs configuration Voltages and Temperature monitor (API
Feedback) SEU monitor JTAG Chain status (chips on the chain) Off-detector electronics status Busy and trigger status for
synchronization (i.e. missing L1, L2, Header status bits)
Data format check
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SPD State Diagram
OFF NOT_READY READY {mode}
INCOMPLETE
ERROR
startup
standby
configure
shutdown
set mode {PHYSICS, TEST, …}
recover
shutdown
recover
shutdown
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SPD hardware Interlock to PSs
2 temperature interlock lines for each sector coming from the Routers (API PT1000 chain, OR for all HSs/sect.)
2 temperature interlock lines for each sector coming from 2nd PT1000 chain (OR for all HSs/sect.)
1 interlock line for each sector coming from the cooling plants (loop locked OR Error Alarms )
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Activity Time table
First SPD DCS prototype: June – July Integration with Alice ECS - DAQ:
July – August Test of the full chain on 2nd half
barrel: September – October
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SPD DCS Outlook ISPD DCS
Infra
FED
FED
Power
HV LV
Cooling
Cooling
LV (HSn) 0-1
HV (HSn)
Device U
CU
LU
Sect0-9
HSect0-1
HS0-5
Legend:FED (HSn)
Cooling (Sect n)
HSnPower
Config. DB
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Condition DB
Noisy & dead pixel mask Thresholds
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SPD DCS Used for…
ALICE RUN: Detector Configuration Status control Characterization
Sector & DCS - FERO Performance Test
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FED Server internal structure
DIM Server
ChDecoder
Driver Layer
Pooling OperationControl
Access Control Manager
Manual Control Agent
Data Buffer
Supervision Agent
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Com
m. &
Ctl
SPD Data and Control flux
OFF-DETECTOR ELECTRONICS
(Routers & LinkRxs)
OFF-DETECTOR ELECTRONICS
(Routers & LinkRxs)Data & Ctl Data
ALICEDAQ
(AliRoot)
ALICEDAQ
(AliRoot)
FED ServerFED Server
Data
Optical
VME
Ethernet (DIM)
ANALYSIS TOOLS
ANALYSIS TOOLS
PVSSPVSS
Com
m &
Stat
us
Data
MOODMOOD
Data
DB
1
2
2
1
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Glossary
ECS: Experiment Control System DCS: Detector Control System FED: Front End Device FERO: Front End ReadOut
Electronics PCA: Partition Control Agent ECA: Experiment Control Agent DIM: Data Interschange manager
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Configuration DB II
440 DACs/HS x 120 = 52800 bytes API-DPI-GOL= 20 byte x 120 = 2400 bytes API conversion = 16000 byte x 120 = 1920 000 bytes Mask&Dead 1% of 8192 x 1200 x 4 = 393 216 bytes HV, LV settings 360 channels x 8 bytes = 2880 bytes
MeanTH&RMS 1200 chip x 4 bytes = 4800 bytes MinTH 1200 chip x 1 byte = 1200 byte Uniformity 1200 chip x 8192 ch x 2 byte= 19 660 800
S-curves 1200 chip x 8192 ch x 2 byte x 10 DAC values = 196 608 000 bytes
TOT 218 646 096
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SPD Sectors
Sector 0 (mixed bus)
Sector 1 (full Al bus)