special considerations on the selection of on-load tap-changers for psts-a2_205.pdf

7/30/2019 Special Considerations on the Selection of On-load Tap-changers for PSTs-A2_205.pdf

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21, rue dArtois, F-75008 PARIS A2-205 CIGRE 2006http : //www.cigre.org

Special Considerations on the Selection of On-load Tap-changers forPhase-shifting Transformers

A. KRMER*, D. DOHNAL, B. HERRMANNMaschinenfabrik Reinhausen GmbH

Germany

SUMMARY

The selection of on-load tap-changers (OLTCs) for application in phase-shifting transformers (PSTs)differs in some tasks from that for standard power transformers (PTs). These differences has to betaken into account seriously in the planning stage of the transformer. This paper will give helpfulguidance in questions of the selection of the appropriate on-load tap-changer (OLTC) for applicationin phase-shifting transformers (PSTs).

When the change-over selector operates, high recovery voltages across the change-over selector con-

tacts can occur, because the tap winding is momentarily disconnected from the main winding. In thecase of PSTs with single core design, where the regulation takes place at the line end, very high reco-very voltages can occur. The use of tie-in resistors or two-way change-over selectors often covers theproblem. However, sometimes it is necessary to change the winding design. Therefore the investiga-tion of this phenomenon should take place very early in the design phase.

Contrary to most of the standard PTs, in PSTs exist service positions where the load current does notflow through any part of the transformer winding. In these positions only a reduced or no short-circuitimpedance is effective between the load and the source side of the PST. This fact may make high de-mands on the short-circuit capability of the OLTC, if no short-circuit limiting measures were taken.

Usually the rated phase shift of the PST is defined under no-load conditions. Internal impedances ofthe PST create a voltage drop, which generates an additional phase shift. The phase shift can be ofadditive or subtractive nature to the rated phase shift. This internal voltage drop depends on the load(through-current) and may affect the step voltage of the OLTC.

When paralleling transformers, especially in case of PSTs, problems can arise, because the effectiveshort-circuit impedance of the tap windings can be near to zero, depending on the OLTC position. Thissituation will be amplified by usually high step voltages in PSTs, which result in high voltage differen-ces between the paralleled PSTs. Therefore high circulating currents between the OLTCs can occurand can lead to a non permissible stress.

KEYWORDS

Phase-shifting Transformer, On-load Tap-changer, Paralleling, Short-circuit Impedance, Rated Condi-

tions

* [email protected]


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1 INTRODUCTION

The growth of electric power consumption combined with environmental pressures and legal regula-tions causing delays and cancellations of new transmission lines, forces the demand to use the existingnetworks with high efficiency and high reliability. Therefore high-voltage power grids are intercon-nected to strengthen the reliability of the electrical power supply and allow the transmission of electri-

cal power over large distances. Complications, attributed to several factors such as different impedan-ces of parallel paths in the grid, the power factor and variations in the power generation output and/orpower consumption, can arise and have to be dealt with to avoid potentially catastrophic system blackouts.

Due to the mainly inductive character of the existing power system, an addition or subtraction of a vol-tage in phase to the system voltage (variation of the magnitude) affects the reactive power flow only,whereas an addition or subtraction of a voltage perpendicular to the system voltage (variation of thelag between source and load) influences the real power flow. The first case is accomplished by meansof variation of the voltage ratio between primary and secondary (regulating power transformers, PTs).The latter one by means of generating a phase shift between source and load terminals (phase-shiftingtransformers, PSTs). PSTs are nowadays in many cases established and well proven to control the real

power flow in transmission lines and system interties to stabilize the grid.2 TYPES OF PSTS

PSTs can be designed to provide a discrete phase angle shift, continuous variable phase angle shift, ora combination of both. Some designs allow for magnitude as well as phase control. Many differentwinding arrangements are possible depending on the rated voltage, the power output, the amount ofphase shift, and whether or not linear voltage control is also required. Discrete phase angle shiftersnormally provide settings for a plus-or-minus fixed degree value and zero. A variable phase shift canbe achieved in a very efficient way by using on-load tap-changers (OLTCs) for the variation of thephase shift in definite steps during operation. In most cases, the PSTs are designed to allow the inver-sion of the phase shift from advance to retard and vice versa.

In practice, various solutions are possible to design a PST. The chosen design depends on the majorfactors [1], [2]:

Throughput power and phase-shift angle requirements Rated voltage Short-circuit capability of the connected system Shipping limitations On-load tap-changer performance requirements

In addition, preferences of a manufacturer as to the type of transformer (core or shell) or other designcharacteristics (symmetric or non-symmetric, quadrature or non-quadrature) may also play a role.With respect to the OLTC, the decision whether a single- or a dual-core design is chosen, is very im-portant and may be determined by the performance characteristics of the OLTC. Dual-core designs

must not necessarily require a dual tank construction.

3 SELECTION OF OLTCS

OLTCs are subjected to numerous limits. Depending on the PST design, the tap-changer can be loca-ted directly at the line end (high voltage) or in a separate exciting unit. The solution with the OLTC(s)at the line end is typical for the single core design. The arrangement of the OLTC(s) in the excitingwinding is typical for dual core designs.

The advantage of the single core design is the less complexity combined with its high economic effi-ciency. However, a number of disadvantages are existing connected with this design and the OLTCapplication. As mentioned above, the OLTCs are located at the line end and therefore exposed to alldisturbances in the system (over voltages, short-circuit fault currents). The regulation requirements de-termine directly the step voltage and the through-current of the OLTC, but a variation of these values(and with this a possibly more economic choice of the OLTC) is not possible due to the customer spe-

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cification. In most of the cases each phase is equipped with one (non-symmetric design) or two (sym-metric design) OLTCs.

The most common configuration of a dual core design consists of a series and an exciting unit. Theseunits can be enclosed in one tank, but for large capacity transformers, they are designed with to separ-ate tanks. When using this design the step voltage and the through-current of the regulating winding

can be varied and optimized with respect to the rated step voltage and rated through-current of theavailable OLTCs. Up to a certain rating, three-phase OLTCs can be used, with higher ratings threesingle-pole OLTCs are necessary. The highest voltage for equipment of the OLTC (insulation level) isindependent of the system voltage and can be kept low. The use of winding arrangements with coarseand tap winding is possible when larger regulating ranges or reduced step voltage by increasing thenumber of steps are wanted or necessary. This solution requires an additional switch (AdvancedRetard Switch) which serves for the advanced/retard selection.

The basic selection of the OLTC is carried out with the maximum through-current and the maximumstep voltage. The determination of these values has to be considered well. For both designs is validthat the maximum phase shift is defined under no load conditions and is, usually, symmetrical. How-ever, the phase shift varies under load due to load losses and leakage impedances, resulting in increase

of the phase shift in the retard position, but a decrease in the advanced position of the PST.Additionally the overloading of a PST amplifies the above mentioned effects and influences the ratedvalues of the transformer and the OLTC.

In addition to the above mentioned consideration and deduced from the experience from many discus-sions regarding the application of OLTCs in PSTs, the following topics could be found as very impor-tant and should be considered very well in the designing stage of a PST:

The recovery voltage at the change-over selector (potential connection of the tap winding) The short-circuit impedance The breaking capacity The paralleling of OLTCs and PSTs

3.1 RECOVERY VOLTAGE AT THE CHANGE-OVER SELECTORThe operation of the change-over selector only takes place in a certain position of the OLTC. Duringthis operation the load current is not flowing through the tap winding. The change-over selector tem-porarily disconnects the tap winding from the main winding and the potential of the tap winding floats.The floating potential during contact separation is determined by the capacitive coupling to the adja-cent winding(s) and/or other adjacent parts of the transformer. Usually, the floating potential is differ-ent from the potential of the tap winding when connected to the main winding.

After contact separation one contact of the change-over selector is still connected to the main winding,the other one is connected to the floating tap winding and discharges occur. The breaking stresses aredetermined by the current flowing before the contacts open (currents through the coupling capacitors)and the voltage which arises when the arc extinguishes (recovery voltage). It can be firstly taken from

this interrelation that high values of the coupling capacitances lead to high currents to be switched off.Secondly, high differences between the floating potential of the tap winding and the fixed potential ofthe main winding lead to high recovery voltages.

The basic principle of generating a phase shift is to add a perpendicular voltage to the voltages of thesource and load side. In a three phase system this can be realized by connecting the tap winding of onephase to the main winding of another phase. During the change-over operation, when the tap windingis disconnected from the main winding, the tap winding will be electrically displaced in direction tothat phase, where it is geometrically located and capacitively coupled.

In case of single core designs, the potential difference between the two stages tap winding connectedto the main winding and tap winding is floating can reach inadmissible high values, because thesystem voltage is part of the potential difference. In certain winding arrangements, the recovery vol-

tage at the change-over selector can reach values higher than the system voltage divided by square rootthree, but the limit of the recovery voltage is in the range of 15 to 35 kV. Therefore, particular atten-

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tion should be paid to the recovery voltage problem very early and the tap-changer manufacturershould be consulted. In some cases the solution of this phenomenon can dictate the OLTC and canhave large impact on the design of the PST due to extensive special countermeasures (additionaldouble-reversing devices, static shielding). More detailed information can be found in [3], [4] and [5].

The potential connection of the tap winding has to be checked in case of dual core designs also, but in

most of the cases the recovery voltage at the change-over selector is controllable with conventionalmeasures.

3.2 SHORT-CIRCUIT IMPEDANCE

When the PST is serving in an intertie between two networks, the short-circuit impedance of the PSTshould be well taken into account. In case of single core PSTs the short-circuit impedance varies be-tween zero and its maximum, depending on the OLTC position respectively the actual phase shift, be-cause the tap winding(s) is the sole impedance between source and load side. Therefore, the PST willnot contribute to a short-circuit impedance and herewith the limitation of fault currents. Although thefault current is not flowing through the tap winding at zero phase shift (zero short-circuit impedance),the OLTC is still in the circuit and the fault current is flowing through the OLTC. But the OLTC has

only a limited short-circuit current carrying capability and, therefore, additional fault current limitingdevices such as current limiting reactors have to be considered very well.

The short-circuit impedance of the dual core PST is the sum of the impedances of the series and theexciting unit. If the impedance of the exciting unit is small compared to that of the series unit, theshort-circuit impedance of the PST is nearly constant and is not much affected by the OLTC positionand herewith by the actual phase shift.

Particular care should be taken in case of low-impedance and booster transformers. In some instances,the short-circuit current magnitude can dictate the OLTC selection.

3.3 BREAKING CAPACITY

3.3.1 DEPENDENCY OF STEP VOLTAGE ON OLTC-POSITION AND PST-LOAD

Beside the through-current the step voltage is the most important parameter for a correct OLTC-selec-tion concerning the required switching capacity of an OLTC. The step voltage in a PST may vary in awide range depending on the load of the PST and the OLTC-position. In the following these depen-dencies are compared for two basic PST-designs: a symmetrical single core design according to fig. 1aand a symmetrical dual core design according to fig. 1b. The two OLTCs in fig. 1a are always opera-ting at the same time, i.e. at 0-position no tap winding is active.

-

+ UE2

IE1

S LILIS

U1=UE1

IB2

IE2

UL

UB2

UB1=USL

N

US

++ -

UE2=USL

U1

US

S

N

L

UE1

UL

IE1

IS IL

-

Fig. 1a: symmetrical single core design Fig. 1b: symmetrical dual core design

For the following equations the series connection of the two separate tap windings in fig. 1a were con-sidered as one tap winding. The definitions of the used abbreviations are:

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OLTC-position with maximum number of steps in service: NmaxOLTC-position with N steps in service: N with N = 0.. NmaxTurns ratio of the exciter unit at OLTC-position Nmax: RETurns ratio of the exciter unit at OLTC-position N: REN = RE*Nmax /N 3.3_1a

Turns ratio of the booster unit: RB

Impedance of the tap winding at position Nmax:Z

EImpedance of the tap winding in service at position N: ZEN ZE*(N/Nmax) 3.3_1bImpedance of the booster unit on the high voltage side UB1: ZBPhase angle between US and UL at OLTC-position N: NPhase angle at OLTC-position Nmax and at no-load: 0

The basic equations for currents and voltages of a transformer under load with turns ratio R, short-cir-cuit impedance Z2 of winding 2 and power flow from winding 1 to winding 2 are:

U2 = U1/R -I2*Z2 3.3_2aI2 = I1*R 3.3_2b

Using eq. 3.3_2a,b the relations of voltages and currents of the exciter unit and the booster unit

become:Exciter unit: UE2 = UE1/REN +IE2*ZEN 3.3_3

with IE2 = (IS +IL)/2 for single core design (fig. 1a), 3.3_4awith IE2 = - j* 3 *IB2 = - j* 3 *RB*(IS +IL)/2 for dual core design (fig. 1b). 3.3_4b

Booster unit: UB1 = UB2*RB +IB1*ZB withIB1 = (IS +IL)/2 (fig. 1b). 3.3_5

The sign of term UE1/REN in eq. 3.3_3 depends on the position of the change-over selector. Sign (+) isretard phase shift, sign (-) is advanced phase shift.

With 3.3_1a,b: UE2 = UE1*N/(RE *Nmax) +IE2*ZE*(N/Nmax) 3.3_6

The OLTC-step voltage can be calculated with eq. 3.3_6:

UStep = UE2/N = UE1/(RE *Nmax) +IE2*ZE*N/Nmax 3.3_7

As an approximation the exciter voltage UE1 in eq. 3.3_7 can be expressed as function of the phaseangle N at OLTC-position N, see fig. 2a:

UE1 = j* 3 *U1 = j* 3 *US*cos(N/2) for single core design (fig. 1a) 3.3_8aUE1 = U1 = US*cos(N/2) for dual core design (fig. 1b) 3.3_8b

USL in fig. 2a is the voltage between source side and load side of the PST. The phase angle betweenUSL and U1 is not exactly 90 due to the voltage drop atZE undZB under load, but the approximation ineq.3.3_8a,b with the cos-function is sufficient to show the basic influence of angle N on UE1.

N

USLU1= US cos(N/2)

US

UL

N0

(IS +IL) / 2=IS *cos(N0/2)

IS

IL

Fig. 2a:Vector diagram of voltages Fig. 2b: Vector diagram of currents

The current IE2 in eq. 3.3_7is a function of the phase angle N0 between the currents of source and load

side at OLTC-position N, see fig. 2b. Due to eq. 3.3_2b the angle N0 is depending only on the turnsratio, whereas the angle N between the voltages is influenced additionally by the voltage drop at the

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transformer impedances, i.e. N0 = N is only true at no-load condition:

from 3.3_4a: IE2 =IS*cos(N0/2) for single core design (fig. 1a) 3.3_9a

from 3.3_4b: IE2 = - j* 3 *RB*IS*cos(N0/2) for dual core design (fig. 1b). 3.3_9b

The equations 3.3_7 to _9 show two contrary effects on the step voltage:

1) The exciter voltage UE1 as well as the OLTC current IE2 decrease with increasing angle N andtherefore with rising OLTC-position N according to functioncos(N/2). This is a characteristic ofthe symmetrical designs shown in fig. 1a,b and can be different for other PST designs, for exampleunsymmetrical dual core design with e.g. UE1 = US = constant. Due to the characteristic of the cos-function the effect of decreasing UE1 and IE2 with rising OLTC-position N is significant only forPSTs with high values of phase angle 0. This has the effect of decreasing step voltage with risingOLTC-position N at low load conditions.

2) The load dependent part of the step voltage in eq. 3.3_7 IE2*ZE*N/Nmax increases with the

number of steps in service (N). This is more effective in case of small angles 0, because IE2 will re-main nearly constant as mentioned above.

The comparison of PSTs with the same voltage, through-put power and impedance ZE but differentphase angles 0 shows that the step voltage will be more affected by the load in PSTs with a small 0than in PSTs with a great 0. The first term in eq. 3.3_7 UE1/(RE*Nmax) is mainly determined by

the required angle 0 (0 defines turns ratio RE, see also cl. 3.4) and will be of low value for PSTswith small angles, while the load dependent part of the step voltage is determined by the impedanceand power and is nearly independent of the phase angle 0.

Figures 3 and 4 show the effects of PST-load and transformer impedances as function of the OLTC-position for application examples with a great and a small phase angle. Each example has been calcu-lated with the two PST designs according to fig. 1a and fig. 1b. The used data are:

No-load angle at position Nmax: Case 1: 0 = 12 Case 2: 0 = 37Transformer impedances in both cases: ZE = 5%, ZB = 5%, (with ratio X/R = 8)Power factor US ,IS for both cases: 0.9

The step voltage UStep is shown as the ratio UStep/UStep0 (with: UStep0 = step voltage at no-load in OLTC-position N = 0). The PST-load is shown in p.u. (with: 1 p.u. = rated current). The meaning of transfor-mer impedance Z = 5% is that that part of the voltage USL in OLTC-position Nmax due to the voltagedrop at Z with a rated load of the PST is 5% of U S. The sign in front of the OLTC-position at the x-axis indicates the position of the change-over selector.

The impedance of the booster transformer in case of dual core designs influences the phase angle and the step voltage in a different way. The voltage USL and in consequence the phase angle of thePST is influenced by the voltage drop at the impedance of the booster transformer in case of dual core

designs:with 3.3_5: USL = j* 3 *UE2*RB +IB1*ZB for dual core design (fig. 1b) 3.3_10

Compared to PSTs with single core design, the phase angle for a PST with dual core design additi-onally will be increased (retard) or decreased (advanced) by the load (fig. 3a and 3b). The differencein for both designs does not depend on 0 or position N of the OLTC but only depends on thevalues of the load and the impedance ZB (in p.u.) (see also [1]).

Different to the above mentioned effect on phase angle , in both designs the step voltage is almost in-dependent from the voltage drop at ZB (fig. 4a and 4b). The step voltage is affected by the phase angle according to eq. 3.3_8b and eq. 3.3_7. Based on an impedance ZB = 5% the phase angle will differabout only 3 at rated load for both designs. The exciter voltage UE1 and in consequence the step vol-

tage will be changed according to eq. 3.3_8b only by approximately 1% due to the difference in phaseangle of 3.

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-50

-40

-30

-20

-10

0

10

20

30

40

16 14 12 10 8 6 4 2 0 -2 -4 -6 -8 -10 -12 -14 -16

OLTC-position

0 = 37 load (p.u) = 0

0 = 37 load (p.u) = 1

0 = 37 load (p.u) = 1.5

0 = 12 load (p.u) = 0

0 = 12 load (p.u) = 1

0 = 12 load (p.u) = 1.5

[]

-50

-40

-30

-20

-10

0

10

20

30

40

16 14 12 10 8 6 4 2 0 -2 -4 -6 -8 -10 -12 -14 -16

OLTC-position

0 = 37 load (p.u) = 0

0 = 37 load (p.u) = 1

0 = 37 load (p.u) = 1.5

0 = 12 load (p.u) = 0

0 = 12 load (p.u) = 1

0 = 12 load (p.u) = 1.5

[]

Fig.3a: Angle for single core design. Fig.3b: Angle for dual core design.

0,5

0,6

0,7

0,8

0,9

1,0

1,1

1,2

1,3

1,4

1,5

16 14 12 10 8 6 4 2 0 -2 -4 -6 -8 -10 -12 -14 -16

OLTC-position

UStep/UStep0

0 = 37 load (p.u) = 0

0 = 37 load (p.u) = 1

0 = 37 load (p.u) = 1.5

0 = 12 load (p.u) = 0

0 = 12 load (p.u) = 1

0 = 12 load (p.u) = 1.5

0,5

0,6

0,7

0,8

0,9

1,0

1,1

1,2

1,3

1,4

1,5

16 14 12 10 8 6 4 2 0 -2 -4 -6 -8 -10 -12 -14 -16

OLTC-position

UStep/UStep0

0 = 37 load (p.u) = 0

0 = 37 load (p.u) = 1

0 = 37 load (p.u) = 1.5

0 = 12 load (p.u) = 0

0 = 12 load (p.u) = 1

0 = 12 load (p.u) = 1.5

Fig.4a: Step voltage for single core design. Fig.4b: Step voltage for dual core design.

3.3.2 OLTC-ADAPTION FOR PHASE-SHIFTING TRANSFORMERSAll specified switching conditions of an application, including overload, have to be concerned to iden-tify the highest value of the step voltage, which is required for the OLTC selection as rated step vol-tage. Especially in PST-applications with small phase angles 0 the specified overload conditionsshould be checked concerning an increase of step voltages in the retard direction. This rated step vol-tage will define the required minimum value of the transition resistor of the OLTC to limit the circu-lating current in the mid-position of the diverter switch to a permissible value concerning the switch-ing capacity of the transition contacts.

The voltage drop at the transition resistor caused by the through-current forms the recovery voltage ofthe main switching contact. Therefore, the switching capacity of this contact limits the maximum per-missible value of the transition resistor for a specified overload to be switched. For the selection of the

transition resistor it is always necessary to find a balance between the effects of the step voltage andthe through-current. Therefore and for switching capability reasons the rated through-current of anOLTC is assigned to a specified rated step voltage. Regarding the switching capability this is also truefor the maximum rated through-current of an OLTC, but the maximum rated through-current ad-ditionally determines the current carrying limits and is, with respect to contact heating and short-cir-cuit withstand capability, independent on the step voltage.

A standard requirement for OLTCs in common PTs is the capability to break twice the rated through-current at rated step voltage (overload condition). This breaking capacity of the OLTC is guaranteed,provided that the step voltage is independent on the (over)load current. In PST-applications, where aload and OLTC-position dependent range of step voltages has to be handled, sometimes it is not pos-sible to find a transition resistor dimensioning, which is suitable for the rated step voltage (maximum

value of step voltage appearing under any specified switching condition) as well as for twice the ratedload current. If the overload requirements in those applications are not based on a breaking capacity

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of twice but for example of only 1.5 times the rated load current, it should be proven, if an OLTC withreduced rated through-current can be used to enable a more economical OLTC solution.

load current

step

voltage

Limit of the rated step voltage at the rated through-current of the OLTC

Limit of the rated step voltage at twice the rated through-current of the OLTC

Maximum rated

through-current

of the OLTC

Required overload

to be switched

Rated load current

of the application

Max. step voltage at overload =

rated step voltage of the application

Step voltage at rated load

current of the application

2

1

34

Fig. 5: Step voltage limits at rated and twice the rated through-current of any OLTC

Figure 5 shows the step voltage limits (switching diagram) as function of the rated through-current aswell as of twice the rated through-current of any OLTC. Load point represents the operating pointof any PST-application at 1 p.u.. Load point represents the operating point of this PST-applicationunder overload condition (here 1.5 times the rated load current). As mentioned above, point re-presents that pair of variates, for which the OLTC transition resistors have to be dimensioned. It isobvious that this point is beyond the limits. With the abdication for an overload switching capability oftwice the rated load current and with the knowledge that the dimensioning of the transition resistors iscarried out considering mainly the overload, now it becomes possible to adjust the transition resistorsto the operating point.

This procedure is only possible, if

1. the rated load current of the application is less than the maximum rated through-current of theOLTC

and

2. the load point under the required overload to be switched is inside the limit of the rated stepvoltage at twice the rated through-current of the OLTC.

3.4 PARALLELING OF PHASE-SHIFTING TRANSFORMERS

When connecting two (or more) regulating transformers equipped with OLTCs in parallel an out-of-step condition temporarily occurs due to the non synchronous operation of the different OLTCs. Evenif their motor drives are operated at the same time, the diverter switches do not operate synchronouslydue to the spring operated energy accumulator. The voltage difference of one tap in the parallel cir-cuits during this out-of-step condition will lead to different loadings of the transformers and theOLTCs, which are no longer proportionally to the rated power of the transformers. The duration of thisout-of-step condition is extremely short (less than 1 s) and therefore causes no problems regardingthe heating of the windings or of the OLTC contacts. However, these special breaking conditions ofOLTCs in paralleled transformers should be taken into consideration for the OLTC-selection.

OLTCs in paralleled PSTs may be more affected by the out-of-step condition than those in PTs. Inthe following the current distribution at out-of-step condition is compared for two paralleled PSTs

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and two paralleled PTs to show the basic differences. Each of the paralleled transformers A and B isrepresented by the no-load voltages U0A resp. U0B and the impedances ZA resp. ZB.

Figures 6a and b show the equivalent networks for two paralleled PSTs respectively two paralleledPTs, loaded with IL and system voltages US and UL.

Fig. 6a: Paralleled phase shift transformers. Fig. 6b: Paralleled power transformers.

With the approximation that the load current IL and the impedances of the transformers are nearlyequal before and after the tap-change operation at one of the paralleled transformers, the current distri-bution on the two transformers acc. fig. 6a and 6b is:

Before the tap-change operation the OLTCs in the paralleled transformers are on the same position:

U0A = U0B 3.4_1a

IA =IL *ZB / (ZA +ZB) =ILA 3.4_1b

IB =IL *ZA / (ZA +ZB) =ILB 3.4_1c

After the tap-change operation at one of the transformers, the out-of-step condition occurs:

IA =ILA +IC 3.4_2a

IB =ILB -IC 3.4_2b

with U = (U0A U0B) 3.4_2c

and IC = U/ (ZA +ZB) (IC = circulating current at out-of-step condition) 3.4_2d

In case of paralleled PSTs the tap-change operation from position 0 or to position 0 (compareclause 3.3) will lead to the most unsymmetrical current splitting of all possible out-of-step conditi-ons. In case of dual core designs the PST impedance in position 0 is only the impedance of the boo-ster unit, because the exciter unit is not loaded in this position and with this the circulating current I Cin eq. 3.4_2d has its maximum value. In consequence the paralleling of PSTs with single core designaccording to fig. 1a is not possible, because there is no PST-impedance in position 0 effective to en-sure a defined current distribution to the paralleled transformers and a short-circuit occurs. The equi-valent network of two paralleled PSTs of dual core design, one in position 0 and one in position 1,

can be reduced to that shown in fig. 7:

Fig. 7: Paralleled PSTs with PST A in pos. 1and PST B in pos. 0.

IL

US ULIB

U0BZB

IAU0A

ZA

USL

PST B

U0BU0A

ILIB

ZB

IA

ZA

PT BPT A

IL

IBZB

IAU

ZA

USL

ULUS

UL

PST A

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In case of paralleled PTs the voltage Uin eq. 3.4_2d is equal to the step voltage at no-load, whereasin case of paralleled PSTs U becomes -USL at no-load in OLTC-position 1 (compare fig. 2a and eq.3.3_10).

The vector diagrams of voltages and currents resulting from figs. 6b and 7 at the out-of-step condi-tion are shown in fig. 8a,b, where a power factor of the load (PF) is assumed in the range of 1. In

fig. 9a,b the same vector diagrams are shown with a PF in the range of 0. For these examples it is as-sumed that ZA and ZB of the paralleled transformers are equal. Then eq. 3.4_1b and 1c can be reducedto:

ILA =ILB = IL /2 (symmetrical current splitting before tap-change operation) 3.4_3

Fig. 8a: Vectors for paralleled PSTs with PF 1 Fig. 8b: Vectors for paralleled PTs with PF 1

IA * ZA

US

U

IC

IA

IBUL

IL/2

IB * ZB

IC

IB

IA

IL/2U0B

U

UL

IB * ZB

ICIB

IAIL/2

U0B

U

UL

IB * ZB

IA * ZA

IA

IBIL/2

US

U

UL

IB * ZB

IA * ZA

IC

IA * ZA

Fig. 9a: Vectors for paralleled PSTs with PF 0 Fig. 9b: Vectors for paralleled PTs with PF 0

Due to the inductive transformer impedances the circulating current IC has a phase shift to U of ap-proximately 90. In case of paralleled PSTs U has a phase shift to the system voltage US of 90, andtherefore the circulating current IC is nearly in phase respectively in phase opposition with US. In caseof paralleled PTs, IC has a phase shift of approximately 90 to the system voltage, because U (= stepvoltage) is in phase with the system voltage. As shown in figs. 8 and 9, the circulating current I C at theout-of-step condition will increase or decrease the magnitudes of the currents IA and IB, all the moreas IC is in phase with the load current IL. This arises at paralleled PSTs, if the power factor PF becomesnearly 1 and at paralleled PTs if PF becomes nearly 0.

As stated above, in case of paralleled PSTs the voltage USL between source and load side at no-loadcondition in position 1 of the OLTC has to be considered as U in eq. 3.4_2d for the worst currentsplitting condition. This U can be calculated as a function of the phase angle 0 and the number ofsteps Nmax. (definitions see clause 3.3). The following abbreviations for phase angle and voltage in po-sition 1 are used:

Phase angle of the PST in OLTC-position 1 at no-load: 1Voltage USL of the PST in OLTC-position 1 at no-load: USL1

For the OLTC in position N at no-load and using the definitions in clause 3.3 the phase anglebecomes:

with 3.3_3 and 3.3_10, fig. 2a: tan(N/2) = (USL/2)/UE1 = j* 3 *RB/(2*REN) 3.4_4a

with 3.3_1a and N= 1: tan(1/2) = j* 3 *RB/(2*RE*Nmax) 3.4_4bwith 3.3_1a and N= Nmax: tan(0/2) = j* 3 *RB/(2*RE) 3.4_4c

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Phase angle 0 and Nmax are specified for a PST in order stage. With these values 1 can be calculated:

tan(1/2) = tan(0/2) / Nmax 3.4_5

with fig. 2a: USL1 = 2*US*sin(1/2) ( = U in fig.7 and 3.4_2d) 3.4_6a

and with 3.4_5: USL1 = 2*US*cos(1/2)* tan(0/2) / Nmax 3.4_6b

and with cos(1/2) 1: USL1 = 2*US* tan(0/2) / Nmax 3.4_6cFor 0 between 10 and 40 eq. 3.4_6c can be approximated with a deviation of less than 2% with:

USL1 = US*Step / 56 with Step = 0/Nmax 3.4_6d

As an example fig. 10 shows the current splitting on two paralleled transformers as a function ofU.The calculation was done with two different power factors PF of 0.9 and 0.3 to demonstrate the dif-ferent influences on PSTs and PTs in the range of common step voltages and transformer impedances.

1,00

1,05

1,10

1,15

1,20

1,25

1,30

1,35

1,40

1,0% 1,5% 2,0% 2,5% 3,0% 3,5% 4,0%

U / US

IA / ILA

PST PF = 0.9 Z = 5%

PST PF = 0.9 Z = 10%

PST PF = 0.3 Z = 5%

PST PF = 0.3 Z = 10%

PT PF = 0.9 Z = 5%

PT PF = 0.9 Z = 10%

PT PF = 0.3 Z = 5%

PT PF = 0.3 Z = 10%

Fig. 10: Increase of the current IA in paralleled transformers, both with the same impedancesZ (ratio X/R = 8), due to out-of-step condition. Load before tap-change operation:ILA = rated current.

The current IA (see eq. 3.4_2a) in one of the two transformers respectively one of the OLTCs duringout-of-step condition will be increased at most by IA assuming the following ordinary values forpower factor and transformer impedance:

PST: IA = 31% of the rated current with: Z = 5% PF = 0.9 U = 3.6 % resp. Step = 2PT: IA = 7% of the rated current with: Z = 10% PF = 0.3 U = 1.5 %.

Regarding the required switching capacity of the OLTC, in case of paralleled transformers the abovementioned increase IA of the OLTC through-current in the out-of-step condition should be covered

by the required overload which the OLTC should be able to break.

4 CONCLUSION

As stated in IEEE Standard C57.135 [5] and IEC Publication 60214-2 [6] the selection of OLTCs forthe use in PSTs has to be considered very well because of some specific duties.

The recovery voltage at the open change-over selector depends mainly on the transformer design. E-specially in case of PSTs some specific rules have to be paid attention to. The recovery voltage shouldbe checked together with the OLTC manufacturer in the planning stage of the PST to proof the designwith respect to these stresses. The recovery voltage limits at the change-over selector can dictate theOLTC selection and sometimes the transformer design.

Because of the limited short-circuit current carrying capability of the OLTC, the short-circuit impe-dance of the PST should be taken into account.

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Unlike in standard PTs, the overloading of a PST influences the rated values of the transformer. Allpossible switching conditions for the OLTCs in the PST-application have to be concerned to identifythe highest value of the step voltage, which is required for the OLTC selection as rated step voltage.Especially in PST-applications with small phase angles 0 the specified overload conditions should bechecked taking into account the increase of step voltages in the retard direction.

When paralleling two (or more) transformers equipped with OLTCs, an out-of-step condition for avery short time period occurs due to non synchronous operation of the different OLTCs. In this casethe momentary voltage difference of the two transformers will force a circulating current through thecircuit, which is only limited by the reactances involved. OLTCs in paralleled PSTs may be moreaffected by the out-of-step condition than those in PTs. Under certain conditions the magnitude ofthis circulating current may reach the order of one third of the load current. This has to be checked inevery case with respect to the switching capability of the OLTC. The paralleling of PSTs in single coredesign is not possible with respect to the OLTC, because in the 0-position there is no transformerimpedance effective. Consequently, the OLTC switching secondly has to break, in addition to the loadcurrent, a circulating current which is in the range of a short-circuit current.

BIBLIOGRAPHY

[1] Gustav Preininger Phase-shiftig Transformers(in: James Harlow Electric Power TransformerEngineering, CRC Press, New York, 2004, pages 2-63 2-80)

[2] Walter Seitlinger Phase Shifting Transformers Discussion of Specific Characteristics(CIGR Session 1998, Paris, 30th August 5th September 1998, paper 12-306)

[3] A. Krmer, J. Ruff Transformers for Phase Angle Regulation Considering the Selection of On-load Tap-changers (IEEE Transactions on Power Delivery, Vol. 13, No.2, April 1998, pages518-525)

[4] Axel Krmer On-load Tap-changers for Power Transformers Operation Principles,Applications and Selection (MR-Publication, Regensburg, 2000).

[5] IEEE Standard C57.135 IEEE Guide for the Application, Specification and Testing of Phase-Shifting Transformers, First edition, 2001

[6] IEC Publication 60214-2 Tap-changers Part 2: Application Guide, First edition, 2004

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special considerations on the selection of on-load tap-changers for psts-a2_205.pdf

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