Specificationof the Pre-ProcessorMulti-Chip Module (PPrMCM)

for theATLAS Level-1Calorimeter Trigger

TheKIP Heidelberg GroupKirchhoff-Institut für Physik,Heidelberg, Germany

Draft Version0.1 26. March.2001

1:1scaledview of thePPrMCM

Abstract

Thisspecificationwill describetechnicalandelectricalcharacteristicsof thePre-ProcessorMulti-Chip Module(PPrMCM)asrequiredfor its FinalDesignReview (FDR).Review Panel:x, x, x, x.

CONTENTS 2

Contents

1 Intr oduction 5

2 Pre-ProcessorSystemOverview 5

3 Functional Description of the PPrMCM 7

3.1 MCM I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 DesignExperience 13

5 Characteristics 14

5.1 MechanicalCharacteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.2 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.3 ElectricalCharacteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6 Production Technique 15

6.1 LayerStructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.2 FeatureSizeandDesignConstraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7 Schematic 18

8 Simulations 25

8.1 Circuit Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

8.2 ThermalSimulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

9 Layout 26

10 Yield and SparePolicy 29

11 Manufacturing 30

12 Testing 31

A Chip Footprints 32

B MCM Pin and Net NameListings 37

LIST OFFIGURES 3

List of Figures

1 Pre-ProcessorModuleblockdiagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 MCM functionalblockdiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Pinningof thePPMfront-panelconnectorfrom LAr calorimeters. . . . . . . . . . . . . . . . . . . . . . 10

4 Block diagramof theanaloginputsignalgenerationcircuit . . . . . . . . . . . . . . . . . . . . . . . . . 11

5 MCM physicaldimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6 MCM timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

7 MCM layerdefinition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

8 Cross-sectionwith staggeredvia connectionthroughall layers. . . . . . . . . . . . . . . . . . . . . . . . 17

9 MCM designrules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

10 MCM schematicTOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

11 MCM schematicpage1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

12 MCM schematicpage2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

13 MCM schematicpage3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

14 MCM schematicpage4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

15 Mixed-signalsimulationandtestvectorgeneration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

16 Temperaturesimulationfor chevron-likeMCM placment . . . . . . . . . . . . . . . . . . . . . . . . . . 26

17 All MCM layers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

18 MCM layer1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

19 MCM layer2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

20 MCM layer3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

21 MCM layer4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

22 MCM testsequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

23 MCM testset-upatMCM assembler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

24 BTH030footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

25 AD9042footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

26 PPrAsicfootprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

27 DS92LV1021footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

28 Phos4footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

List of Tables

1 Resetandbroadcastsignalsfrom TDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2 Power-upsequenceandinitializationdefaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3 Electrical,mechanicalandthermalcharacteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

LIST OFTABLES 4

4 Layoutandvia characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5 Yield andsparepolicy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6 Pinassignmentof partJ1(BTH03001FDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7 Pinassignmentof partJ1(BTH03001FDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8 Pinassignmentof partJ2(BTH03001FDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

9 Pinassignmentof partJ2(BTH03001FDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

10 Pinassignmentof partU1 (AD9042) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

11 Pinassignmentof partU2 (AD9042) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

12 Pinassignmentof partU3 (AD9042) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

13 Pinassignmentof partU4 (AD9042) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

14 Pinassignmentof partU5 (PPRASIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

15 Pinassignmentof partU5 (PPRASIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

16 Pinassignmentof partU5 (PPRASIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

17 Pinassignmentof partU6 (PHOS4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

18 Pinassignmentof partU7 (DS92LV1021) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

19 Pinassignmentof partU8 (DS92LV1021) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

20 Pinassignmentof partU9 (DS92LV1021) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

1 INTRODUCTION 5

1 Intr oduction

Mostof thereal-timesignalprocessingandpartsof thereadoutfunctionalityof thePre-Processorof theATLAS Level-1CalorimeterTriggerareintegratedin a Multi-Chip Module(MCM). A MCM packagingtechnologyis similar to hybridcircuits wheremany electroniccomponentsaremountedon a multi-layer substrate.In contrastto hybridsMCMs areencapsulatedhermeticallyandhenceareseenasa singlemodulewith hiddenfunctionalityfrom outside.

ThePre-Processorof theATLAS Level-1 CalorimeterTriggeris a complex systemwhich consistsof many chips(dice).This makes it desirableto assemblemany chips in a single packageto reducesystemsize and printed circuit boardcomplexity. Theadvantageof anMCM in thePre-Processorsystemis thatone-to-oneconnectionsbetweenchips,e.g.wide digital buses,canbekeptinternal.Only signalslike control,power supplyandmoduleinput andoutputsignalsareusedaspackagepinsto interfaceto theoutsideboard.

ThePPrMCMtechnologycanbeclassifiedby its substratetype. It is referredto asanMCM-L (laminated)technology.This techniquewaschosento combinesmallfeaturesizeswith low prices.Thesubstrateis basedonamulti-layerprintedcircuit boardtechnology(PCB).It is anextensionof chip-on-boardtechnology(COB),wherethebaredicearemounteddirectly on a substrate.Themulti-layerstructuresareformedby etchingpatternsin copperfoils laminatedon anorganicinsulatorcore of Polyimid. Interconnectionsbetweenlayersare formed by ‘blind’ vias, which only extendfrom thesurfacepart-way throughthe layers,or ‘buried’ vias,which connectonly adjacentinner layersanddo not extendto thesurfacein eitherdirection. Thesmallestfeasiblelayoutstructurein thedesignis referredto asfeaturesize. Thefeaturesizeof theMCM-L technologyof thePPrMCMis 100 � m.

RelatedDocuments

Dueto thecomplexity of theMCM thefollowing chipspecificationsanddocumentsareof importancefor theunderstand-ing of theelectronicsfunctionality.

� ChipSpecifications:[ADC], [PPrAsic],[LVDS], [Phos4]� ModuleSpecifications:[PPM], [ROD]� Thesis:[Ste00], [Pfe99/2]� FirstLevel TriggerTDR: [TDR98]

2 Pre-ProcessorSystemOverview

TheCalorimeterTriggergetsanaloginputsignalsfrom theelectro-magneticandthehadroniccalorimeters.Thesesignalsaresummedseparatelyin orderto form trigger tower signalswith a granularityof 0.1 x 0.1 in the � and � directions.All in all theCalorimeterTriggerhasabout7296analoginput signals,which aretransmittedelectricallyvia twisted-paircablesfrom thedetectorto theLevel-1Triggerelectronics,locatedin thetriggercavern. Themaximumcablelengthfortriggerinputsignalsis 60m.

ThePre-Processorat thefront-endof theATLAS Level-1CalorimeterTriggerlinks theATLAS calorimeterswith subse-quentCalorimeterTriggerprocessors.It providesthedigital datato identify objectsof interestfor thedecisionmakingon Level-1. Thepreprocessingincludesdigitization,identificationof thecorrespondingbunch-crossingin time (BCID),calibrationof the transverseenergy, ratemonitoring,readoutof raw trigger data,andhigh-speeddatatransmissiontothe subsequentprocessors.Thepreprocessingof a largenumberof analogsignalsrequiresa compactsystemwith fasthard-wiredalgorithmsimplementedin application-specificintegratedcircuits(ASICs)andMulti-Chip Modules(MCMs).

The basisof the Pre-ProcessorSystemis a compact64-channelPre-ProcessorModule (PPM).This modularitywith ahighdegreeof componentintegrationis requiredto pre-processall triggertowersignalseconomicallyin eightelectronics

2 PRE-PROCESSORSYSTEMOVERVIEW 6

Pre-Processor Module

VME�Control/�Monitorfor �64 chans�

Standard�VME64x_J2�(5row)Fast ReadOut (PipeLineBus)on "user def"

Standard�VME64x_J1(5row)

16an.IN

16 LRec,16 Discr(extBCID),

+32 DACs(Offs, Thr)

40 cm�

36,6 cm�

10 cm

16an.IN

16an.IN

16an.IN

MCM9: 4 chs

MCM10: 4 chs

MCM11: 4 chs

MCM12: 4 chs

MCM13: 4 chs

MCM14: 4 chs

MCM15: 4 chs

MCM16: 4 chs

MCM1: 4 chs

MCM2: 4 chs

MCM3: 4 chs

MCM4: 4 chs

MCM5: 4 chs

MCM6: 4 chs

MCM7: 4 chs

MCM8: 4 chs

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CtrlLEDs

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Figure1: Pre-ProcessorModuleblockdiagram

crates. Unusedchannelsof the Pre-Processorshouldbe groundedon the front-panelor maybeusedto monitor noiseeffectsthroughouttheup-streamtrigger-towerelectronics.Unusedchannelscanbeswitchedoff by loadinganappropriatelook-uptablecontentto thePPrAsic.A Receiver Stationin front of thePre-Processorconvertstheanaloginput signalsto transverseenergy within a � 5 % band. The outputresultsfrom the Pre-ProcessorSystemaresentvia serialLVDSlinks to thedown-streamprocessors,includingduplicationat � -boundaries.All in all thePre-Processorconsistsof 128suchmodules.See[TDR98] for a detaileddescriptionof thetasks.Thetaskson its input signalscanbesummarizedasfollows:

� Preprocessing:Provide the triggerprocessorsdownstreamwith digital datacontainingthe transverseenergy de-posited,identifiedwith thecorrespondingbunch-crossing.For theClusterProcessor(CP)thegranularityis 0.1 � 0.1for � ��������� andfor theJet/Energy-SumProcessor(JEP)thegranularityis 0.2 � 0.2for � �����"!#� $ . In bothcasestheinputdataareseparatefor theelectro-magneticandthehadroniccalorimeters.

� Readoutof event data: Raw triggerdatafrom thePre-Processorareneededto beableto tell whathascausedatriggerandto allow monitoringof theperformanceof thetriggersystem.

A 64-channelPre-ProcessorModulehasto carry16 PPrMCMs. Input connectorsfor 64 differentialanalogsignalswillbe locatedat thefront panel.On thebackplanesideof a modulethereadoutbusconnectors(PipelineBus),theVMEbusconnectors,andtheconnectorsfor theserialLVDS links will belocated.

Figure1 showsa blockdiagramof thePre-ProcessorModuleboardspace.Themodulewill have9 units(9U = 36,6cm)and40 cm in depth. The positionof the PPrMCM on the Pre-ProcessorModule wasoptimizedin termsof goodheatexchangeanda minimumof crosstalk betweenthehigh-speedMCM outputsignalsandtheanaloginputs. This figuremakesit obviousthatefficient signalroutingandcomponentplacementwill beof importance,andthatthefeasibility of

3 FUNCTIONAL DESCRIPTIONOFTHE PPRMCM 7

64 channelsper modulerelieson the Pre-ProcessorMCM beingcompactin size. See[PPM] for a specificationof thePre-ProcessorModule.

3 Functional Description of the PPrMCM

The PPrMCM containsthe preprocessingandthe readoutof the ATLAS Level-1 CalorimeterTrigger, for four triggertower signals,in a singleelectronicsmodule. The boundariesof the PPrMCM packagewerechosenat pointsof theprocessingchainwhereonly few signalscomein andoutof theMCM package.TheMCM hasanaloganddigital signalsasinputsandoutputs,respectively, andit includesdifferentsemiconductordevicessuchasmixed-signalandpuredigitalchips. Someof themarecommerciallyavailableandothersareapplicationspecific. The MCM processesfour triggertowersignalsusinga Pre-ProcessorASIC developedat theASIC laboratoryof theUniversityof Heidelberg [PPrAsic].

A schematiclike block diagramof the PPrMCM is shown in Figure 2. It contains9 dice: four ADCs [ADC], onefour-channelPre-ProcessorASIC [PPrAsic], threeLVDS serializersfor the digital datatransmissionto the subsequentprocessors[LVDS], anda timer chip [Phos4], neededfor thephaseadjustmentof theFADC strobeswith respectto theanaloginputsignals.

Thetasksof thePPrMCMare:

% to digitizefour analogtriggertowersignalsat40MHz with 10-bitresolution.Digitizationat12-bit is usedto extendtheeffectivenumberof bits. Thismeans,thelowesttwo bitsarenotconnectedto thePPrAsic;

% to pre-processeachtriggertowerdatain termsof energy calibrationandbunch-crossingidentification;% to serializepre-processedtriggertowerdatausinghigh-speedBusLVDS chip-sets.% to providedead-timefreereadoutof four triggertowers.

In orderto achievethese,theMCM consistsof:

% four ADCsfrom AnalogDevices(AD9042,[ADC]);% onefour-channelPPrAsic,providing readoutandpreprocessing;% one timer chip [Phos4], neededfor the phaseadjustmentof the FADC strobeswith respectto the analoginput

signals;

% threeBusLVDS Serializer([LVDS]) serializing10-bit at 40 MHz (400Mbpsuserdatarate,480MBd includingstart-andstopbit).

3 FUNCTIONAL DESCRIPTIONOFTHE PPRMCM 8

SD

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Figure2: MCM functionalblockdiagram

3 FUNCTIONAL DESCRIPTIONOFTHE PPRMCM 9

Theblockdiagramshows thescopeof theMCM, wherewide paralleldatabusesarekeptinternalandonly analoginput,control,andthehigh-speedserialdatasignalcomeout of theMCM package.Eachcomponenthasits own clock input,which will be bufferedexternally with the sameclock phase. To ensurevalid dataat the following stagethe risingor falling edgeof the PPrAsicclock canbe programmed.Programmingis requiredbecausethe ADC clock phaseisadjustablechannel-by-channelto theanaloginputpulsemaximum.This is requiredto optimizeBCID performance.TheADC clockphaseis programmablein stepsof 1 nsby thePhos4Asic within 25ns.TheLVDS clockedgecanbeselectedexternallyto meetthetiming requirementsat its input.

Therealtimesignalprocessingflows from theleft to theright. First, theFADC digitizestheanalogtriggertower signalsat40MHz to 12-bitprecision(10-bitsused)in a rangeof 1 V peak-to-peakaroundtheinternalgenerated2.4V referencevoltage. EachFADC die generatesits own referencevoltage. The offset adjustmentandscalingfrom the 2.5 V inputsignalrangeto this 1 V rangeis doneby theanaloginput boardshown in Figure4. Next, thefour 10-bit databusesareeachdigitally pre-processedinsidethePPrAsic.ThePPrAsicoutputis interfacedto threeLVDS Serializerchips.Duetotheuseof bunch-crossingmultiplexing (BC-mux)oneLVDS chip cantransmitthedatafrom two ADCs. Dueto coarserjet-elementstheLVDS usedfor datatransmissionto theJet/Energy Processortransmitsthedatafrom four channels.

Due to the complexity of the PPrAsicit hasits own review. Ihe PPrAsicdatapathcontainsa look-up table(LUT) fordatacalibrationanda Bunch-CrossingIdentificationunit (BCID) for unsaturatedandsaturatedtriggertowersignals.TheunsaturatedBCID unit consistsof a finite impulseresponsefilter (FIR filter) with configurablecoefficientsanda peakfinder. ThesaturatedBCID unit consistsof asetof registersandcomparators.Thereadoutdatapathcanrecorddatafroma pipelinememoryup to a level-1acceptrateof 100kHz for five time-slicesincludingtheBCID result.

3.1 MCM I/O Signals

TheMCM I/O signalscanbedividedinto threegroups:analoginput signals,digital outputsignals,controlandreadoutsignals.Thesesignalswill bedescribedin thefollowing.

Analog Input Signals

The analogtwisted-pairtrigger-tower signalsareseparatefor the electro-magneticandhadroniccalorimeter. They arereorderedby theReceiverStationin front of thePre-Processorto theazimuth-orientedarchitectureof thetriggersystem.One can distinguishbetweenPPMsexclusively assignedto em-signalsand thoseassignedto had-signals.OnePPMcoversa triggerspaceof 0.4 x 1.6 in the & and ' direction. This correspondsto 4 x 16 signalseach0.1 x 0.1 in & and' for thecentralregion ( &)(+*-,/. ). Thesignalmappingto PPMsin the forwarddirectionabove &102*�, . is describedin[PPM] where‘thinnedout’ cablesareusedto allow identicalPPMsto beused.Thedifferentialsignalsarecomingin viafour Sub-D37cconnectorson thefront panel.A footprint of theSub-D37cconnectoron thePPMboardcanbeseeninFigure3. Thepair numbersareorderedalongthefront-panelfrom top to bottom. A groupof four signalspairscover a0.2x 0.2areaclockwise.In orderto allow BC-multiplexing along ' insidethePPrAsic,a re-orderingof signaltracesisrequiredontheMCM. Up to theMCM, signaltracesarestraightforwardconnectedthroughtheanaloginputboards,usedfor signalconditioningand‘externalBCID’. On theMCM, single-endedoutputsof theanaloginput boardarereorderedin sucha way that signal1 and4 areconnectedto the PPrAsicchannels1 and2, andsignal2 and3 areconnectedtoPPrAsicchannel3 and4.

The voltagerange 3#46587�9;: of the ADC correspondsto 0 to 250 GeV transverseenergy depositedin the detector. Thetrigger-tower signal is bipolar shapedin caseof the Liquid-Argon Calorimeter(LAr), with an undershootof 3=A@B9;:(20%). It is unipolarin caseof theTile Calorimeter. Thevoltagerange3 46587�9;: is mappedto thedigitizationrange3#CEDGFof theADC. This is doneby theanaloginputboardin front of theMCM. Thiscircuit is shown in Figure4. Theboardhasa low impedanceoutputamplifierin orderto eliminategainvariationsintroducedby variationof theADC inputresistanceHJI >�K CEDGF . It is alsousedfor baselineshift andto createan‘externalBCID’ signalconnectedto thePPrAsic.Intrinsicgainvariationsof the ADC will be compensateddigitally by loadinganappropriatelook-up tablecontentinto the PPrAsic.Eachinput stageof the PPrMCMhasa low-passfilter to reducehigh frequency noiseascloseaspossibleto the ADC

3 FUNCTIONAL DESCRIPTIONOFTHE PPRMCM 10

12L

3M

4N

5O

6P

7Q

8R

9S

10111213141516171819

2021222324252627282930M

31M

32M

33M

34M

35M

36M

37M

161514131211109T

8U

76V

5W

43X

21 SIGNAL number

PIN numberYPIN number

Pair Shield 1-4Y

Pair Shield 5-8

Pair Shield 9-12YPair Shield 13-16

GlobalZ

Cable Shield[

Sub-D 37c Connector\

PPM boardPCB_top PCB_bottom

Figure3: Pinningof thePPMfront-panelconnectorfrom LAr calorimeters.

input. Default RC valuesare5nsfor manufacturing.If it turnsout, duringthefinal MCM test,thatthe input impedancevariationof the ADC ( ]_^a`�b cEdGe ) is effecting the gain, an adaptionof the resistorand capacitorvaluesis requiredtomatchthegaincriteriaby keepingtheRC valueconstant.This procedurewill bepartof thefinal MCM parametertestafterencapsulation.Thesecomponentsareaccessablefor later re-solderingon an ‘RC-balcony’. SeeSection5.1 for amechanicaldescription.Theanalogreturncurrentof theinputsignalsstageof theADC will bekeptseparateof thedigitalby introducingananalogground,connectedto adjacentpinsfor shieldingreasons.

Digital Output Signals

ThePPrMCMdeliversthreeBUSLVDS serialoutputstreamsataserialdatarateof 480MBd ( fGgh] ). Theuserdatarate,excludinga startanda stopbit, is 400Mbps( ijgh] ). Eachserialoutputis generatedfrom anDS92LV1021BusLVDSserializerfrom NationalSemiconductor. Thisdevice transformsa 10-bitwide parallelCMOSdatabusfrom thePPrAsicinto a singleBusLVDS serialdatastreamwith anembedded40 MHz clock. Two of theserialdatastreamscontainthedatato theClusterProcessor, which representenergy depositson the0.1 x 0.1 k and l grid. The third streamcontainsenergy depositsonthe0.2x 0.2grid,whichareto besentto theJet/Energy Processor. TheClusterProcessordatacontainsa 8-bit energy value,oneBC-muxflag bit, andoneoddparity bit. TheJet/Energy Processordatacontainsa 9-bit energyvalueandoneoddparitybit.

TheLVDS outputtracesarematchedto 100Ohmdifferentialimpedance.No pre-compensationcircuit is requiredon theMCM, sincetheLVDS signalsarerefreshedon thePPMmotherboard.A pre-compensationnetwork is only usedat theoutputstageof themotherboardLVDS buffer to drivethesignaloverafew metersof cable.Thiscircuit doesnot influencetheLVDS outputsectionof theMCM.

Link testsatBirmingham,Heidelberg, andMainz indicatelow bit-errorratesandacceptablelink performanceover20 mlong cables. The DS92LV1021 Bus LVDS Serializeris designedto work with the DS92LV1210 Deserializer, whichrequiresa clock-jitter betterthan150 ps. But, the TTCrx chip on the PPM may have a clock jitter of up to 250 ps,which makesit necessaryto usetheDS92LV1212A asan upgradeon the receiver end. This chip is an upgradeof theDS92LV1212devicewhichtoleratesaminimumof 450psjitter thetypicalvalueis 730ps. It maintainsall of thefeaturesof theDS92LV1212andis designedto beusedwith theDS92LV1021BusLVDS Serializer. Hence,a low jitter PLL atthePPMboardlevel is not requiredto ensurea clock jitter betterthan150psfor theLVDS Serializerusedon theMCM.

Control Signalsand ReadoutSignals

Thecontrolandreadoutsignalscanbesummarizedasfollows:

m I2C (Phos4)

3 FUNCTIONAL DESCRIPTIONOFTHE PPRMCM 11

differentialnanalogoInput

LineRec(Gain=1)

Gain=1.43,Offset: +1.75 to +2.19V,2 mV stepp

analog qSignal to r

FADC

ComparatorsOutPutt

Duration ofCal.Signalsabove Thresholdo

Bit#11 @FIFO latches "rise"

+u

-

+u -OPA4650

1k 1k

1k 1k

4k7

5656 LT1813

-+u

I2C"extBCID"

3.0 Vpp (Inv)

ThrDACv8-fold

MAX521

56-+uInv

MAX901

Comparators-+u

ZeroDAC8-fold

I2C10n

Ref=+2.5 V1k61k2

1k3

560

560

20

250

51

FADC-Ref+2.4 Vu

10n

AGnd

PPrMCM

FADC

AnIn_PCB

~ 5cm

PPrASIC

BaseLine Offset;(Gain=0.43, 2.5 V -> 1.0V)

1.2Vpp ~100p

RC ~ 5 nsec

33

1.0 Vppto digitise

Figure4: Block diagramof theanaloginputsignalgenerationcircuit

w JTAG (PPrAsic)w Serialshift register(PPrAsic)

The I2C interfaceis usedfor Phos4programming.TheJTAG interfaceis usedfor in-circuit testingandboundary-scanof the PPrAsic. The JTAG interfaceprovidesboundary-scanI/O, to pre-loaddefinedpadstatesandto scanthe valuesreceivedfrom theADC. This is a veryusefultestfeaturefor theMCM productiontestto identify connectivity problemsinside. The serialshift register is the main readoutpathof the MCM. It is connectedto a configurabledevice calledRemFPGAlocatedon the PPM.At the momentit is not intentedto usethe PPrAsicdaisy-chainoption, sinceroutingboardspaceonthePPMdoesnotseemto beaproblem.A temperaturemeasurementdiodeonPPrAsicwill beconnectedto anexternalresistor, whichallows to monitortheMCM temperaturevia thePPMCAN-businterface.

Readoutoperationsof thePPrAsicaretriggeredby a Level-1Acceptsignal,generatedby theCTPanddistributedby theTTC system.TheTTC systemdistributesall timing informationsynchronouslyto all destinations.This includestheLHCclock, thebunch-crossingnumber(BCID-number),aswell astheevent-number(L1ID) andbroadcastsignals.Also resetsignalsfor internalcountersto maintainsynchronizationfor thebunch-crossingnumberandLevel-1numberis distributedvia TTC. TheMCM will useTTC broadcastsignalsto trigger theLVDS SYNC pattern,aswell to trigger thePPrAsicresetandto startsynchronousreadoutandplayback. The following table is a summaryof TTC signalsconnectedtothePPrMCM.Pleasereferto thePPrAsicspecification[PPrAsic]andto theROD specification[ROD] for furtherdetailsaboutthereadout.

3 FUNCTIONAL DESCRIPTIONOFTHE PPRMCM 12

Table1:Symbol Parameter DefaultResetandBroadcastSignalsfrom TDCEVCNTRES PPrAsicevent-numberresetxzy|{-y|}

PPrAsicresetsignalBCCNTRES PPrAsicbunch-crossingnumberresetL1ACCEPT Level-1acceptsignalSYNCPLAYBACK startsynchronousplaybackSYNCREADOUT synchronizereadoutLVDS SYNC SYNCpatternfor LVDS

Inter nal Signals

ThePhos4DetectsignalontheMCM is connectedfromthePhos4Phi2outputto thePPrAsicFreqIninput. Thefrequencydetectioncircuit in thePPrAsicis ableto discriminatea frequency appliedat theFreqIn input. This frequency detectionis foreseento beusedfor monitoringof thePhos4phasedetectionoutput,whichsendsasignalwith a frequency between2 MHz and6 MHz, whenthePhos4chip is operatingcorrectly. ThePhos4chip losesall its programmedtiming settings,if amomentarylossof its clocksignalClk Phos4appears.In normaloperationthisshouldnotbethecasesincetheMCMClk Phos4pin is connectedto astableandfreerunningquarzoscillatoron thePPMmotherboard.

The PPrAsicfrequency detectorchecks,if the signalappliedat FreqIn hasa frequency higher than0.3 MHz. If thefrequency is lower or thesignalhasa constantvalue,theMCM Phos4Error outputis setto 1. The frequency detectionworksreliably for frequenciesup to 20MHz. Higherfrequenciesmaynotbedetectedcorrectly, dependingonhow phaseandfrequency arerelatedto the40MHz systemclockof thePPrAsic.TheFreqLostsignalis alsoincludedin aread-backstatusword.

Power-up Sequenceand Initialization

The Serializerhasa synchronizationmodethat shouldbe activateduponpower-up of the MCM. TheDeserializerwillestablishlock to this signalwithin 1024cycles,andwill flag lock status.Beforedatacanbetransmitted,theMCM mustbe initialized. Initialization refersto synchronizationof the LVDS SerializerPLLs to the local 40 MHz clock. AfterMCM power-upandPPrAsicresettheMCM is in ‘transparentmode’.Thismodewill bypass10-bitdatafrom theADCsto theLVDS Serializers.TheLVDS Deserializers,which arelocatedin theClusterProcessorandJet/Energy Processor,have to synchronizeto theMCM outputs.TheMCM Serializeroutputsareheld in tri-state,while theLVDS PLL locksto the40 MHz clock (LVDS TCLK pin). TheSerializeris thenreadyto senddataor SYNC patternsdependingon thelevelsof theSYNC1andSYNC2inputs. TheSYNC patternis composedof six ‘ones’ andsix ‘zeros’ switchingat the40 MHz input clock rate. Pleaserefer to the Serializerspecification[LVDS]. The transmissionof SYNC patternstotheDeserializerenablestheDeserializerto lock to theSerializer. Oneor bothof theSerializerSYNC inputshave to beassertedfor at least1024clock cyclesto initiate transmissionof SYNC patterns.TheMCM Serializerwill continuetosendSYNCpatternsaftertheminimumof 1024cyclesif eitherof theSYNCinputsremainshigh.

If theDeserializerloseslock, its ~ pin will go high. This mustbemonitoredby theProcessorsto detecta lossofsynchronizationandthesystemmustarrangeto asserttheSerializersSYNC1andSYNC2pin to re-synchronizethelinks.This takesat least1024clock cycles.TheSYNC1input pin is programmablevia theserialinterfaceof thePPrAsicandcanbeassertedby software,wheretheSYNC2pin is anexternalMCM pin which will besetvia a TriggerTiming andControl(TDC) broad-cast.

Theedgeof TCLK usedto strobein datais selectablevia theTCLK R/F pin. TCLK R/F highselectsthetherisingedgefor clockingdataandlow selectsthe falling edge.TheMCM outputs(DO ) transmitdatawhentheenablepin (DEN)is high, G xJ =highandSYNC1andSYNC2arelow. TheDEN pin maybeusedto tri-statetheoutputswhendrivenlow. The G xJ signalshutsdown theSerializerPLL andtri-statesoutputsputtingtheLVDS into a low power sleep

4 DESIGNEXPERIENCE 13

Table2:Symbol Parameter DefaultDefaultConditionsGenOut1 4..0 genericoutputsof PPrAsicchannel1 0b’00011GenOut2 4..0 genericoutputsof PPrAsicchannel2 0b’00011GenOut1 2 LVDS1SYNC2to CP 0b’0GenOut1 3 LVDS2SYNC2to CP 0b’0GenOut1 4 LVDS3SYNC2to JP 0b’0GenOut1 0 LVDS1 GJ 0b’1GenOut1 1 LVDS2 GJ 0b’1GenOut2 0 LVDS3 GJ 0b’1LVDS1 DEN externalMCM pin 0b’1LVDS1 TCLK R/F externalMCM pin 0b’1LVDS2 DEN externalMCM pin 0b’1LVDS2 TCLK R/F externalMCM pin 0b’1LVDS3 DEN externalMCM pin 0b’1LVDS3 TCLK R/F externalMCM pin 0b’1

mode.After a power-up of theMCM anda resetof thePPrAsicthedefaultsin Table2 ensurethatall LVDS Serializersareenabledto transmitvalid data.

ThethreeBUS LVDS serialoutputstreamswill bebufferedon thePPMto berefreshedbeforetransmissionvia twisted-pair cableson thePPMbackplaneconnectors.Currentlytwo optionsexist for thatpurpose.First anin-housedevelopedASIC called‘LFAN’, which is an8-fold differentialLVDS buffer chip providing sufficientoutputcurrentto driveLVDSsignalsacrossthe cableconnectionbetweenprocessorcrates. Fan-outof LVDS signalsto different processorsat boundariesis doneby distributing theserialsignalto two LFAN inputs. Thesecondoption is to useanXILINX VirtexFPGAwith LVDS in- andoutputpins.Fan-outin thiscaseis doneby programmingthedevice. All LVDS signalswill beterminatedwith a100Ohmdifferentialimpedanceat theinputof thebuffer chip.

4 DesignExperience

Thedesignof thePPrMCMwill benefitfrom thedesignexperienceestablishedby variousdemonstratorprojects.First,ademonstratorMulti-Chip Module(PPrD-MCM)wassuccessfullybuilt andtested(see[Pfe99/2] for details).Thedemon-stratorMulti-Chip Module hada sizeof 15.9cm and it consistedof 9 dies. The MCM wasdesignedwith the samefeaturesize(100 m) asthe PPrMCM andit wasfabricatedin the samelaminatedMCM-L processofferedby WürthElektronik. A Flip-Chip mounttechniquewasinvestigatedandcoolingwasimprovedby cutoutareasin the layerstruc-tureto dealwith 12.25W powerdissipation.ThePPrD-MCMwastestedaspartof a modularPre-Processortestsystem,wheretransmissiontestswith 800MBd andreadouttestshave beenperformed.Comparedto this MCM thePPrMCMwill belessdemandingin termsof power, temperature,andlink speedandhenceit canachieveanimprovedreliability.

Furtherdevelopmentstowardthefinal PPrMCMwhereinvestigated.This ‘intermediate’stepbetweenthedemonstratorandthe final PPrMCM wasset-upto test the interplayof new componentsandto evaluatelayout properties.The dieversionsof ADC, LVDS andPhos4weremountedona CMC cardcalledECMC(see[Ste00] for details).

Link testsatBirmingham,Heidelberg, andMainz indicatelow bit-errorratesandacceptablelink performanceover20 mlongcables.If theremightbeaproblemusingLVDS chipsetsin theTriggeronecouldof causehavetheG-link optionasa fallbacksolutionimplementedontheMCM. Thiswasprovedto befeasibleon thePPrD-MCM.Theimplicationwouldbe to re-designthePPrMCMlayoutandto usecutoutareasto dealwith an increasedpower dissipationfor theG-links.But seriouslyfolks, why shoulda device, lower in power, lower in speedandlower in temperaturebe lessreliablethanG-links?

5 CHARACTERISTICS 14

5 Characteristics

ThissectiondescribesPPrMCMcharacteristicslikemechanical-,timing-, andelectricalcharacteristics.

5.1 MechanicalCharacteristics

Thephysicaldimensionsof thePPrMCMareshown in Figure5. It will be20 mm wide and70 mm long with clampson eachendto arrestit andallow a quick replacementif required.On eachenda 60 pin SMD connectorfrom SAMTEC(BSH-030-01-F-D-A)[Sam] connectsit to thePPMmotherboard.Thechipsareencapsulatedwith a lid in betweenthetwo SMD connectors.Thelid will begluedwith electricallyconductingepoxyto the layercompound.It will actasanEMI-shieldingdeviceandit will befilled with asiliconegel to removeatmosphereandto protectthedicefrom moisture.The four layercompoundwill begluedelectricallyisolatedto a 800 m thick coppersubstrate.The substrateitself isnot grounded,becauseit doesnot actasa shieldingdevice. The fourth layer ‘groundplane’ is exclusively usedfor thispurpose,whichallowsawell definedthicknessto ensuresteadyimpedancefor thedesignof 100OhmLVDS microstrip-lines. On thebacksideof thesubstratean8 mm heat-sinkis gluedto it. Thetotal height of theMCM will be15 mm. SeeTable3 for MCM dimensions.Dueto theheightof theconnectorheaderon themotherboardtherewill beaclearanceof 2 mmbetweenthemotherboardandthelid. ThisallowssmallSMD componentsto beplacedbetween,closeto theconnectorpins,e.g.bypass-capacitorsfor powersupplylines.

clamp

3

lidconnector

50 20

70

1512

4

1

Figure5: MCM physicaldimensions

5.2 Timing Characteristics

Theinternaltimingcharacteristicof thePPrMCMhasto follow therequirementsgivenbyeachchipspecification.Figure6shows aninternalPPrMCMtiming diagramto illustrateset-updelay, outputdelay, andhold delayfor eachchip. Pleasereferto theindividualchipspecifications.

Dueto theprogrammabilityof theADC digitizationstrobeto theanaloginputsignal,theADC outputdatawill beshiftedaccordingly. Hence,thePPrAsicmustbeprogrammeddependingontheactualdelayvalueusedby thePhos4chipto shifteachADC clock individually. The PPrAsicclock edgeusedto latch the ADC input datacanbe programmedchannel-by-channelaswell asthedatabit from theexternalBCID. This synchronizationis requiredto clock valid datainto theLVDS Serializers.TheLVDS Serializerclock will beselectedto latchthePPrAsicdatawith thefalling edge.This maybechangedafterdetailedtiming measurementsat thePPrAsichave provenits hold delay  ¢¡?£ ¤�¤¦¥8§�¨;©«ª (5 ns)andoutputdelay  ¢¬8£ ¤�¤¦¥8§�¨;©«ª (7 ns).SeealsoTable3 for theswitchingcharacteristics.

6 PRODUCTIONTECHNIQUE 15

tod,Phos4

thd,PPrAsict sd,PPrAsic

tod,ADC

tod,LVDS

thd,LVDSt sd,LVDStod,PPrAsic

select select40 MHz

6.5ns

PPrAsicClkLVDS_TCLK

System Clock:

25ns

25ns

ADC Encode:

Phos4 out

Analog ADC_In:

ADC out:

PPrAsic out:

LVDS out:

0−24ns

0ns

5ns9ns

7ns1ns

3ns

Figure6: MCM timing diagrams

5.3 Electrical Characteristics

ThePPrMCMrequires3.3 V and5 V supplyvoltages.Only theADCs require5 V. TheADC outputstagewill have a3.3V supplyto matchtheoutputlogic levelsto beCMOScompatible.ThePPrAsicandtheLVDS SerializershaveCMOScompatibleI/O logic levelsexceptof thehigh-speedserialdataoutputsof theLVDS chips.Pleasereferto Section4,wheretestsof theADC andLVDS chipshavebeenmade.Oneof themajoroutcomesof thesetestsare,thatnocurrentlimitingresistorsarerequiredon theMCM dueto thereducedcapacitive loadof shortchipconnections.

6 Production Technique

Thedesignprocessof the laminatedmulti-layerstructureis basedon an industrially-availableproductiontechniqueforhigh-densityprintedcircuit boards.Theprocess,which is offeredby Würth Elektronik [Wue] is calledTwinFlex. It ischaracterizedby its useof plasmaetchedmicro-vias,whereplasmais usedfor ‘dry’ etchingof the organicinsulatingPolyimide.Radicalsandionsfrom a plasmareactchemicallywith organicmoleculesaccessiblethroughopenareasin alayermask.Reactionproductsareremovedinstantaneouslyduringtheetchingprocess,becauseof thereducedpressureanddensityof theplasmaphase.Plasmaetchingenablesprecisevia contactsbetweenlayerswith a diameterof 100 m.

6 PRODUCTIONTECHNIQUE 16

Table3:Symbol Parameter Conditions Typ UnitsElectricalCharacteristicsDVCC digital powersupply 3.3 VDGND digital ground 0 VAVDD analogpowersupply 5 VAVCC analogpowersupply 3.3 VAGND analogground 0 V®¯E°G±

powerdissipation DC 595 mW®²�²�³ ¯�´;µ«¶powerdissipation (to bedefined) 1200 mW®²¦·?¸ ´º¹powerdissipation @40MHz 200 mW®»=¼ °¾½powerdissipation @40MHz 106 mW®¿ ± ¿powerdissipation (to bedefined) 4100 mWÀJµaÁ� ¯E°G±input impedance 250 à 50 OhmÀJµaÁ� ¿ ± ¿input impedance 300 à 1% OhmÀ ¸8ÄÅoutputimpedance differential(DO- to DO+) 100 OhmÀj´ÇÆ Ä?ÈɳËÊtraceresistancepersquare ÌÎÍ+ÏAÐÒÑÔÓÔÕÖ)Ï×�ØÚÙÜÛÝ 0.069 Ohm

AnalogInputÞ=¯E°G±analoginputvoltagerangeADC 0-1 VÞ Å6¸8ß�Ê;³trigger-towervoltagerange 0-2.5 VÞ Ä ÁAà Ê;³bipolarLAr under-shoot 20 %ÞÚ´ ÈáÅanalogtrigger-towersaturationvoltage 3.0 Vâäãæå|¿ ± ¿differentialnon-linearity10-bits 10.15MHz sine,@40MHz ÃJ×�Ð/Ó LSBçèãæå¿ ± ¿integralnon-linearity10-bits 10.15MHz sine,@40MHz ÃjÓ LSBéêãìëjíJ¿ ± ¿effectivenumberof bits 1.8MHz sine,@40MHz 8.9 ENOBséêãìëjíJ¿ ± ¿effectivenumberof bits 9.9MHz sine,@40MHz 7.8 ENOBs

SerialLVDS OutputÞ=î¦ïhigh level outputvoltage

çÉîðï=-9mA 2.93 VÞ=

low level outputvoltageçÉîð»

=-9mA 2.0- 5.0 Vñ âhÀserialdatarate @40MHz 480 MBdòâhÀuserdatarate @40MHz 400 Mbps

SwitchingCharacteristicsó ¸ à ²¦·?¸ ´º¹outputdelayPhos4 programmabledelay 0-24 nsó ¸ à ¯E°G±outputdelayAD9042 +2 ticks 9 nsó ¸ à ²�²�³ ¯�´;µ«¶outputdelayPPrAsic (+10CP, +11JP)ticks 7 nsó ¸ à »=¼ °¾½outputdelayDS92LV1021 +2 ticks 3 nsó ¸ à ¿ ± ¿MCM outputdelay3+10(11)+1 (+14CP, +15JP)ticks 3 nsó ´¢à »=¼ °|½set-updelayDS92LV1021 1 nsó · à »=¼ °¾½holddelayDS92LV1021 6.5 nsó ´¢à ²�²�³ ¯�´;µa¶set-updelayPPrAsic 0 nsó · à ²�²¦³ ¯�´;µ«¶holddelayPPrAsic 5 ns

MechanicalCharacteristicsâôöõ  ¿ ± ¿MCM substratedimension heat-sink 70x 20 mm÷â ôöõ  ² ±ðøMCM substratedimension incl. connectorhead 70x 22 mm÷âù ¿ ± ¿totalMCM height inc. heat-sink 15 mmãÎú ¸ ÁAànumberof wire bonds incl. testbonds 416ãûܵüÁnumberof connectorpins 120ãÎàáµ Ênumberof dice 9ãêýüÈBõÜÊdznumberof routinglayers inc. groundplane 4

ThermalCharacteristicsþ ¿ ± ¿max.MCM temperature forcedconvection2m/s 55 ÿ C� þ_í�� ¿ ± ¿MeanTimeBetweenFailures � àáµ Ê = 1 ppm 111.111 hÀ ¿ ± ¿reliability 92.4 %À�� ¶8 ¿ ± ¿junction-to-caseresistance 7.3 ÿ /W

6 PRODUCTIONTECHNIQUE 17

Thenumberof vias,which maybeetchedat onceis not limited anddoesnot effect the complexity of a designanditsprice.

6.1 Layer Structure

The body of the PPrMCM is a combinationof threeflexible Polyimid foils laminatedonto a rigid coppersubstratetoform four routing layers. Herea descriptionof the layer cross-sectionis given in the way they aremanufactured:aninner-foil of 50 � m thickness,alsoreferredto ascore foil, carries18 � m copperplateson eitherside.Plasmaetchingisusedfor ‘buried’ via connectionsto adjacentlayersandroutingstructuresareformedin copperusingconventionaletchingtechniques.Thecorefoil is surroundedby outerfoils of 25 � m Polyimid,whicharecopperplatedonly ononeside.Figure7 shows a sideview of eachflexible foil prior to laminating. The actualcontactthroughthe corefoil is accomplishedwith electroplatedcopperandafter that, theroutingstructureareformed. Theelectroplatingprocessincreasesthetrackthicknessfrom 18 � m to 25 � m. Thesurfacemetallurgy of layer1 will begoldplatedwith 100nmto allow wire-bondinguniversallywith 25 � m Al wires.

‘buried’ via

Outer−foil

Core foil

Outer−foil

CopperPolyimid

Copper

Polyimid

Copper

Polyimid

Copper

Plasma etched

Figure7: MCM layerdefinition

The applicationof adhesive accomplisheslaminating. Then insulatingPolyimid is removed by plasmaetchingabovea ‘target’ padto form a surface‘blind’ micro-via contactfor the ‘outer’ foils. After electroplatingof copper, routingstructuresfor the top andbottomlayer areetchedto form final connections.Figure8 shows the final laminatedandflexible partof theMCM afteretchingof outerroutingstructures.

Routing

Staggered

structures

via

Figure8: Cross-sectionwith staggeredvia connectionthroughall layers.

As shown in Figure8, a combinationof threevias is neededto accomplisha contactfrom the top to thebottomlayer.A ‘blind’ surfacemicro-viaconnectslayer1 to layer2, a ‘buried’ via connectslayer2 to layer3, andfinally a surfacemicro-viaconnectslayer3 to its destinationon layer4. Drilled viasareavoided,becausethey would needa morerigidandthereforethickercorefoil, whichwouldunnecessarilyincreasethetotal thermalresistanceof thedesign.

Theflexible multi-layeris finally gluedontoanelectricalisolatedcoppersubstrate(layer4 actsasgroundplane).Diceareconnectedto bondpadsonthetoplayerof thecross-sectionusingastandardultrasonicwire-bondtechnique.Componentssuchascapacitorsandresistorsareconnectedto themulti-layerstructureusingsurface-mounttechnology. AdvancedFlip-Chip mountingwasinvestigatedbut is omittedfor the final PPrMCMto reduceproductioncomplexity. Staggeredviasaregroupedascloseaspossibleto form thermalvias, which improve heatconductionto the substrateunderneaththeADCs. Due to the largenumberof semiconductordevicesandMCMs at the Pre-Processorboardlevel, a high-densitySMD connectoris usedto permita quick replacementof a brokenMCM. If built-in testshave identifieda brokenMCM,it canbereplacedwithout any soldering.TheMCM is encapsulatedwith a lid andfilled with a silicon gel asanelasticencapsulationmaterialto absorbstressandto hermeticallyprotectall componentsfrom atmosphere.

7 SCHEMATIC 18

� � � �� � � �� � � �� � � �� � � �� � � �� � � �� � � �

Silicon

Copper

Bond Pad

Solder Mask

Line� �� �� �� �� �� �� �� � � � �

� � � �� � � �

� � � �� � � �

die2padD

cu2pad

W

D

liney

,pad

x,pad

die2cuD

die2maskD

D

D

Figure9: MCM designrules

6.2 FeatureSizeand DesignConstraints

TheTwinFlex MCM-L technologyis offeredby its manufacturerwith norelationto any specificphysicallayouttool. Thecompany doesnot supporta softwareproductwith librariescontaininginformationonmaterials,cross-section,or designconstraints.The designeris free to choosea suitablelayout tool, andhe hasto ensurethat all processparametersandconstraintsgivenby themanufactureraresetup properly. Thelayout tool is thenableto checkthe layoutagainstgivenconstraintsautomatically, which is referredto asDesignRuleCheck(DRC).

For thePPrMCMthephysicallayouttool APD (AdvancedPackageDesigner, [Apd97]) wasused.It is a layoutsystemforcreatingandoptimizingmicro-electronicpackages,suchasMCMs or Single-ChipModules(SCM). APD is partof theintegratedsoftware,whichtheCadencecompany [Cad] sellsfor accomplishingthemajorphysicallayouttasks.APD canalsobeusedtogetherwith otherCadenceproducts,namely:Concept[Con96] for schematiccapture,Thermax[The97]for thermalanalysis,SigNoise[Sig97] for signalnoiseanalysis,andEMC [Emc97] for checkingof electro-magneticinterferencerules. Following this productdivision, onecandefineconstraintsin eachof theseproducts,e.g. for thegeometricallayout,for themaximumallowedmoduleandcomponenttemperature,for theelectricalsignalintegrity, andtheelectro-magneticinterference.

Table 4 describesthe appliedlayout constraintsas they were arrangedin conjunctionwith Würth Elektronik for thePPrMCM. The layout constraintsare illustratedin Figure 9. A characteristicnumberof 100 � m was chosenas theminimum allowed featuresize. No line or shapeof the layout is allowed to be smallerthanthis number. The etchingtechniquecanproducesmallerroutingstructuresof 80 � m, but 100 � m wasusedto lower theMCM price andto staywithin a moreconservative rangefor which the TwinFlex processhasshown bestresults. The minimum featuresizeappliesto the line spaceandwidth of coppertracksaswell asto thesolder-maskspaceandwidth. For thedistanceoflinesandshapesto cutoutregionsandfor themilling tool radius,asizeof 500 � m wasdefined.Via constraintsaredefinedby aholediameter, to form thecontactto anadjacentlayer, andthediameterof a surroundingcontactandtargetpad. Table4 lists their valuesfor ‘buried’ micro-vias,and‘blind’ micro-vias.Thesevia typescanbecombinedto form a staggeredcontactthroughall four signallayers. Apart from the definitionof alternatingmaterials,their thicknessis importantfor both thermalandelectricalcharacteristics.SeeTable4 for the thicknessof eachcross-sectionlayer.

7 Schematic

ThePPrMCMschematicwascreatedin Conceptasfront-endtool for thephysicaldesignentry. Conceptis part of theCadencedesignwork frame. It canbe usedin combinationwith the simulationtool Analog Workbench(AWB) thatCadenceprovidesfor accomplishingmixed-signalsimulations.All schematicpagesareincludedin this document.TheTOPpage(Figure10) wasusedasa top-level symbolin a mixed-signalsimulationasdescribedin Section8.1. Pageone

7 SCHEMATIC 19

Table4:Symbol Parameter Conditions Typ UnitsGeometricalLayoutCharacteristics���������

line width min featuresize 100 � m� �"!$# %'&)(bondpaddimension singlewidth 300x 150 � m*�+(,�-� * %.&.( distancesilicondie edgeto bondpadedge 750 � m�+/10 * %.&.( copperto bondpadedge 550 � m�+(,�-� * /10 silicondieedgeto copperoverlap 200 � m� (,�-� *32 &.465 silicondieedgeto solder-maskcut-out 200 � m� /10 *32 �7�8� copperto mcmboundaryspace(milling tool space) 500 � m

Via Characteristics‘buried’ micro-viaholediameter 100 � m‘buried’ micro-viapaddiameter 300 � m‘blind’ micro-viaholediameter 100 � m‘blind’ micro-viapaddiameter 350 � m

LayerCharacteristicsSurfacemetallurgy (Au) thickness 100 nmSurfacemetallurgy (Ni) thickness 5 � mCoppertracks thickness 25 � mOuterPolyimid insulator thickness 25 � mEpoxygluebetweenlayers thickness 10 nmCorePolyimid insulator thickness 50 � mEpoxyglueto substrate thickness 50 � mCoppersubstrate thickness 800 � mAluminium heatsink thickness 8000 � m

(Figure11) is theADC partof theMCM, Pagetwo (Figure12) thePPrAsicandPhos4schematic,pagethree(Figure13)is theLVDS Serializerschematicandfinally pagefour (Figure14)shows theconnectorpin to signalallocation.

7 SCHEMATIC 20

Figure10: MCM schematicTOP

7 SCHEMATIC 21

Figure11: MCM schematicpage1

7 SCHEMATIC 22

Figure12: MCM schematicpage2

7 SCHEMATIC 23

Figure13: MCM schematicpage3

7 SCHEMATIC 24

Figure14: MCM schematicpage4

8 SIMULATIONS 25

8 Simulations

Electricalandthermalsimulationswereof useduringthedesignof theMCM. A circuit simulationwasset-upandusedto checkfor connectivity errorsduringthedesign.Thissimulationwill alsobeusedfor thefinal MCM productiontesttogeneratedigital andanalog‘test vectors’aswell as‘expectedvectors’(seeSection12). The thermalsimulationwasofusefor thetemperaturebudgetof thePPM.

8.1 Cir cuit Simulations

Figure15showsthescopeof themixed-signalsimulation.Analogcalorimeterinputdatato theSimulationweregeneratedby a Pspicesimulationof theLAr triggertowerelectronic.Otheranalogstimulusdatacanbegeneratedwithin theAWBsimulation;likeclockpulses,noise-,or time-jittereffects.Thissimulationwasusedto checkset-upandhold times,ADCclock phase-adjustmentusingthePhos4.It canalsobe usedto simulatethe effect of e.g. variationsof theADC inputresistance.‘Basic’ simulationmodelsfor theADC, Phos4,andLVDS werewritten in VerilogA. For thePre-ProcessorAsic theactualVerilogcodewasused.This simulationis of importanceto generateexpectedresultvectorsto beusedinanautomatedproductiontestrequiredfor suchacomplex mixed-signaldevice.

PPrAsicADC LVDS

Phos4

Tower

clk

VerilogA

VerilogAVerilog

VerilogAPSpice

rec.

Spice

Analog Workbench

Figure15: Mixed-signalsimulationandtestvectorgeneration

8.2 Thermal Simulations

For analyzingthethermalcharacteristicsof thedemonstratorPPrMCM,theanalysistool Thermax[The97] wasused.It ispartof theCadenceproductdistribution [Cad] andit is integratedin theAPD (AdvancedPackagingDesigner,[Apd97]).After a Thermaxsimulationis complete,onecanview two- andthree-dimensionalmapsthatcanbeoverlaidon theAPDdesign.

For eachdie,material,size,andthermalresistancefrom thejunctionto thedie attachmentweredefinedandprovidedina componentlibrary for simulation. Becauseof equaltreatmentof eachcomponent,thesimulationcannottake specialcoolingapproachessuchasthermalviasof thecross-sectioninto account.Hence,thesimulationresultsfor theMCM mustbeseenasa worstcasesystemsimulationto estimatemaximumratings,andto observe thethermalbehaviour dependenton variationof boundaryconditions.From thermalspread-sheetcalculationsthe individual die cooling is improvedbyabout87% by usingthermalvias[Pfe99/2]. But, becauseof thelossof all routingareaunderneathachip,suchacoolingmechanismwasonly appliedto theADCs.

9 LAYOUT 26

49.348.146.645.544.243.041.740.439.237.036.635.334.132.831.530.229.027.726.425.1

T [°C]

BOARD MAP

Figure16: Temperaturesimulationfor chevron-likeMCM placment

Figure16 shows the heatedareaof thePre-Processormotherboardequipedwith 16 PPrMCMs. The PCB is heatedupfrom theinitial temperatureof 25 9 C to themaximumof 49.3 9 C. A fanis blowing vertically from thebottomto thetopandthetemperaturemapis overlaidon thePPMlayout to identify theMCM positions.Thetemperaturesimulationhasshown goodresultsfor a‘chevron-like’ MCM placement.In addition,thisplacementseparatesanalogsignalsfrom digitalsignals.

9 Layout

Figure17 shows anoverview pictureof all MCM routinglayers.Onecanseethecoppershapesfor thedie attachment,SMD pads,bondingpads,andthetopgroundshielding.Thechiplocationis, from left to theright: Phos4,ADCs,PPrAsic,andLVDS.Eachconnectorhas60pins.Theleft onecarriesonly analog,power, andslow controlsignalswhereastherightonecarriesdigital, clock,andhigh-speedserialoutputsignals.As aguideline, thefollowing pointshavebeenconsideredduringthelayout:

: Analog and digital parts: Analog chipswereseparatedfrom digital chips,andpower andgroundsignalswerekeptseparate.Thisappliesalsoto thesignalrouting.

: Componentplacement: Optimumdistanceto othercomponents,to achieve uniform heatdistribution werecon-sidered.Extraspaceneededfor componentmountingtechnologies,e.g.wire-bondingandsolderingwereforeseen.

: Signal routing: Becauseof thehighsignaldensity, noautoroutingtool wasused.Thelayoutis fully handcrafted,with two signal layerssurroundedby the bottom groundplaneand a top layer, consistingof shieldingshapes,bondingpads,andSMD pads.Onesignallayerwasmainly usedfor routing in x-directionandtheotheroneforroutingin y-direction.

9 LAYOUT 27

Figure17: All MCM layers

Figure18: MCM layer1

; Track width: Wider power trackswereusedto limit thevoltagedropon power rails. For a MCM copperroutinglayer a resistivity of 1.724

9 LAYOUT 28

Figure19: MCM layer2

Figure20: MCM layer3

` Testpads: Testpadsareplacedon thetop layer. During theMCM pre-testat Heidelberg, needleprobescanthenspy onsignalswhichareotherwiseburiedin thelayercross-section.This is importantduringtheMCM test,whereeachchipneedsto betested.SeeSection12.

` Thermal vias: A thermalvia is a kind of staggeredvia, which connectsthroughthecross-sectionto providegoodthermalconduction. Attention mustbe paid to chip mountingon thermalvias, becausethe silver glue needstofill up all micro-via holesto remove air betweenchip andcoppershape.Whenthe MCM is heatedup with airunderneath,theattachmentwill popup,which is oftenreferredto as‘popcorn’effect. Thiswill beavoided.

` EMI shielding: Layerfour of thelayercompound(Figure17) is usedasgroundplaneandelectro-magneticshield-ing layer. Onthetoplayer, across-hatchedgroundshapesurroundingbondingandSMD padsis usedto improvetheshieldingfurther. This reducestheelectro-magneticinfluenceof signalsto eachotherandit stabilizesthegroundpotential.A cross-hatchedshapeis neededbecausedryingmoisturecomingoutof thecross-sectioncandestroy theMCM.

` Chip attachment: Coppershapesbeneatheachdiearerequiredto connectthediesubstratewith its voltagepoten-tial.

` Solder-mask: A solder-maskis usedto preventshortcircuitsduringsolderingof SMD components,andto protectbondingpadsfrom thedieattachmentglue.

Individual routing layersareshown in Figure18 for layer1, in Figure19 for layer2, in Figure20 for layer3, andthecommonDGND groundplaneon layer4 is shown in Figure21. On eachplot thefootprintsof dice,SMD capacitorsandSMD connectorsareincluded.

10 YIELD AND SPARE POLICY 29

Figure21: MCM layer4

Table5:Parts Production # Running # Spares Spares Testing Yield Defect

(inc. yield) (pluggedon) (preserved)Yield andsparepolicyPPMs 143 128 0 13 (10%) 2 100% 0PPrMCMs 2870 2048 240 572(25%) 10 75% 957MCM substrates 3866 3827 99% 39PPrASIC 6378 3827 60% 2551AD9042 17009 1530 90% 1701Phos4 4037 3827 95% 210LVDS 12757 1148 90% 1276Socket 7732 7654 99% 78Header 4623 4576 99% 47Lid 3866 3827 99% 39HASEC 3827

10 Yield and Spare Policy

ThePre-Processoris of importancefor therunningof theATLAS experiment,becauseall theLevel-1CalorimeterTriggerinputdatahave to go throughit. In casethatthePre-Processorneedsto berepaired,a quickexchangeof brokenmodulesis required.Therefore,it is notdesirableto havedifferenttypesof modulesimplyingalargesetof differentsparemodules.Hence,all thePre-ProcessorModulesandMulti-Chip Moduleswill beidentical,having thesamefunctionality.

Systemfailuresareoftencausedby acombinationof temperatureandvibration.Therefore,low temperatureoperationwasoneof themajorobjectiveswhendesigningthePPrMCMto improvethesystemreliability. ThePPrMCMconsistingof 9dice,eachhaving anassumedfailurerate a of 1.0partpermillion hours.TheMeanTimeBetweenFailures(MTBF bdceb )is 111.111hours.Theprobabilityof zerofailuresover oneyearis 92.4% (seeEquation1). This makesit obviousthatconnectorsfor thePre-ProcessorMCM areessential,becauseanexchangeof a Pre-ProcessorModuleasa wholein caseof anMCM failureis of coursenotaffordablein termsof sparesandcosts.

ThePPrMCMreliability f is definedas:fhg8ikjml noBp$q$r ots"ovu wdx�y3z {}|d~ bdcbi k a (1)

11 MANUFACTURING 30

11 Manufacturing

The developmentanddesignof the PPrMCM wasdoneby the University of Heidelberg, whereasthe final productionof 2780MCMs needsto bedonein conjunctionwith externalcompanies.The four layerMCM substrateincluding the800 m coppercarrierwill bedoneby WürthElektronik[Wue]. Theassemblyof dice,SMD components,wire bonding,andencapsulationwill bedoneby Hasec[Has]. Alternativemanufacturershavebeenlookedat,but thementionedabovesatisfiesourneedsfor cooperation,quality andprices.Thelid andheat-sinkincludingclips at eachendwill beprovidedby us.

Theproductionstartswith a pre-productionof 64MCMs to fully equip4 PPMs.ThesePPMswill bepartof theATLASLevel-1 CalorimeterTriggerslicetestandto actasa datasource.UsingtheATLAS terminologythesemoduleswill benamedmodule-0devices.BeforethisproductioncanactuallybestartedtheMCM have to havea pre-testwhereerrorsinthedesigncanbeidentified.As partof this pre-testa movableMCM testset-upwill bedeveloped,which is requiredtotesttheMCM at themanufacturesite. Thesmallvolumepre-testwill include10 MCM. Thesemoduleswill bebuild attheASIC laboratoryof theUniversityof Heidelberg. This assemblyprocedurewasalreadyappliedto thedemonstratorMCM includingultrasonicwire bonding,chipattachment,andsoldering.Encapsulationat thispointwill notberequired.

Theproductionsequenceis linkedwith testsat variouspoints,becauseit is not affordablein termsof yield andpricestojust identify known goodMCMs andto sortout defectdevicesaftera wholebatchwasmanufactured.Thefollowing listprovidesthesequencein which thePPrMCMwill bemanufacturedandtested.

1 Production: Substratelayercompound

2 Test: Electricaltest

3 Test: Bondtest

4 Assembly: Silk-screenprintingof solderpaste

5 Assembly: Placementof SMD components

6 Assembly: SMD reflow soldering

7 Assembly: Chipattachment

8 Assembly: Ultrasonicwire-bonding

9 Test: Electricalconnectiontest

10Test: MCM testandrepairprocedure

11Assembly: Encapsulation,lid andsilicongel

12Test: Performancetest(notpartof theproduction)

Point1 and2 will takeplaceatWürthElektronik[Wue]. Point3 to 11will bedoneatHasec[Has]. Thefinal performancetestandchangesto theinput RC-filter on theMCM will bedoneat Heidelberg. SeeSection3.1 for theuseof the ‘RC-balcony’. The first electricaltestat Würth checksfor manufacturingerrorsof the MCM substrateagainstthe ‘netlist’provided. This testwill rejectbrokenvia connectionsandshort-cuts.The secondtest locatedat Haseccanbe seenasa quality inspectionof the deliveredsubstratesto ensurebondabilityon its surfacemetallurgy. After assemblyof allcomponentsanelectricalconnectiontestchecksfor wire bondconnectionsby measuringtheinput resistanceof thechipI/O stages.Badwire-bondconnectionscanbedoublebondedbecauseof anextraspacethatis foreseenontheMCM bondpadlayout.Point10 in theproductionsequenceis probablythemostimportanttest,becausetheyield of thecommercialADC andLVDS dicewill not be100%. We expectto have failureson chipsandhencewe needto replacethemon theMCM. This testneedsto besufficientcomplex to find theerrorandto identify thedefectchip. Seethefollowing Section

12 TESTING 31

12 for a descriptionof the planedtestset-up. For the repairproceduretwo optionsexist. The first preferedoption isto remove thediceby heatingthecoppershapeon which they aregluedto. This worksfine for chip footprintswithoutthermalvias. It is lesssuitablefor theADC chipswherethermalviasprovideagoodthermalcontactto thecoppercarrier.EssentialheatingtheADC meansheatingtheMCM andthis is not desirable.In thiscase,optiontwo hasbeenlookedat,which justmountsaseconddieon topof abrokenone.This is quiteacommonandeasywayto exchangedicebut maybenotvery ‘esthetic’.

12 Testing

Thissectiondescribesa testset-upwhichwill beusedaspartof a repairprocedureatHasecandit will alsobeusedfor afinal performancetestatHeidelberg. A fastandautomatedtestto say‘yes’ or ‘no’ is requiredto identify chipandMCMfailures. Hence,a mixed-signalsimulationof the full MCM including the chip logic is requiredto generateexpectedresultsonecancheckfor. Sucha simulationwasdescribedin Section8.1. Analog stimulussignalswill be generateby anarbitraryfunctiongeneratoror by a moresuitablevideoRAM, modifiedfor thatpurpose.This device will thanbeprogrammedby digital datawhichwasusedduringsimulation.The‘real’ outputof theMCM canthenbecheckedagainstwhatwassimulated.Thecomparisoncanbeexecutedin software(HDMC) or in programmablehardware.Becauseof itsanalognature,theMCM testwill haveboundarycriteriawithin theresultshouldstay. For example,aparameterrejectioncanbedoneby ignoringtheLSB endof a dataword,seeFigure22.

PPrMCM

RAMVideo

10

00

01

11

1

all MCMs at Hasec

00

00

11

1config / set−up

digital results vektors

LVDSrxCMC

digital stimulus vectors

1) assembly:

2) functional test:

3) repair:

4) encapsulation:

5) "full" test: performance measurements, parameter rejections

final encapsulation at Hasec

exchange defect components at Hasec

−> first test of ADCs at 40 MHz & LVDS at 480 Mbit/se.g. power, bonding; using Jtag and "transparent" PPrAsic mode (10bit)apply analog & digital stimulus for functional test

Figure22: MCM testsequence

The testhardwarewill be built from a modularVME basedtestsystemusedto build a small-scaleversionof the Pre-Processorbasedon theexisting prototypecomponents.Thebasisof themodularPre-Processortestsystemis a general-purposemotherboardonwhichseveraldaughter-cardsprovidethespecialfunctionality. Thetestset-upmayconsistof twosuchmotherboardswhereCMC cardscanbepluggedinto cardslots.OneCMC cardcarriesthePPrMCManda secondCMC cardcarriesanLVDS receiver. SeeFigure23. The testwill beset-upandanalyzedby theHardwareDiagnosticMonitor andControlsoftware(HDMC) [Sch99].

A CHIPFOOTPRINTS 32

BG

VideoRAM

sync.

PC

PPrMCM

CMC card

R

Motherboard

compare with vectors

VM

E

VM

E

Motherboard

LVDS receiver CMC

set−up

configreadout

readout

HDMC

Figure23: MCM testset-upatMCM assembler

A Chip Footprints

This appendixprovides the chip footprints as usedfor the MCM layout. Thesefootprints will also serve as bondigdiagramsfor theMCM assembly.

A CHIPFOOTPRINTS 33

Figure24: BTH030footprint

Figure25: AD9042footprint

A CHIPFOOTPRINTS 34

Figure26: PPrAsicfootprint

A CHIPFOOTPRINTS 35

Figure27: DS92LV1021footprint

A CHIPFOOTPRINTS 36

Figure28: Phos4footprint

B MCM PIN AND NET NAME LISTINGS 37

B MCM Pin and Net NameListings

This appendixprovidespin andnetnamelistings for eachdie in theMCM layoutandthepin andnetnamesassignedtotheSMD connectors.

B MCM PIN AND NET NAME LISTINGS 38

Pin Number Pin Name APD Net Name1 1A DVCC2 1B DVCC3 2A DVCC4 2B DVCC5 3A AVDD6 3B AVDD7 4A AVDD8 4B AVDD9 5A AGND10 5B AGND11 6A AGND12 6B AGND13 7A EXTBCID 0 14 7B ADC1 IN15 8A DGND16 8B AGND17 9A SCL18 9B PHOS4ADD 2 19 10A JTAGTDI20 10B PHOS4ADD 3 21 11A JTAGTDO22 11B PHOS4ADD 4 23 12A DGND24 12B AGND25 13A EXTBCID 2 26 13B ADC3 IN27 14A DGND28 14B AGND29 15A ADC CLK30 15B JTAGTRST31 16A CLK PHOS432 16B SDA33 17A DGND34 17B AGND35 18A EXTBCID 3 36 18B ADC4 IN37 19A DGND38 19B AGND39 20A PHOS4ADD 5 40 20B JTAGTMS

Table6: Pinassignmentof partJ1(BTH03001FDA)

B MCM PIN AND NET NAME LISTINGS 39

Pin Number Pin Name APD Net Name41 21A GENOUT 1 42 21B PHOS4ERROR43 22A TEMPMEASURE44 22B JTAGTCK45 23A DGND46 23B AGND47 24A EXTBCID 1 48 24B ADC2 IN49 25A AGND50 25B AGND51 26A AGND52 26B AGND53 27A AVDD54 27B AVDD55 28A AVDD56 28B AVDD57 29A DVCC58 29B DVCC59 30A DVCC60 30B DVCC

Table7: Pinassignmentof partJ1(BTH03001FDA)

B MCM PIN AND NET NAME LISTINGS 40

Pin Number Pin Name APD Net Name1 1A DVCC2 1B DVCC3 2A DVCC4 2B DVCC5 3A DGND6 3B LVDS1 SYNC17 4A LVDS1 DO8 4B DGND9 5A LVDS1 DOBAR10 5B DGND11 6A DGND12 6B LVDS1 TCK R F13 7A GENOUT 3 14 7B L1ACCEPT15 8A AGND16 8B AGND17 9A LVDS1 DEN18 9B LVDS1 TCLK19 10A SEROUT120 10B SEROUT221 11A SERIN222 11B LVDS2 SYNC123 12A SERFRAME24 12B PPRASICCLK25 13A SERCLK26 13B SYNCPLAYBACK27 14A DGND28 14B SYNCREADOUT29 15A LVDS2 DO30 15B DGND31 16A LVDS2 DOBAR32 16B DGND33 17A DGND34 17B LVDS2 DEN35 18A LVDS3 SYNC136 18B LVDS2 DEN37 19A EVCNTRES38 19B SERIN139 20A BCCNTRES40 20B LVDS2 TCK R F

Table8: Pinassignmentof partJ2(BTH03001FDA)

B MCM PIN AND NET NAME LISTINGS 41

Pin Number Pin Name APD Net Name41 21A GENOUT 2 42 21B LVDS2 TCLK43 22A GENOUT 4 44 22B LVDS3 SYNC145 23A RESETBAR46 23B LVDS3 DEN47 24A AGND48 24B AGND49 25A DGND50 25B LVDS3 TCK R F51 26A LVDS3 DO52 26B GENOUT 3 53 27A LVDS3 DOBAR54 27B DGND55 28A DGND56 28B LVDS3 TCLK57 29A DVCC58 29B DVCC59 30A DVCC60 30B DVCC

Table9: Pinassignmentof partJ2(BTH03001FDA)

Pin Number Pin Name APD Net Name3 ENCODE CLK ADC14 ENCODEBAR DummyNet7 AIN DummyNet8 VOFFSET DummyNet9 VREF DummyNet10 C1 DummyNet25 D0 NC26 D1 NC27 D2 ADC1 0 28 D3 ADC1 1 29 D4 ADC1 2 30 D5 ADC1 3 31 D6 ADC1 4 32 D7 ADC1 5 33 D8 ADC1 6 42 D9 ADC1 7 43 D10 ADC1 8 44 D11BAR ADC1 9 11,12,15,16,19,20 AVDD1,2,36,37,40,41 DVCC5,6,13,14,17,18,21,22 AGND24,34,35,38,39 DGND

Table10: Pinassignmentof partU1 (AD9042)

B MCM PIN AND NET NAME LISTINGS 42

Pin Number Pin Name APD Net Name3 ENCODE CLK ADC24 ENCODEBAR DummyNet7 AIN DummyNet8 VOFFSET DummyNet9 VREF DummyNet10 C1 DummyNet25 D0 NC26 D1 NC27 D2 ADC2 0 28 D3 ADC2 1 29 D4 ADC2 2 30 D5 ADC2 3 31 D6 ADC2 4 32 D7 ADC2 5 33 D8 ADC2 6 42 D9 ADC2 7 43 D10 ADC2 8 44 D11BAR ADC2 9 11,12,15,16,19,20 AVDD1,2,36,37,40,41 DVCC5,6,13,14,17,18,21,22 AGND24,34,35,38,39 DGND

Table11: Pinassignmentof partU2 (AD9042)

Pin Number Pin Name APD Net Name3 ENCODE CLK ADC34 ENCODEBAR DummyNet7 AIN DummyNet8 VOFFSET DummyNet9 VREF DummyNet10 C1 DummyNet25 D0 NC26 D1 NC27 D2 ADC3 0 28 D3 ADC3 1 29 D4 ADC3 2 30 D5 ADC3 3 31 D6 ADC3 4 32 D7 ADC3 5 33 D8 ADC3 6 42 D9 ADC3 7 43 D10 ADC3 8 44 D11BAR ADC3 9 11,12,15,16,19,20 AVDD1,2,36,37,40,41 DVCC5,6,13,14,17,18,21,22 AGND24,34,35,38,39 DGND

Table12: Pinassignmentof partU3 (AD9042)

B MCM PIN AND NET NAME LISTINGS 43

Pin Number Pin Name APD Net Name3 ENCODE CLK ADC44 ENCODEBAR DummyNet7 AIN DummyNet8 VOFFSET DummyNet9 VREF DummyNet10 C1 DummyNet25 D0 NC26 D1 NC27 D2 ADC4 0 28 D3 ADC4 1 29 D4 ADC4 2 30 D5 ADC4 3 31 D6 ADC4 4 32 D7 ADC4 5 33 D8 ADC4 6 42 D9 ADC4 7 43 D10 ADC4 8 44 D11BAR ADC4 9 11,12,15,16,19,20 AVDD1,2,36,37,40,41 DVCC5,6,13,14,17,18,21,22 AGND24,34,35,38,39 DGND

Table13: Pinassignmentof partU4 (AD9042)

B MCM PIN AND NET NAME LISTINGS 44

Pin Number Pin Name APD Net Name3 ADCIN1 3 ADC1 3 4 ADCIN1 2 ADC1 2 5 ADCIN1 1 ADC1 1 6 ADCIN1 0 ADC1 0 7 ADCIN2 9 ADC2 9 8 ADCIN2 8 ADC2 8 9 ADCIN2 7 ADC2 7 10 ADCIN2 6 ADC2 6 11 ADCIN2 5 ADC2 5 12 ADCIN2 4 ADC2 4 13 ADCIN2 3 ADC2 3 14 ADCIN2 2 ADC2 2 15 ADCIN2 1 ADC2 1 16 ADCIN2 0 ADC2 0 17 ADCIN3 9 ADC3 9 18 ADCIN3 8 ADC3 8 19 ADCIN3 7 ADC3 7 20 ADCIN3 6 ADC3 6 21 ADCIN3 5 ADC3 5 22 ADCIN3 4 ADC3 4 23 ADCIN3 3 ADC3 3 24 ADCIN3 2 ADC3 2 25 ADCIN3 1 ADC3 1 26 ADCIN3 0 ADC3 0 27 ADCIN4 9 ADC4 9 28 ADCIN4 8 ADC4 8 29 ADCIN4 7 ADC4 7 30 ADCIN4 6 ADC4 6 35 ADCIN4 5 ADC4 5 36 ADCIN4 4 ADC4 4 37 ADCIN4 3 ADC4 3 38 ADCIN4 2 ADC4 2 39 ADCIN4 1 ADC4 1 40 ADCIN4 0 ADC4 0 41 GENOUT1 0 GENOUT1 0 42 GENOUT1 1 GENOUT1 1 43 GENOUT1 2 GENOUT1 2 44 GENOUT1 3 GENOUT1 3 45 GENOUT1 4 GENOUT1 4 46 PHOS4ERROR PHOS4ERROR1,32,33,47,63,64,81,82,97,98,114,129 DVCC2,31,34,48,62,65,79,80,96,99,113,128 DGND

Table14: Pinassignmentof partU5 (PPRASIC)

B MCM PIN AND NET NAME LISTINGS 45

Pin Number Pin Name APD Net Name49 PHOS4DETECT PHOS4DETECT50 GENOUT2 0 GENOUT2 0 51 GENOUT2 1 GENOUT 1 52 GENOUT2 2 GENOUT 2 53 GENOUT2 3 GENOUT 3 54 GENOUT2 4 GENOUT 4 55 TOJP 8 TOJP 8 56 TOJP 7 TOJP 7 57 TOJP 6 TOJP 6 58 TOJP 5 TOJP 5 59 TOJP 4 TOJP 4 60 TOJP 3 TOJP 3 61 TOJP 2 TOJP 2 66 TOJP 1 TOJP 1 67 TOJP 0 TOJP 0 68 TOJPPARITY TOJPPARITY69 TOCP2 7 TOCP2 7 70 TOCP2 6 TOCP2 6 71 TOCP2 5 TOCP2 5 72 TOCP2 4 TOCP2 4 73 TOCP2 3 TOCP2 3 74 TOCP2 2 TOCP2 2 75 TOCP2 1 TOCP2 1 76 TOCP2 0 TOCP2 0 77 TOCPBCMUXFLAG2 TOCPBCMUXFLAG278 TOCPPARITY2 TOCPPARITY283 TOCP1 7 TOCP1 7 84 TOCP1 6 TOCP1 6 85 TOCP1 5 TOCP1 5 86 TOCP1 4 TOCP1 4 87 TOCP1 3 TOCP1 3 88 TOCP1 2 TOCP1 2 89 TOCP1 1 TOCP1 1 90 TOCP1 0 TOCP1 0 91 TOCPBCMUXFLAG1 TOCPBCMUXFLAG192 TOCPPARITY1 TOCPPARITY193 CLK PPRASICCLK94 RESETBAR RESETBAR95 L1ACCEPT L1ACCEPT100 SEROUT2 SEROUT21,32,33,47,63,64,81,82,97,98,114,129 DVCC2,31,34,48,62,65,79,80,96,99,113,128 DGND

Table15: Pinassignmentof partU5 (PPRASIC)

B MCM PIN AND NET NAME LISTINGS 46

Pin Number Pin Name APD Net Name101 SEROUT1 SEROUT1102 SERIN2 SERIN2103 SERIN1 SERIN1104 SERFRAME SERFRAME105 SERCLK SERCLK106 BCCNTRES BCCNTRES107 EVCNTRES EVCNTRES108 SYNCPLAYBACK SYNCPLAYBACK109 SYNCREADOUT SYNCREADOUT110 JTAGTDO JTAGTDO111 JTAGTCK JTAGTCK112 JTAGTRST JTAGTRST115 JTAGTMS JTAGTMS116 JTAGTDI JTAGTDI117 TEMPMEASURE TEMPMEASURE118 EXTBCID 3   EXTBCID 3  119 EXTBCID 2   EXTBCID 2  120 EXTBCID 1   EXTBCID 1  121 EXTBCID 0   EXTBCID 0  122 ADCIN1 9   ADC1 9  123 ADCIN1 8   ADC1 8  124 ADCIN1 7   ADC1 7  125 ADCIN1 6   ADC1 6  126 ADCIN1 5   ADC1 5  127 ADCIN1 4   ADC1 4  1,32,33,47,63,64,81,82,97,98,114,129 DVCC2,31,34,48,62,65,79,80,96,99,113,128 DGND

Table16: Pinassignmentof partU5 (PPRASIC)

Pin Number Pin Name APD Net Name1 DO2 CLK ADC33 SDA SDA5 SCL SCL6 A5 PHOS4ADD 5  7 A4 PHOS4ADD 4  8 A3 PHOS4ADD 3  9 A2 PHOS4ADD 2  13 PHI2 PHOS4DETECT15 DO1 CLK ADC217 DO0 CLK ADC119 DI0 ADC CLK20 DI1 ADC CLK22 PHI1 CLK PHOS424 DI2 ADC CLK25 DI3 ADC CLK27 DO3 CLK ADC44,16,21,28 DVCC2,12,14,18,23,26 DGND

Table17: Pinassignmentof partU6 (PHOS4)

B MCM PIN AND NET NAME LISTINGS 47

Pin Number Pin Name APD Net Name1 SYNC1 LVDS1 SYNC12 SYNC2 GENOUT1¡ 2 ¢3 DIN0 TOCPPARITY14 DIN1 TOCPBCMUXFLAG15 DIN2 TOCP1¡ 0 ¢6 DIN3 TOCP1¡ 1 ¢7 DIN4 TOCP1¡ 2 ¢8 DIN5 TOCP1¡ 3 ¢9 DIN6 TOCP1¡ 4 ¢10 DIN7 TOCP1¡ 5 ¢11 DIN8 TOCP1¡ 6 ¢12 DIN9 TOCP1¡ 7 ¢13 TCLK R F LVDS1 TCK R F14 TCLK LVDS1 TCLK19 DEN LVDS1 DEN21 DOBAR LVDS1 DOBAR22 DO LVDS1 DO24 PWRDNBAR GENOUT1¡ 0 ¢18,20,23,25 AGND15,16 DGND17,26 AVCC27,28 DVCC

Table18: Pinassignmentof partU7 (DS92LV1021)

Pin Number Pin Name APD Net Name1 SYNC1 LVDS2 SYNC12 SYNC2 GENOUT1¡ 3 ¢3 DIN0 TOCPPARITY24 DIN1 TOCPBCMUXFLAG25 DIN2 TOCP2¡ 0 ¢6 DIN3 TOCP2¡ 1 ¢7 DIN4 TOCP2¡ 2 ¢8 DIN5 TOCP2¡ 3 ¢9 DIN6 TOCP2¡ 4 ¢10 DIN7 TOCP2¡ 5 ¢11 DIN8 TOCP2¡ 6 ¢12 DIN9 TOCP2¡ 7 ¢13 TCLK R F LVDS2 TCK R F14 TCLK LVDS2 TCLK19 DEN LVDS2 DEN21 DOBAR LVDS2 DOBAR22 DO LVDS2 DO24 PWRDNBAR GENOUT1¡ 1 ¢18,20,23,25 AGND15,16 DGND17,26 AVCC27,28 DVCC

Table19: Pinassignmentof partU8 (DS92LV1021)

REFERENCES 48

Pin Number Pin Name APD Net Name1 SYNC1 LVDS3 SYNC12 SYNC2 GENOUT1£ 4 ¤3 DIN0 TOJPPARITY4 DIN1 TOJP£ 0 ¤5 DIN2 TOJP£ 1 ¤6 DIN3 TOJP£ 2 ¤7 DIN4 TOJP£ 3 ¤8 DIN5 TOJP£ 4 ¤9 DIN6 TOJP£ 5 ¤10 DIN7 TOJP£ 6 ¤11 DIN8 TOJP£ 7 ¤12 DIN9 TOJP£ 8 ¤13 TCLK R F LVDS3 TCK R F14 TCLK LVDS3 TCLK19 DEN LVDS3 DEN21 DOBAR LVDS3 DOBAR22 DO LVDS3 DO24 PWRDNBAR GENOUT2£ 0 ¤18,20,23,25 AGND15,16 DGND17,26 AVCC27,28 DVCC

Table20: Pinassignmentof partU9 (DS92LV1021)

References

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[Mah99] Mahboubi,K.A descriptionof monitoringratesin hardwareaswell as”r aw” transverseenergyspectraIHEP, Heidelberg,Germany 1999http://wwwasic.kip.uni-heidelberg.de/atlas/L1/DISCUSS/ppa his rate.pdf

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[Pfe99/1] Pfeiffer, U.Bunch-CrossingIdentificationfor saturatedcalorimetersignalsATLAS Trigger/DAQ note,ATL-DAQ-99-009,Universityof Heidelberg,Germany 17May 1999http://wwwasic.ihep.uni-heidelberg.de/atlas/publications.html

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[Phos4] Phos4PHOS4- 4 ChanneldelaygenerationASICwith 1 nsresolutionDatasheet,CERN— Microelectronicsgrouphttp://pcvlsi5.cern.ch/MicDig/Thomas/Delaychip.pdf

[PPrAsic] Pre-ProcessorASIC (PPrAsic)Specificationof thePre-ProcessorAsicPreliminaryDesignReview, UniversiẗatHeidelberg,Germany 24.Juli 1999http://wwwasic.ihep.uni-heidelberg.de/atlas/docs/chips.html

[ROD] ReadoutDriverDRAFTSpecificationof thePre-ProcessorRead-OutDriver Prototypefor theATLASLevel-1CalorimeterTriggerTheATLAS Heidelberg Group,15thFebruary2001http://wwwasic.kip.uni-heidelberg.de/atlas/docs/modules.html

[Sam] SAMTECInc.http://www.samtec.com

[Sch99] Schumacher, C.DesignGuidefor thePPrASICIHEP, Heidelberg,Germany 1999http://wwwasic.kip.uni-heidelberg.de/atlas/L1/DISCUSS/designguide.ps

[Sig97] DF/SigNoiseDF/SigNoise- UserGuideCadenceProductVersion12.0,Openbookdocumentation,February1997http://www.cadence.com

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[Ste00] Stelzer, O.CompactDigitizing andSerializingfor theATLASLevel-1CalorimeterTriggerDiplomaThesis,Institut für HochenergiephysikderUniversitaetHeidelberg,Germany July2000http://wwwasic.kip.uni-heidelberg.de/atlas/docs.html

[TDR98] ATLAS Level-1TriggerGroupATLASFirst-LevelTrigger TechnicalDesignReportATLAS TDR-12,CERN/LHCC/98-14,CERN,Geniva24June1998http://atlasinfo.cern.ch/Atlas/GROUPS/DAQTRIG/TDR/tdr.html

[The97] DF/ThermaxDF/ThermaxExpertfor PackageDesign- UserGuideCadenceProductVersion12.0,Openbookdocumentation,February1997http://www.cadence.com

[Wue] WürthElektronikhttp://www.wuerth-elektronik.de