speech based wheel chair control final project report

INDEX

1. ABSTRACT 1

2. INTRODUCTION 2

3. BLOCK DIAGRAM 3

4. THE SYSTEM PRINCIPLE AND WORKING 4

5. CONSTRUCTION 21

6. TESTING, ADJUSTMENTS AND FAULT FINDING 23

7. COMPONENTS LIST 24

8. SOURCE CODE 25

9. ADVANTAGES 72

10.APPLICATIONS 73

11.FUTURE ENHANCMENT 74

12.CONCLUSION 75

13.BIBLIOGRAPHY 76

SPEECH BASED WHEEL CHAIR CONTROL

ABSTRACT

The main aim of the project is to design a user-friendly speech system such that any

handicap person can sit and operate from the chair.

In this project we are using the speech-processing unit along with PC. The

speech processor initially has to be trained with the known commands of the user. When the

same are repeated these commands are compared to the stored one and accordingly generates

the signal. These signals are fed to the Parallel port and to the Micro controller. The micro

controller is connected to the stepper motor. When the user gives a specific command from

his wheel chair the PC and the Micro controller accordingly drives the stepper motor either in

clockwise or anticlockwise direction. Thus controlling the chair on which the person is

sitting.

This technique is very interactive and is very easy to operate by any handicap

person.

1


INTRODUCTION

Several researchers have considered using human voice to control powered wheelchairs,

Naturally, a wheelchair voice control system should operate reliably for a large number of

users, reduce the physical requirements; and should assist a user in maintaining well the chair

position. In wheel chair control, compared with other means for human-machine interface

such as head movement, verbal communication remains the most natural .

In this project, the essential parts of a voice interface system for wheelchair control will

be presented along with the stepper motor control unit. This project is aimed at providing

services to handicap persons. The circuit employs the 16F873PIC micro controller and the

parallel port interface card.

A personal computer is utilized for speech processing. The Microsoft Speech SDK

software recognize and synthesis the speech commands. The code written in java language

detect the processed speech command and accordingly create the required control signal and

sends to the parallel port interface circuit The parallel port interface circuit sends the required

signals to the micro controller circuit. A stepper motor is used to control the wheel chair

rotation.

In practical implementation all the units are in cooperated to a single unit and are placed

below the chair with its power supply. Also it can control the chair motions But in the demo

only the chair rotation is implemented

2


BLOCK DIAGRAM

Microphone

THE SYSTEM PRINCIPLE AND WORKING

The system operates in two parts .The software part and the hardware part.

The software part process the sound commands given by the user and generates the required

signals. The hardware part controls the stepper motor accordingly. The block diagram is

given below.

3

PC Micro controller Unit

Relays

Stepper Motor

Parallel port Interface

8255


SOFTWARE PART:

The software part mainly consists of a java program and a

Parallel port interface C program. A microphone connected to the PC receives

the sound commands from the user and Microsoft’s Speech SDK recognize and synthesis the

command.

A token, sometimes called a terminal symbol, is the part of a grammar that

defines what a user may speak. Most often, a token is equivalent to a word. A token is a

reference to an entry in a recognizer's vocabulary The recognizer's vocabulary defines the

pronunciation of the token. With the pronunciation, the recognizer is able to listen for that

token. The Java Speech Grammar Format allows multi-lingual grammars, that is, grammars

that include tokens from more than one language. However, most recognizers operate mono-

lingual so a typical grammar will contain only one language. It is the responsibility of the

application that loads a grammar into a recognizer to ensure that it has appropriate language

support. The grammar format used in the project is listed below.

#JSGF V1.0;

grammar testGram;

public <test1> = WheelChair | STOP | START | BACK |EXIT;

4


HARDWARE PART:

The hardware mainly consist of the parallel port interface

card, the micro controller circuit ,the driver circuit and the stepper motor .

PARALLEL PORT INTERFACE CARD

LPT1 INTERFACE WITH 8255 PPI

5


HARDWARE REQUIREMENTS:

Parallel port interface card.

5V Regulated power supply.

PC with a LPT1 port.

26 wire Flexible Ribbon Cable (FRC).

Printer sharer cable.

Test card LED module. (For test purpose only).

SOFTWARE REQUIREMENTS:

Turbo C.

Device Driver – P8255.DRV version 1.0.

Interface Card Tester – ICT.EXE version 1.0. (For test purpose only).

.

6


SPECIFICATIONS OF INTERFACE CARD

GENERAL

Interface Component : 8255 PPI.

Number of Ports: Three.

Port Resolution: 8-Bit.

Mode – Input: Programmed (Software Controlled).

Mode – Output: Programmed (Software Controlled).

Maximum Input Resolution: 24-Bit.

Maximum Output Resolution: 24-Bit.

Input/Output Signal level: TTL.

Signal Compatibility: CMOS (Operating on 5.00V).

OPERATING VOLTAGE

Nominal operating Voltage: 5.00 V

Maximum operating Voltage: 5.25 V

Minimum operating Voltage: 4.75 V

Operating Temperature

Minimum operating Temperature: -4°C.

Maximum operating Temperature: 80°C.

DIMENSION

Length X Breadth X Height: 2.65” X 2.65” X 0.4”

7


A parallel/LPT1 port is basically used for operation of a printer. Other than a

printer, a parallel port can also be used for simple interfacing applications. A parallel port has

12 output lines and 5 input lines, some of which are inverted, hence parallel port, cannot be

used as it is for other demanding applications other than a printer.

Hence the need for an interface card connected to parallel port which can

handle ample number of inputs and outputs .The present design of interface card connected to

parallel port can handle 24 bit input or output, which is sufficient for most interfacing

applications. The heart of this interface card is Programmable Peripheral Interface PPI chip

8255. Intel originally developed 8255 PPI. This interface card has three 8-bit ports, which can

be individually programmed as input or output. Hence we can program the ports to provide

24 bit input or 24-bit output or combination of both input and output .A device driver

software is used as a translator between parallel port and 8255 PPI. This device driver

P8255.DRV should be included in the source code, the details of which are given in software

section. The device driver bridges the incompatibilities of the signals between the parallel

port and 8255 PPI. The signal levels of interface card is TTL compatible, hence it can be used

both for TTL as well as CMOS interfacing. The outputs of interface card are capable of

sinking 2mA of current. Hence suitable buffering should be provided for high current sinking

applications.

8


9


PARALLEL PORT BASICS

Port Assignments

Each parallel port consists of three port addresses; data, status and control port. These

addresses are in sequential order. That is, if the data port is at address 0x0378, the

corresponding status port is at 0x0379 and the control port is at 0x037a.

The following is typical.

Parallel Port Data Port Status Control

LPT1 0x03bc 0x03bd 0x03be

LPT2 0x0378 0x0379 0x037a

LPT3 0x0278 0x0279 0x027a

To definitively identify the assignments for a particular machine, use the DOS debug program

to display memory locations 0040:0008. For example:

>Debug

-D 0040:0008 L8

0040:0008 78 03 78 02 00 00 00 00

Note in the example that LPT1 is at 0x0378, LPT2 at 0x0278 and LPT3 and LPT4 are not

assigned.

Thus, for this hypothetical machine;

Parallel Port Data Port Status Control

LPT1 0x0378 0x0379 0x037a

LPT2 0x0278 0x0279 0x027a

LPT3 NONE

LPT4 NONE

An alternate technique is to run Microsoft Diagnostics (MSD.EXE) and review the LPT

assignments.

10


Outputs

Please refer to the figures titled Figure #1 - Pin Assignments and Figure #2 - Port

Assignments. These two figures illustrate the pin assignments on the 25 pin connector and the

bit assignments on the three ports.

Fig 1. Pin Assignments

Fig 2. Port Assignments

Note that there are eight outputs on the Data Port (Data 7(msb) - Data 0) and four additional

outputs on the low nibble of the Control Port. /SELECT_IN, INIT, /AUTO FEED and

/STROBE. [Note that with /SELECT_IN, the "in" refers to the printer. For normal printer

operation, the PC exerts a logic zero to indicate to the printer it is selected. The original

function of INIT was to initialize the printer, AUTO FEED to advance the paper. In normal

printing, STROBE is high. The character to be printed is output on the Data Port and

STROBE is momentarily brought low.]

11


All outputs on the Data Port are true logic. That is, writing a logic one to a

bit causes the corresponding output to go high. However, the /SELECT_IN, /AUTOFEED

and /STROBE outputs on the Control Port have inverted logic. That is, outputting a logic one

to a bit causes a logic zero on the corresponding output. This adds some complexity in using

the printer port, but the fix is to simply invert those bits using the exclusive OR function prior

to outputting.

[One might ask why the designers of the printer port designed the port in

this manner. Assume you have a printer with no cable attached. An open usually is read as

logic one. Thus, if logic one on the SELECT_IN, AUTOFEED and STROBE leads meant to

take the appropriate action, an unconnected printer would assume it was selected, go into the

auto feed mode and assume there was data on the outputs associated with the Data Port. The

printer would be going crazy when in fact it wasn't even connected. Thus, the designers used

inverted logic. A zero forces the appropriate action.]

In summary, the printer port affords a very simple technique for

interfacing with external circuitry. Twelve output bits are available, eight on the Data Port

and four on the lower nibble of the Control Port. Inversions are necessary on three of the bits

on the Control Port. Five inputs are available on the Status Port. One software inversion is

necessary when reading these bits.

12


WORKING OF INTERFACE CARD

Please refer to the schematic diagram of interface card and timing diagram of 8255 PPI

(WRITE & READ cycles).The operation of interface card can be broadly divided into

WRITE and READ operation. These operations are explained in detail below.

The interface card uses four ICs.

IC-1 8255A TTL Programmable Peripheral Interface.

IC-2 4503B CMOS Hex Tristate Buffer.

IC-3 4503B CMOS Hex Tristate Buffer.

IC-4 74LS157 TTL Four Bit Data Selector.

13


WRITE OPERATION

The WRITE operation of interface card deals with outputting a desired byte to

a desired port.Referring to the schematic diagram of interface card, we see that the data port

of parallel port is connected to the input of the CMOS buffer. The control port of parallel port

is connected directly to the WR, RD, A0, and A1 of 8255 PPI. A0 and A1 help select the

desired port, i.e. Port A, Port b or port C. The table below shows port selection by using A0

and A1.

A1 A0 Port Selected

0 0 Port A

0 1 Port B

1 0 Port C

1 1 Control Word Register

The byte to be outputted is output on the data port of parallel port

(D0-D7). For WRITE operation WR is made low and RD is made high. Similarly A0 and A1

are selected for desired port. Once WR, RD, A0, A1 are determined, they are outputted to the

control port of parallel port, which is directly connected to 8255 PPI. As soon is WR is made

low, the CMOS buffers get active. The ENABLE pins of both buffers are connected to WR of

8255 PPI. Now the byte that was outputted on data port of parallel port gets loaded on to the

data bus of 8255 PPI. To complete the WRITE operation WR is made high. Thus the data on

data bus of 8255 PPI gets transferred to the desired port, the address of which is determined

by A0 and A1.

14


READ OPERATION

The READ operation of interface card deals with reading or inputting a byte from a

desired port of 8255 PPI. Due to the limited number of input lines i.e. the status port of

parallel port; the READ operation is divided into two steps.

The parallel port has five input lines, the interface card uses four input lines of status

port of parallel port for performing a READ operation. For reading a byte i.e. 8-bits, it is

divided into two 4-bits. First four LSB is read and then four MSB is read into the status port

of parallel port. Later these two groups of four bits each are processed to form a complete

byte. Referring to the schematic diagram of interface card we see that the data bus of 8255

PPI is connected to input of 4-bit data selector IC-4 74LS157. D0-D3 constitutes the lower

four bits and D4-D7 constitutes the upper four bits. The data selector pin of 74LS157 is

connected to D0 bit of data port of parallel port. Suppose if we want to read a byte from a

desired port, then the following procedure has to be followed.To read the lower four bits (D0-

D3) of 8255 PPI, bit D0 of data port of parallel port is made low, now the output of data

selector will be lower four bits. For READ operation RD is made low and WR is made high.

The desired port is selected by using A0 and A1. Once WR, RD, A0 and A1 are determined,

they are outputted on the control port of parallel port. To complete the read operation RD is

made high. This loads the inputted byte on the data bus of 8255 PPI. Lower four bits appear

at the output of data selector. The output of data selector is connected to the status port of

parallel port. After this the lower four bits are inputted through the status port of parallel port

and stored in a variable for future processing.To read the higher four bits (D4-D7) of 8255

PPI, bit D0 of data port of parallel port is made high, now the output of data selector will be

higher four bits. For READ operation RD is made low and WR is made high. The desired

port is selected by using A0 and A1.

15


Once WR, RD, A0 and A1 are determined, they are outputted on the control port of

parallel port.To complete the read operation RD is made high. This loads the inputted byte on

the data bus of 8255 PPI. Higher four bits appear at the output of data selector. The output of

data selector is connected to the status port of parallel port. After this the higher four bits are

inputted through the status port of parallel port and stored in another variable for future

processing. Once we have both lower four bits and higher four bits, processing of variables

are done to yield the inputted byte (8-bits).

16


Device Driver

P8255.DRV

17

DEVICE DRIVER FOR PARALLEL PORT INTERFACE CARD Version – 1.0 SEPT2001. Developed by COOLSID @ BCS, Bangalore – India. Email - <[email protected]>

HELP! USAGE: This device driver <P8255.DRV> must be copied to the directory Which contains the 'HEADER FILES'. This driver should be included in the C source code at the beginning

#Include<stdio.h> #Include<dos.h> . . . #Include<p8255.drv>

PORT DESIGNATIONS: Port A - 0 Port B - 1 Port C - 2 Control word Register -3

INPUT : in (port designation);

Example: in (1); Inputs a byte from Port B of 8255.

OUTPUT: out (port designation, byte (hex format));

Example: out (2,0x01) Outputs a byte (01) to Port C of 8255.


16F873PIC MICRO CONTROLLER CIRCUIT

The circuit mainly consists of 16F873PIC IC , crystal oscillator of

10 MHz,, capacitor, two resistors , LED and a toggle switch .The crystal oscillator gives the

required clocking signals for the micro controller IC .The capacitor is used to bypass the

possible ac signals to ground, preventing the damage that may cause the PIC IC. A 100ohm

resistor is used to connect the LED .And a 1kohm resistor is used to give the required drop

for the pin (pin no:1) {Master clear (reset) input or programming voltage input or high

voltage test mode control. This pin is an active low reset to the device.} via the toggle switch.

The PA0, PA1, PA2 & PA3 (4,3,2&1) pins of 8255 IC are connected

to the RC0, RC1,RC21& RC3 (11,12,13& 14) pins of IC16F873 respectively. PA0-PA3 pins

are the portA Bits.RC0-RC3 pins are to PORTC which is a bi-directional I/O port.RC0 can

also be the Timer1 oscillator output or Timer1 clock input.RC1 can also be the Timer1

oscillator input or Capture2 input/Compare2 output/PWM2 output.RC2 can also be the

Capture1 input/Compare1 output/PWM1output.RC3 can also be the synchronous serial clock

input/output forboth SPI and I2C modes.

The data memory is partitioned into multiple banks which contain the General Purpose

Registers and the Special Function Registers. Bits RP1(STATUS<6>) and RP0

(STATUS<5>) are the bank select bits.Each bank extends up to 7Fh (128 bytes). The lower

locations of each bank are reserved for the Special Function Registers. Above the Special

Function Registers are General Purpose Registers, implemented as static RAM. All

implemented banks contain Special Function Registers. Some “high use” Special Function

Registers from one bank may be mirrored in another bank for code reduction and quicker

access. The circuit diagram is given below.

18


19

CIR

CU

IT D

IAG

RA

M O

F S

PE

EC

H B

AS

ED

WH

EE

LC

HA

IR C

ON

TR

OL


RELAY DRIVER CIRCUIT

The UTC ULN2003 is used as the driver for the stepper motor and it is a high-voltage,

high-current darlighton drivers comprised of seven NPN darlington pairs. The driver

strengthen the signals from the PIC16F873 IC.

STEPPER MOTOR

The Step Motor is an electromagnetic device that converts digital pulses into mechanical

shaft rotation. Advantages of step motors are low cost, high reliability, high torque at low

speeds and a simple, rugged construction that operates in almost any environment. The main

disadvantages in using a step motor is the resonance effect often exhibited at low speeds and

decreasing torque with increasing speed. Depending on the type of relays to be activated and

the particular order, stepper motor accordingly moves in either clock wise or anti-clock wise

direction.

20


CONSTRUCTION

The software part is done on a personal computer with Windows 2000

profession operating system. In the PC install the following softwares.

1. j2sdk-1_4_1_01-windows-i586

2. speechsdk51

3. Jcreater

Then write the program code in java language, compile it. Write the required gram

file and compile. Write the C language code for the Parallel port interface card. Create the

required DLL file. Then copy the file user port.sys and run the user port.exe file.

The hardware can be developed on a PCB, layout are shown in fig .1 All the

circuits are housed in metal box with holes opening for external connections.. Low profile

socket may be used for ICs for easy replacement and faultfinding. Assembly of the

component may be done in the following sequence: IC sockets, resistors, capacitors diodes,

transistors, LEDs etc observing correct polarity of components. The 16F873PIC micro

controller is programmed using a PIC programmer. Before putting the ICs in their respective

sockets, it is better to measure the resistance between their pins and ground point using

Multimeter. It must not be very low. Observe PCB for dry joints; solder splashes and bridges

between tracks. After that connect the power supply.

21


SINGLE ENDED PCB FOR PIC16F873 IC

22


TESTING,ADJUSTMENT AND FAULT FINDING

Check the ICs

Connect the Parallel port with the computer.

The LED in the Parallel port interface circuit glows indicating the connection with the

computer.

Connect the Dc power supply.(+12v,+5v)

The LED in the Micro controller circuit glows.

Test the Hardware part by using the C language code given.

If the stepper motor works correctly, then the hardware part is ready for operation

Then in Windows 2000 profession run the user port.exe file and start the same.

Run the command prompt (cmd)

Type the path to setclasspath.bat file

Then run the Java SpeechControl.

The speech synthesizer runs and give the password through the micro phone

(“WHEELCHAIR”)

Then give the required commands for the motor rotation.

23


COMPONENTS LIST

Software

j2sdk-1_4_1_01-windows-i586

speechsdk51

Jcreater

User port

Windows 2000 profession operating system.

Hardware

ICs:

16F873PIC

8255A programmable peripheral interface

4503B Hex Non-Inverting 3-State Buffer (2 no:)

74LS157 Quad 2-Input Multiplexer

ULN2003 Relay driver

RESISTORS

CAPACITORS

10MHz CRYSTAL OSCILLATOR

DIODES

LEDS

POWER SUPPLY 5V &12V

24


SOURCE CODE

1 . JAVA PROGRAM FOR SPEECH SYNTHESIS

//import speech.*;import speech.Synthesis;import javax.speech.*;import javax.speech.recognition.*;import java.io.FileReader;import java.util.Locale;

public class SpeechControl extends ResultAdapter { /* The adapter which receives the events for Recognizer*/

static Recognizer recognizer; String gst; static Synthesis synthesis; static boolean flag = false; nativeSpeech nspeech;

SpeechControl(){ nspeech = new nativeSpeech(); nspeech.Initialize();

} public void resultAccepted(ResultEvent re)

{

try { Result res = (Result)(re.getSource());

/* A token contained by a Result. Representing something heard by a recognezer for the

result of the grammar rule.For any result the best guessed finalize tokens are obtained from

getBestTokens().token ranges must be in the range of zero to length-1. if it is zero an

exception i thrown.*/

25


ResultToken toke = res.getBestToken(0);

//This will return the corresponding text to the token number

gst = toke.getSpokenText(); System.out.println(" The token is "+gst + " ");

if(gst.equals("WheelChair")) {

synthesis.speak("You are a valid user. Plz start giving the commands."); flag = true;

gst=""; System.out.println(" Valid User.");

}if(flag){

if(gst.equals("STOP")) {

synthesis.speak("Motor Stopped.");System.out.println("MOTOR STOPPED.");nspeech.Stop();

}

if(gst.equals("BACK")) { synthesis.speak("Motor running in Left Direction"); System.out.println("See you later!");

nspeech.Left(); }

else if(gst.equals("START")) {

synthesis.speak("Motor running in Right Direction");System.out.println("See U Later");nspeech.Right();

} else if(gst.equals("EXIT"))

{System.out.println("Exits.");System.out.println("See you later!");

recognizer.deallocate();

System.exit(0);

}

26


}

}catch(Exception ee) { System.out.println("Exception " + ee); }

}

public static void main(String as[]){

new SpeechControl();

try {

/* The recognizer provides acces to speech controller capabilities.The

Recognize will extend the javax.speech.engine so inherits all the properties of the speech

engine.for example grammar handling etc.*/

/* A Recognizer is created by making a call to the central class. The

central class is the initial class to all the speech input and outptut capabilities.Central provides

the abilities to locate create and select the speech recognizers.createRecognizer is

the method which is used to create speech engines.it accepts a single parameter that will that

defines the required properties for the engine created.the parameter may be Engine mode desc

which is a subclass Locale is java.util.Locale class object.which is used to select language

supported by the engine.*/

recognizer = Central.createRecognizer(new EngineModeDesc(Locale.ENGLISH)); /* Allocate the resources required by the engine andput that in ALLOCATED

STATE*/

recognizer.allocate();

synthesis=new Synthesis(); synthesis.speak("the creators of this unique voice recognition wheel chair

are Vinayaka Sripal & numan"); synthesis.speak ("Your PASSWORD PLease");

// recognizer.allocate(); FileReader grammar =new FileReader("F:/Speech Based Wheel Chair

Control/testGram.gram");

/* loadJSGF will load the grammar rule from java speech grammar

format. from the URL format specified. */

27


RuleGrammar rg = recognizer.loadJSGF(grammar); rg.setEnabled(true);

recognizer.addResultListener(new SpeechControl()); System.out.println("Ready for Input");

/*Commit changes to all loaded grammar and all changes of grammar

since from last commit.*/

recognizer.commitChanges();

/* This will requests the speech focus from the underlying recognizer engine.

and also it processes the focus gained and focus released events.*/

recognizer.requestFocus();

recognizer.resume();

System.out.print(" Here comes the result");

}catch (Exception e) { System.out.println("Exception " + e); }

}}

class nativeSpeech{ public native void Initialize(); public native void Stop(); public native void Left(); public native void Right();

static{

System.loadLibrary("SpeechDll");}

}

28


2. Source code in C language for parallel port interface card

#include "dos.h"#include "conio.h"

int pport;

//extern "C" int _delay(int);void out(int p,int d)//int p,d;{int prt,tem;//int far *bpa=0x408; /* base port addr. */

//pport=*bpa;pport=0x378;//pport=0x408;

switch(p){ case 0: prt=0x09; /* port A (wr_addr.)- 0x09 */

break; case 1: prt=0x0d; /* port B (wr_addr.)- 0x0d */

break; case 2: prt=0x01; /* port C (wr_addr.)- 0x01 */

break; case 3: prt=0x05; /* port CWR (wr_addr.)- 0x05 */

break; default:break; }tem=prt&0x0c;//outp(pport,d);_outp(pport,d);_outp(pport+2,tem);Sleep(0);_outp(pport+2,prt);_outp(pport+2,tem);_outp(pport+2,0x08);}

29


int in(int p)//int p;{int prt,lb,hb,d;

//int far *bpa=0x408; /* base port addr. *///int *bpa=0x408;//pport=*bpa;pport=0x378;

switch(p){ case 0: prt=0x0a; /* port A (rd_addr.)- 0x0a */

break; case 1: prt=0x0e; /* port B (rd_addr.)- 0x0e */

break; case 2: prt=0x02; /* port C (rd_addr.)- 0x02 */

break; default:break; }

_outp(pport,0x00); _outp(pport+2,prt); lb=_inp(pport+1);

_outp(pport,0x01); hb=_inp(pport+1);

_outp(pport+2,0x08);

lb=((lb&0xf0)^0x80)/0x10; hb=(hb&0xf0)^0x80;

d=(lb+hb);

return(d);

}

30


3.PIC16F873 Micro controller program

;RECEIVER PROGRAM LIST P=16F873

#INCLUDE<P16F873.INC>

;REG1 EQU 0X20 ;Registers for delay;REG2 EQU 0X21;REG3 EQU 0X22TEMP EQU 0X23COUNT EQU 0X24COUNT1 EQU 0X25COUNTER EQU 0X26TEMP1 EQU 0X27TEMP2 EQU 0X28

ORG 0X00

BSF STATUS,RP0 ;Bank1CLRF TRISB ;Configure PortB as output PortsMOVLW 01FH ;Configure PortC as Input PortMOVWF TRISC;BCF TRISB,5

BCF STATUS,RP0 CLRF PORTB

WORK CALL TEST

MOVLW 01H ;If Switch '1' is pressed XORWF TEMPBTFSC STATUS,ZGOTO ROTATE ;If key=1 then the motor starts rotating

MOVLW 02H ;If Switch '2' is pressed XORWF TEMP1

31


BTFSC STATUS,ZGOTO STOP ;If key=1 then the motor stops rotating

MOVLW 03H ;If Switch '3' is pressed XORWF TEMP2BTFSC STATUS,ZGOTO REVERSE ;If key=3 then the motor starts rotating in reverse

direction

GOTO WORK;------------------------------------------------------------------------------------------------ROTATE

MOVLW 32HMOVWF COUNTER

ROTATE1MOVLW 01HMOVWF PORTBCALL TEST1MOVLW 02HMOVWF PORTBCALL TEST1MOVLW 04HMOVWF PORTBCALL TEST1MOVLW 08HMOVWF PORTBCALL TEST1DECFSZ COUNTER,1GOTO ROTATE1GOTO WORK

;-----------------------------------------------------------------------------------------------STOP

CLRF PORTBCALL TEST1CALL SSDELAYGOTO WORK

;-----------------------------------------------------------------------------------------------REVERSE

MOVLW 32HMOVWF COUNTER

REVERSE1

32


MOVLW 08HMOVWF PORTBCALL TEST1MOVLW 04HMOVWF PORTBCALL TEST1MOVLW 02HMOVWF PORTBCALL TEST1MOVLW 01HMOVWF PORTBCALL TEST1DECFSZ COUNTER,1GOTO REVERSE1GOTO WORK

;--------------------------------------------------------------------------------------------------TEST

MOVFPORTC,0ANDLW 0FHMOVWF TEMPMOVWF TEMP1MOVWF TEMP2RETURN

;---------------------------------------------------------------------------------------------------

TEST1CALL SSDELAY ;Checks for any signal from DTMF RxRETURN

;----------------------------------------------------------------------------------------------------

SSDELAY MOVLW 00H ;;00HThis Delay Is Short Delay with l5ms MOVWF COUNT1 SSDLOOP MOVLW 00AH;0A

MOVWF COUNTSSDLOOP1 DECFSZ COUNT,1

GOTO SSDLOOP1 DECFSZ COUNT1,1 GOTO SSDLOOP

RETURNEND

33


4.Program in C for testing Hardware

#include<stdio.h>#include<conio.h>#include<p8255.drv>#include<dos.h>

void main()

{ int i; clrscr(); out(3,0x80);printf(“ENTER YOUR CHOICE\n”);printf(“ENTER 1-MOTOR STARTS ROTATING\n”);printf(“ENTER 1-MOTOR STOPS ROTATING\n”);printf(“ENTER 1-MOTOR STARTS IN REVERSE DIRECTION\n”);

up: scanf(%D”,&I);

switch(i) {case 1: out(0,0x01); break;

case 2: out(0,0x02); break;case 3; out(0,0x03); break;case 4; exit();default: break;}goto up;

}

34


COMPONENTS DISCRIPTIONS

35


PIC16F87X

28-pin 8-Bit CMOS FLASH Microcontrollers

Microcontroller Core Features :

• High-performance RISC CPU

• Only 35 single word instructions to learn

• All single cycle instructions except for program branches which are two cycle

• Operating speed: DC - 20 MHz clock inputDC - 200 ns instruction cycle

• Up to 8K x 14 words of FLASH Program Memory, Up to 368 x 8 bytes of Data Memory

(RAM) Up to 256 x 8 bytes of EEPROM data memory

• Pinout compatible to the PIC16C73B/74B/76/77

• Interrupt capability (up to 14 sources)

• Eight level deep hardware stack

• Direct, indirect and relative addressing modes

• Power-on Reset (POR)

• Power-up Timer (PWRT) andOscillator Start-up Timer (OST)

• Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation

• Programmable code-protection

36


• Power saving SLEEP mode

• Selectable oscillator options

• Low-power, high-speed CMOS FLASH/EEPROM technology

• Fully static design

• In-Circuit Serial Programming(ICSP)via two pins

• Single 5V In-Circuit Serial Programming capability

• In-Circuit Debugging via two pins

• Processor read/write access to program memory

• Wide operating voltage range: 2.0V to 5.5V

• High Sink/Source Current: 25 mA

• Commercial and Industrial temperature ranges

• Low-power consumption:

< 2 mA typical @ 5V, 4 MHz

20 A typical @ 3V, 32 kHz

< 1 A typical standby current

37


Peripheral Features:

• Timer0: 8-bit timer/counter with 8-bit prescaler

• Timer1: 16-bit timer/counter with prescaler, can be incremented during sleep via external

crystal/clock

• Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler

• Two Capture, Compare, PWM modules

- Capture is 16-bit, max. resolution is 12.5 ns

- Compare is 16-bit, max. resolution is 200 ns

- PWM max. resolution is 10-bit

• 10-bit multi-channel Analog-to-Digital converter

• Synchronous Serial Port (SSP) with SPIä (Master Mode) and I2Cä (Master/Slave)

• Universal Synchronous Asynchronous Receiver Transmitter (USART/SCI) with 9-bit

address detection

• Parallel Slave Port (PSP) 8-bits wide, with external RD, WR and CS controls (40/44-pin

only)

• Brown-out detection circuitry for Brown-out Reset (BOR)

38


Pin Diagram

39


PIC16F873 AND PIC16F876 BLOCK DIAGRAM

PIC16F873 PINOUT DESCRIPTION

40


I/O PORTS

41


Some pins for these I/O ports are multiplexed with an alternate function for the

peripheral features on the device. In general, when a peripheral is enabled, that pin may not

be used as a general purpose I/O pin.

PORTC and the TRISC Register

PORTC is an 8-bit wide, bi-directional port. The corresponding data direction

register is TRISC. Setting a TRISC bit (=1) will make the corresponding PORTC pin an input

(i.e., put the corresponding output driver in a hi-impedance mode). Clearing a TRISC bit (=0)

will make the corresponding PORTC pin an output (i.e., put the contents of the output latch

on the selected pin). PORTC is multiplexed with several peripheral functions (Table 3-5).

PORTC pins have Schmitt Trigger input buffers. When the I2C module is enabled, the

PORTC (3:4) pins can be configured with normal I2C levels or with SMBUS levels by using

the CKE bit (SSPSTAT <6>). When enabling peripheral functions, care should be taken in

defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a

pin an output, while other peripherals override the TRIS bit to make a pin an input. Since the

TRIS bit override is in effect while the peripheral is enabled, read-modify write instructions

(BSF, BCF, XORWF) with TRISC as destination should be avoided. The user should refer to

the corresponding peripheral section for the correct TRIS bit settings.

42


MEMORY ORGANIZATION

There are three memory blocks in each of these PIC micro MCUs. The

Program Memory and Data Memory have separate buses so that concurrent access can occur

and is detailed in this section. The PIC16F87X devices have a 13-bit program counter capable

of addressing an 8K x 14 program memory space. The PIC16F877/876 devices have 8K x 14

words of FLASH program memory and the PIC16F873/ 874 devices have 4K x 14.

Accessing a location above the physically implemented address will cause a wraparound. The

reset vector is at 0000h and the interrupt vector is at 0004h

PIC16F874/873 PROGRAM

MEMORY MAP AND STACK

43


DATA EEPROM AND FLASH PROGRAM MEMORY

The Data EEPROM and FLASH Program Memory are readable and writable

during normal operation over the entire VDD range. A bulk erase operation may not be issued

from user code (which includes removing code protection). The data memory is not directly

mapped in the register file space. Instead it is indirectly addressed through the Special

Function Registers (SFR). There are six SFRs used to read and write the program and data

EEPROM memory. These registers are

EECON1

EECON2,

EEDATA,

EEDATH,

EEADR, and

EEADRH.

44


The EEPROM data memory allows byte read and writes. When interfacing to

the data memory block, EEDATA holds the 8-bit data for read/write and EEADR holds the

address of the EEPROM location being accessed. The registers EEDATH and EEADRH are

not used for data EEPROM access. These devices have up to 256 bytes of data EEPROM

with an address range from 0h to FFh. The EEPROM data memory is rated for high

erase/write cycles. The write time is controlled by an on-chip timer. The write time will vary

with voltage and temperature, as well as from chip-to-chip. Please refer to the specifications

for exact limits. The program memory allows word reads and writes. Program memory access

allows for checksum calculation and calibration table storage. A byte or word write

automatically erases the location and writes the new data (erase before write). Writing to

program memory will cease operation until the write is complete. The program memory

cannot be accessed during the write, therefore code cannot execute. During the write

operation, the oscillator continues to clock the peripherals, and therefore they continue to

operate. Interrupt events will be detected and essentially “queued” until the write is

completed. When the write completes, the next instruction in the pipeline is executed and the

branch to the interrupt vector address will occur.

When interfacing to the program memory block, the EEDATH:EEDATA registers form a

two byte word, which holds the 14-bit data for read/write.

The EEADRH:EEADR registers form a two byte word, which holds the 13-bit address

of the EEPROM location being accessed. These devices can have up to 8K words of program

EEPROM with an address range from 0h to 3FFFh. The unused upper bits in both the

EEDATH and EEDATA registers all read as “0’s”.

The value written to program memory does not need to be a valid instruction.

Therefore, up to 14-bit numbers can be stored in memory for use as calibration parameters,

serial numbers, packed 7-bit ASCII, etc. Executing a program memory location containing

data that orms an invalid instruction results in a NOP.

EEADR

The address registers can address up to a maximum of 56 bytes of data EEPROM or up to a

maximum of 8K ords of program FLASH. When selecting a program address value, the

MSByte of the address is written to the EEADRH register and the LSByte is written to the

45


EEADR register. When selecting a data address value, only the LSByte of the address is

written to the EEADR register. On the PIC16F873/874 devices with 128 bytes of EEPROM,

the MSbit of the EEADR must always be cleared to prevent inadvertent access to the wrong

location. This also applies to the program memory. The upper MSbits of EEADRH must

always be clear.

EECON1 and EECON2 Registers

EECON1 is the control register for memory accesses. EECON2 is not a physical

register. Reading EECON2 will read all '0's. The EECON2 register is used exclusively in the

memory write sequence. Control bit EEPGD determines if the access will be a program or a

data memory access. When clear, any subsequent operations will operate on the data memory.

When set, any subsequent operations will operate on the program memory .Control bits RD

and WR initiate read and write operations , respectively. These bits cannot be cleared, only

set, in software. They are cleared in hardware at the completion of the read or write operation.

The inability to clear the WR bit in software prevents the accidental or premature

termination of a write operation. The WREN bit, when set, will allow a write operation. On

power-up, the WREN bit is clear. The WRERR bit is set when a write operation is interrupted

by a MCLR reset or a WDT time-out reset during normal operation. In these situations,

following reset, the user can check the WRERR bit and rewrite the location. The value of the

data and address registers and the EEPGD bit remains unchanged. Interrupt flag bit EEIF, in

the PIR2 register, is set when write is complete. It must be cleared in software.

Reading the Data EEPROM Memory

To read a data memory location, the user must write the address to the EEADR register,

clear the EEPGD control bit (EECON1<7>) and then set control bit RD (EECON1<0>). The

data is available in the very next instruction cycle of the EEDATA register, therefore it can be

read by the next instruction. EEDATA will hold this value until another read operation or

until it is written

to by the user (during a write operation).

Writing to the Data EEPROM Memory

46


To write an EEPROM data location, the address must first be written to the EEADR register

and the data written to the EEDATA register.

Watchdog Timer (WDT)

The Watchdog Timer is as a free running on-chip RC oscillator which does not require any

external components. This RC oscillator is separate from the RC oscillator of the

OSC1/CLKIN pin. That means that the WDT will run, even if the clock on the OSC1/CLKIN

and OSC2/CLKOUT pins of the device has been stopped, for example, by execution of a

SLEEP instruction. During normal operation, a WDT time-out generates a device RESET

(Watchdog Timer Reset). If the device is in SLEEP mode, a WDT time-out causes the device

to wake-up and continue with normal operation (Watchdog Timer Wake-up). The TO bit in

the STATUS register will be cleared upon a Watchdog Timer time-out.

The WDT can be permanently disabled by clearing configuration bit WDTE WDT time-out

period values may be found in the Electrical Specifications section under parameter #31.

Values for the WDT prescaler (actually a postscaler, but hared with the Timer0 prescaler)

may be assigned sing the OPTION_REG register

WATCHDOG TIMER DIAGRAM

47


Instruction Descriptions

48


49


50


51


52


53


54


55


8255A-5

PROGRAMMABLE PERIPHERAL INTERFACE

Features :

MCS-85 Compatible 8255A-5

24 Programmable I/O Pins

Completely TTL Compatible

Fully Compatible with Intel Microprocessor Families

Improved Timing Characteristics

Direct Bit Set/Reset Capability Easing Control Application Interface

Reduces System Package Control

Improved DC Driving Capability

The Intel 8255A is a general purpose programmable I/O device designed for use

with Intel microprocessors. It has 24 I/O pins which may be individually programmed in 2

groups of 12 and used in 3 major modes of operation. In the first mode (MODE0), each group

of 12 I/O pins may be programmed in sets of 4 to be input or output. In MODE1, each group

may be programmed to have 8 lines of input or output. Of the remaining 4 pins, 3 are used for

handshaking and interrupt control signals. The third mode of operation (MODE2) is bi-

directional bus mode which uses 8 lines for a bi-directional bus, and 5 lines, borrowing one

from the other group, for handshaking.

Pin Diagram

56


57


8255A BLOCK DIAGRAM

58


MC 14503B

59


HEX NON-INVERTING 3-STATE BUFFER

The MC14503B is a hex non–inverting buffer with 3–state outputs, and a high current source

and sink capability. The 3–state outputs make it useful in common bussing applications. Two

disable controls are provided. A high level on the Disable A input causes the outputs of

buffers 1 through 4 to go into a high impedance state and a high level on the Disable B input

causes the outputs of buffers 5 and 6 to go into a high impedance state.

3–State Outputs

TTL Compatible Will Drive One TTL Load Over Full Temperature Range

Supply Voltage Range = 3.0 Vdc to 18 Vdc

Two Disable Controls for Added Versatility

Pin for Pin Replacement for MM80C97 and 340097]

PIN DIAGRAM

60


61


62


SN54/74LS157

QUAD 2-INPUT MULTIPLEXER

The LSTTL/MSI SN54/ 74LS157 is a high speed Quad 2-Input Multiplexer. Four

bits of data from two sources can be selected using the common Select and Enable inputs.

The four buffered outputs present the selected data in the true (non-inverted) form. The

LS157 can also be used to generate any four of the 16 different functions of two variables.

The LS157 is fabricated with the Schottky barrier diode process for high speed and is

completely compatible with all Motorola TTL families.

• Schottky Process for High Speed

• Multifunction Capability

• Non-Inverting Outputs

• Input Clamp Diodes Limit High Speed Termination Effects

• Special Circuitry Ensures Glitch Free Multiplexing

• ESD > 3500 Volts

Applications & Features

Expand any data input point

Multiplex dual data buses

Generate four functions of two variables(one variable is common)

Source programmable counters

Buffered inputs and outputs

Typical Propagation Time

DM74LS157 9 ns

DM74LS158 7 ns

Typical Power Dissipation

DM74LS157 49 mW

DM74LS158 24 mW

63


PIN DIAGRAM

64


65


66


ULN2003 LINEAR INTEGRATED CIRCUIT

SEVEN DARLINGTON ARRAYS

DESCRIPTION

The UTC ULN2003 is high-voltage,high-current darlighton

drivers comprised of seven NPN darlington pairs.

FEATURES

*Output current (single output) 500mA MAX.

*High sustaining voltage output 50V MIN.

*Output clamp diodes

*Inputs compatible with various types of logic

APPLICATIONS

*Relay, hammer, lamp and display (LED) drivers.

PIN DIAGRAM

67


68


69


70


ADVANTAGES:

Cost effective and time efficient

Provides better security

Easy to construct and install

Consumes less energy and is more efficient.

Increases the over all efficiency of the system.

Works at high speeds.

Has wider range of applications

Etc.

71


APPLICATIONS:

Used in communication industry

Used in process control industries

Used in defense

Used in domestic and industrial applications

Used in Data loggers

Used in the R & D industries.

Etc.

72


FUTURE ENHANCEMENTS:

The project can done using Graphical LCD also

Higher capacity PIC can be used to store more data.

The project can be demarked to work with running LCD display.

The RF can also be used for the communication

73


CONCLUSIONS:

With the available facilities and the infrastructure provided, we were successful in

completing the project in the stipulated time using the PIC module. The testing of the project

took a lot of time in the whole process. The demonstration was taken into account for

rotation of the chair only. With the slight modifications it can also be used for the motion of

the chair. The project proved to be in expensive to construct to the applications that it can

provide. Given more time the same could have been developed with a lot of built features

also.

.

74


BIBLIOGRAPHY:

Communications and analysis by Ann Hyde

Intel data Hand book

www.google.com

www.microchip.com

www.epanorama.com

www.ams2000.com

www.dpmotor.com

75

http://www.dpmotor.com/

http://www.ams2000.com/

http://www.epanorama.com/

http://www.microchip.com/

http://www.google.com/


76

speech based wheel chair control final project report

Documents