Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering, University of Rostock Slide 1

Spezielle Anwendungen des VLSI – Entwurfs

Applied VLSI design

Course and contest

Results of Phase 3

Sebastian Kruse

Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering, University of Rostock

Optimizations

Slide 8

• Change of coefficent Now no adder is needed for calculation

Look for higher metric at lower voltage area

• Comparison between different adder types

Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering, University of Rostock

Carry Skip Adder

Slide 8

CLA

𝑎0𝑏0

CLA

𝑎1𝑏1

CLA

𝑎2 : 3𝑏2: 3

CLA

𝑎4 : 6𝑏4 : 6

CLA

𝑎7 : 8𝑏7 : 8

CLA

𝑎9𝑏9

𝑠0 𝑠1 𝑠2 : 3 𝑠4 : 6 𝑠7 : 8 𝑠9

𝑐𝑜𝑢𝑡 ,0 𝑐𝑜𝑢𝑡 ,6 𝑐𝑜𝑢𝑡 ,8𝑐𝑜𝑢𝑡 ,3𝑐𝑜𝑢𝑡 ,101

01

01

• Delay time of O()

• Variable block size

• Area compared to RCA:

Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering, University of Rostock

• Han Carlson

• Brent Kung

Han Carlson / Brent Kung

Slide 4

Source: Binary Adder Architectures for Cell-Based VLSI and their Synthesis, Prof.Dr. W. Fichtner, 1997

Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering, University of Rostock

Comparison between FPGA and ASIC

Slide 8

• FPGA { Frequency / Area } Carry Skip: 324.044 MHz / 143 LUT Ripple Carry: 426,439 MHz / 109 LUT Han Carlson: 332,779 MHz / 128 LUT Brent Kung: 293,083 MHz / 135 LUT

• ASIC { Frequency / Pdyn / Pleak } Carry Skip: 356 MHz / 3,156 nW / 19,330 nW Ripple Carry: 390 MHz / 3,135 nW / 19,185 nW Han Carlson: 356 MHz / 3,146 nW / 19,241 nW Brent Kung: 356 MHz / 3,148 nW / 19,244 nW

Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering, University of Rostock

Filter response

Slide 9

FPGA ASIC

Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering, University of Rostock

Results

Slide 10

Mandatory values for ASIC

Frequency f 900,00 MHz

Area A 2864.67

Power PDyn 3,135 nW

Power PLeak 19,185 nW

# Pipeline Stages 8

Metric (10-3 / (pJ)²) [2,532]

Used parameters for synthesis in Synopsys:• set frequency 0.001• compile_ultra• set_max_leakage_power 0 mw• set_max_dynamic_power 0 mw• set_wire_load_mode top

Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering, University of Rostock

Future improvements

• Change type of adder (phase 3) Brent Kung adder Han Carlson adder Carry skip adder

• Only do an addition for important digits

• Summation compression (Wallace tree) Carry save representation

Slide 11

Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering, University of Rostock

Thank you for your attention!

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