spice circuit handbook

SPICE Circuit Handbook

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Steven M. Sandler

Charles Hymowitz

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http://dx.doi.org/10.1036/0071468579

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DOI: 10.1036/0071468579
http://dx.doi.org/10.1036/0071468579

This book is dedicated to my wife Susan and mydaughters Shanna and Rachel. It is you whoencourage me to be the best I can be.

Steven M. Sandler

This book is dedicated to my wife Teresa and mythree wonderful blessings, Mitchell, Olivia, andMakenna. You make it all worthwhile.

Charles Hymowitz

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Contents

Acknowledgments xi

Chapter 1. Introduction 1

Chapter 2. Description of the PSpice, IsSpice, SIMetrix, andMicro-Cap Simulators 7

Basic Overview of SPICE 10SPICE syntax and tutorial 10DC analysis 11Transient analysis 12AC analysis 13

Simulation Types and Data Acquisition 14Convergence Problems 14

Steps to avoid common mistakes 14DC convergence solutions 15Transient convergence solutions 16AC convergence solutions 17

Chapter 3. Filter Circuits 19

Fourth-Order Butterworth Low Pass Filter 19Fourth-Order Butterworth High Pass Filter 24Fourth-Order Butterworth Band Pass Filter 25BesselThompson Delay Low Pass Filter 27BesselThompson Delay Low Pass Filter with Pulse Shaper 33Inverted BesselThompson Delay High Pass Filter 37Chebyshev Band Pass Filter 39Chebyshev Low Pass Filter 46Chebyshev High Pass Filter 52Electromagnetic Interference (EMI) Filter 52

Chapter 4. Power Conversion Circuits 61

LM117 Three-Terminal Linear Regulator 61LM78S40 Simple Switcher DC-to-DC Converter 68

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UA723 Hysteretic Buck Regulator 731524A Buck Regulator 82Low Drop-Out Regulator 93STR6600 Quasi-Resonant Discontinuous Flyback 106Discontinuous Flyback Converter 112

Chapter 5. Electronic Load Circuits 119

Power Section of an Electronic Load 119Positive DC to Negative DC Comparator Converter 129Built-in Variable Electronic Load Adjustment 133Electronic Load Using Power BJT Transistors 137

Chapter 6. Instrumentation Circuits 143

555 Timer 143555 Missing-Pulse Detector 148Class AB Amplifier 160Window Detector 161Voltage Clamp 176Resistance to Voltage 176Polarity Gain 186

Chapter 7. Logic Circuits 195

Binary Counter 195Binary Decoder 199Set-Reset Latch 205Staircase Generator 208

Chapter 8. Resonator/Oscillator Circuits 215

555 Timer Oscillator 215Fourth-Order Butterworth Low Pass Oscillator 216Hex Inverter Oscillator 222Fourth-Order Butterworth No-Offset Low Pass Oscillator 228Harmonic Neutralized Sine-Wave Oscillator 236Colpitts Oscillator 244Schmitt Trigger Oscillator 250LM111 Oscillator 256

Chapter 9. Gate Drive Circuits 261

UC1846 50% Duty Cycle Gate Drive Circuit 262555 Pulse-Shaped MOSFET Driver 266Zero-to-100% Duty Cycle Driver 269

Chapter 10. Voltage Multiplier Circuits 277

AC-to-DC Voltage Doubler 277Cascade Doubler 281

Contents ix

Bridge AC-to-DC Doubler 285AC-to-DC Quadrupler 287AC-to-DC Octupler ( 8) 292High Voltage, High Current DC-to-DC Doubler 297

Index 305

Acknowledgments

We would like to thank AEi Systems personnel, including MarkKwamusi, Greg Boger, and Danny Chow, for performing all of the sim-ulations for this book in an effort to obtain the best relative run timespossible, capturing and running most if not all simulations on the samecomputer.

Thanks to Steve Chapman, the publisher at McGraw-Hill, for contin-uing to provide us these opportunities to write.

Thanks to John Wagner and his guys at Catena Software Ltd. forcreating SIMetrix, Andy Thompson and the guys at Spectrum Softwarefor creating Micro-Cap, Larry Meares and Intusoft for creating IsSpice,and OrCAD for creating PSpice.

Thanks to Priyanka Negi and the staff at TechBooks for the outstand-ing effort they put into creating this book.

Thanks to Ron Rohrer, Larry Nagel, and all the students at the Uni-versity of California, Berkeley, who worked hard in 1969 and 1970 todevelop the first computer simulation software, Cancer (ComputerAnalysis of Non-Linear Circuits Excluding Radiation). This effort wouldresult in the release of SPICE into the public domain in 1971.

Steven M. SandlerCharles Hymowitz

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Chapter

1Introduction

Since its introduction in 1971, SPICE (Simulation Program with Inte-grated Circuit Emphasis) has become the most popular analog simu-lation tool in use today. In the last 15 years, we have seen explosivegrowth in the use of SPICE, with the addition of Berkeley SPICE 3 en-hancements, and support for C code model and mixed-mode simulationusing XSPICE (Cox et al. 1992, Kielkowski 1994).We have also seenmany new companies emerge as developers of SPICE-based simulationtools, most of which are currently available for the PC platform.

Each vendor of SPICE simulation software has added features suchas Monte Carlo analysis, schematic entry, and post simulation wave-form processing, as well as extensive model libraries. In most cases,the manufacturers have modified the algorithms for controlling conver-gence and have added new parameters or syntax for component models.As a result, each electronic design automaton (EDA) tool vendor has thebasic Berkeley SPICE 2 features and a unique set of capabilities andperformance enhancements.

We have also seen component manufacturers providing SPICE modelsupport. Many of these manufacturers provide models of componentssuch as MOSFETs, transistors, and operational amplifiers. Most ofthese models are available for free via the manufacturers web sites,though not all are accurate or well documented. One company filling thevoid in the modeling area, especially with respect to power electronics,is AEi Systems, LLC (AEi Systems 2005; www.AENG.com). The abil-ity of computers to simulate electronic circuits is increasing every day.The often-quoted Moores law states that the speed of microprocessorsdoubles nearly every 18 months. As computers become more powerfuland more capable, computer simulation is becoming a significant toolin the design process.

1

www.AENG.com

2 Chapter One

Unfortunately, there is still unwillingness in the electronic designcommunity to embrace the abilities of computers to emulate circuitbehavior. Many engineers still dont take SPICE simulation seriously.Typically, a design engineer, on being shown a SPICE model of theimpeding failure of his or her circuit, will reply, Thats nice, but lets seewhat the hardware does. Even when the hardware fails, the engineeris more likely to investigate the charred and smoking breadboard thanthe SPICE model that predicted the result.

The purpose of this book is to showcase the ability of SPICE, viathe simulation tools of several EDA vendors, to accurately predict thebehavior of electronic circuitry.

The time it takes to run a simulation is orders of magnitude lessthan the time it takes to build the equivalent circuit on a breadboard. Asimulation can be run through any number of environmental conditionswith easeconditions often unavailable or impractical to duplicate ina laboratory environment. Circuit stimulus and tolerances and theireffect on the operation of the circuit can be easily evaluated.

Still, there are limitations to the capabilities of SPICE and similarcircuit simulators. While the sophistication of simulation increases, thehardware breadboard will still remain a necessary step in the designprocess. This book will aid the engineer in using SPICE simulation asa very powerful tool in the design process.

This book is a compilation of all various types of electronic circuits.Such compilations are not unusual; in fact, there are several excellentcircuit encyclopedias on bookshelves. However, this book goes severalsteps further. Instead of simply presenting the circuit to the reader, italso provides a SPICE schematic and details about the equivalent hard-ware performance. The intricacies involved in developing an accurateSPICE model of the circuit are also included. This format benefits read-ers in numerous ways. First, it allows them to emulate the correlationtechniques introduced in this book in order to make their own SPICEmodels accurately mimic the behavior of the hardware. Secondly, it al-lows them to clearly see where SPICE excels in its ability to representreal hardware performance.

SPICE simulation gives design engineers a vast array of informationthat can help ensure a successful and optimal design of their hardware.If designers have circuit designs that they know operate correctly un-der nominal conditions and also have a SPICE model that can accu-rately reflect the designs behavior they are much more likely to beable to produce a design that will operate under all operating condi-tions. Clearly, SPICE simulation can be a much more integral step inthe design process and prove its worthiness to engineers of any circuitdiscipline.

Introduction 3

The beginning of the book concentrates on the basics of computersimulation of electronic circuits. A brief overview of four popular SPICEprograms is provided along with their basic differences.

We have selected a broad cross section of analog and mixed-modedesigns, which we have simulated, as well as constructed. The circuitsare grouped into logical chapters. Generic topics, such as oscillators,amplifiers/receivers, power converters, and filters, all head their ownchapter. Each chapter starts with a brief overview of the function ofthe circuits in the chapter. This is followed by several circuit examples.For instance, in the chapter on reference circuits, the beginning detailswhat reference circuits are and their uses at the system level. This isfollowed by a detailed discussion on a single type of reference circuit,the band gap reference.

The theory of operation of each circuit is discussed, followed by thecircuit schematic, the simulation results, and a comparison to labora-tory data. Advantages and disadvantages of each circuit are added,along with any tips or hints useful in modeling the circuit accurately.We have attempted to perform each simulation using several versions ofSPICE for comparison. Also included are the run times for each circuitsimulation.

Four simulation programs were used to simulate the circuits inthis book: ICAP/4Windows/IsSpice4 v8.11, OrCAD/PSpice v10.5,SIMetrix v5.1, and Micro-Cap v8.0.

The simulations in this book were performed using a PC desktopcomputer running a 2.8 GHz Intel microprocessor, 512 MB RAM, andWindows XP Professional.

The run times of the circuits are highly dependant on the CPUsand memory capabilities of the computers running them, as well asthe .TRAN and .OPTIONS settings in the simulation. It should benoted that any simulation program can be made to run faster orslower than any other program just by changing various variables, eventhough comparable output results are obtained. With slight changesin parameters like RELTOL, ABSTOL, VNTOL, TRTOL, or TMAX,simulations have been shown to run 14 times faster (Sandler 1996).Each circuit can be optimized for speed differently, and each EDAvendors SPICE program has its own set of enhanced simulation op-timization and modeling features. Similarly, the same function orindividual component can be modeled in different ways, causing dra-matic differences in simulation performance. Tricks that speed up sim-ulations in one circuit may not work in another, or even have theopposite effect on speed. Invariably, SPICE simulations are a trade-off between simulation speed, accuracy, and convergence (Kielkowski1994).

4 Chapter One

We have made a reasonable effort to make apples to apples com-parisons between the simulation speeds of the software in this bookby using commonly available Berkeley SPICE 2 OPTIONS. The readerwill notice that it is not predictable which software package will run thefastest on any given circuit. The real purpose of including the run timesis to provide the user with an estimate as to how long the circuit willtake to simulate on his or her own computer, nothing more. That beingsaid, the simulation times noted after the simulations are reasonablyaccurate.

The reader will also note that in some circumstances, one or more ofthe simulation software results did not match the hardware results. Wehave attempted to explain the reasons why this might have occurred.Bear in mind that SPICE is one of those labors in life where you get outof it what you put into it. If you put very little effort into understandingwhat the models and circuit are doing, chances are your simulationaccuracy will be poor.

The CD-ROM that comes with this book contains four simulationfile folders, one for each of the four simulators. Each folder containsthe relevant simulation files for that particular simulator. Schemat-ics in their native format are provided in all cases. The circuit namesare provided in the appropriate section for that circuit. For exam-ple, Circuit 1, a fourth-order Butterworth low pass filter, lists the filenames for that circuit as follows: lp fltr (IsSpice), lpflt (Micro-Cap),lp flt (PSpice). Demonstration versions of each simulation tool set arealso included. For SIMetrix both a PC version and a Linux version areincluded.

To make the circuits in this book and your own simulations more use-ful, we suggest you investigate the Power IC Model Library from AEiSystems, LLC (www.AENG.com/PSpice.asp). This product provides awide variety of popular switching regulator and PWM IC models, mostof which are verified against hardware and not readily available any-where else. A multitude of application circuit examples are also in-cluded in the library. Modeling components using the data sheet in-formation, as is done by most EDA vendors, is not sufficient to modelcomplex parts like power electronics ICs. AEi Systems has taken thetime to develop proprietary relationships with IC manufacturers in or-der to obtain the necessary information.

We have put a great deal of effort into the construction of this book.It is our sincere hope that the reader benefits from our hard work.

Bibliography

AEi Systems. 2005. EMA Design Automation and AEi Systems Announce New PowerIC Model Library for PSpice, Rochester, NY, June 28. Press release.
www.AENG.com/PSpice.asp

Introduction 5

Cox, F. L., III, W. B. Kuhn, J. P. Murray, and S. D. Tynor. 1992. Code-levelModeling in XSPICE, in Proceedings of the IEEE International Symposium onCircuits and Systems, 1992 (ISCAS 92), vol. 2, pp. 871874, http://users.ece.gatech.edu/mrichard/Xspice

Kielkowski, Ron M. 1994. Inside Spice. New York: McGraw-Hill.Sandler, Steven M. 2006. Switch-Mode Power Supply Simulation with PSpice and SPICE

3. New York: McGraw-Hill.Sandler, Steven M. 1996. SMPS Simulation with SPICE 3. New York: McGraw-Hill.
http://users.ece.gatech.edu/~mrichard/Xspicehttp://users.ece.gatech.edu/~mrichard/Xspice

Chapter

2Description of the PSpice,

IsSpice, SIMetrix, andMicro-Cap Simulators

The development of SPICE was initiated by Ron Rohrer, a junior facultymember at the University of California, Berkeley. Rohrer was teachinga class on circuit simulation, in which he and Larry Nagel developed asimulator using the FORTRAN programming language that was to benamed CANCER (Computer Analysis of Nonlinear Circuits ExcludingRadiation). It was difficult to test integrated circuits (ICs), but SPICEwas thought to be an answer to the quick and reliable design of ICs.Larry Nagel increased the capabilities of CANCER by increasing the400 component or 100 node limit, adding new and improved compo-nents and a macromodeling capability. In 1971, Nagel released thisimproved version of CANCER as SPICE 1 (Simulation Program withIntegrated Circuit Emphasis). In 1975, SPICE 2 was released, whichoffered equation formulation for voltage-defined elements as well asincreased simulation speed. This was achieved through the develop-ments of time step control algorithms. The capabilities of SPICE grewwith those of computers.

In 1983, SPICE 2G.6 was released and remained the industry stan-dard for many years. Motivated by the increased use of UNIX worksta-tions and superior programming tools, SPICE 2 was converted into theC programming language and released as SPICE 3. Although SPICE 3is not entirely backward compatible with SPICE 2, the new features faroutweigh this drawback. SPICE 3 has a technical advantage of beingreadily modified because it is written in C. SPICE 3 also offers moreand improved device models and analysis functions.

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8 Chapter Two

A major improvement in terms of usability has been the addition of agraphical waveform post processing and schematic capture tools. Wave-form post processors greatly facilitate computation and documentationof simulation results. Schematic capture automates the SPICE netlistgeneration dramatically reducing the number of syntax errors.

Understanding the development of SPICE is useful in making aworthwhile comparison of vendor-offered simulation software. Thefoundation of many vender-offered simulators is Berkeley SPICE 3F.5combined with XSPICE from the Georgia Institute of Technology.XSPICE is an add-on to SPICE 3, enhancing it with several key fea-tures, including a mixed-mode simulation capability (true digital simu-lator) and over 40 new primitive functional blocks such as Laplace andstate machine elements.

Four of these software manufacturersOrCAD (PSpice), Intusoft(IsSpice), Micro-Cap V (Micro-Cap), and Catena (SIMetrix)have theirproducts featured in this book. With the exception of PSpice, which usesa greatly enhanced version of SPICE2G.6, these software manufactur-ers took the Berkley SPICE 3F.5 core and wrapped schematic and wave-form display programs around it. The schematic entry tools translatethe user-defined design into an ASCII netlist using SPICE syntax. Thecircuit is processed by SPICE and an answer is generated. The soft-ware then takes the result from SPICE and passes it into a graphicspostprocessor in order to display the answers in a meaningful form.

The tool flow used by EDA vendors to enhance the basic SPICE engineis roughly the same. Four separate modules are utilized (see Table 2.1).

The first module is the schematic capture program. Originally, usingSPICE meant translating a schematic by hand into the SPICE descrip-tion language for calculation. The schematic capture program allowsthe user to pull down parts from a menu, wire together the components

TABLE 2.1 The Four Simulation Tool Modules and Their Functions

Schematic Graphical postcapture Text editor SPICE Simulator processor

Allows users toquickly generateSPICE-compatiblenetlists graphically.Cross-probingallows users toeasily view varioussimulation results inthe post processor byclicking on the objectin the schematic.

Examines outputfiles from SPICE.Examines SPICEnetlists generatedby the schematiccapture program.

Performs numericaliteration of thecircuit to determinesolutions in variousdomains (time,frequency, DC, etc.).

Converts the textoutput of SPICEinto moremeaningful graphsand waveforms.Has the ability toperform complexnumericalcalculations onwaveforms.

Description of the PSpice, IsSpice, SIMetrix, and Micro-Cap Simulators 9

using a mouse, and click a button to start the simulation. The schematicbuilding feel of the schematic capture programs helps SPICE users toquickly translate their circuit ideas into a schematic compatible withSPICE.

A text editor is also included and is an invaluable tool for viewing thegenerated output text files of SPICE, as well as investigating syntaxerrors and other subtleties of the SPICE programming language. Thetext output of SPICE is in an excellent format for exporting to otheruseful engineering tools such as Excel or MathCAD.

The third module is the simulator itself. As stated earlier, each ofsimulators from the different software vendors uses the core code fromBerkeley to iterate solutions of the circuit using mesh equations.

The fourth module is the graphics waveform postprocessor. It has thefeel of an oscilloscope, translating SPICEs numerical data output intowaveforms. Many different mathematical operations can be performed,such as integration, FFTs, etc. allowing users to get the most out ofSPICE.

A key difference between the products offered by vendors relates tohow the user interfaces with the simulation engine, and the featuresoffered by the various modules. Model libraries are also a key distin-guishing characteristic of a vendors offering.

Users can create their own models, but most of the time they willdepend on the model libraries provided by a vendor. The library modelsthat do not use pure Berkeley SPICE 2G.6 syntax are unique to thatparticular simulator. While the SPICE syntaxes of each product aresimilar, they are not exactly compatible; both distinct and subtle differ-ences exist. However, in many cases, most models in vendors librarieshave been provided by the component manufacturers. These models areavailable for free on the Internet.

It is very important to test and qualify models in a library, ratherthan assuming that they are accurate. The library governs the accuracyof the simulation in which they are used. Just because a model is in alibrary does not mean that it provides correct results or that it has beenverified over even a small portion of the operation range of the real part.

Each of the simulators has a schematic editor program, which is usedto enter the circuit into the simulator. Accessing the overall quality ofa particular schematic editor comes down to preferences. Even thoughan assessment may be made from the number of keystrokes or clicks ofthe mouse required to enter a circuit, a users effectiveness is a functionof familiarity and comfort. Maximizing the performance of a schematiceditor is dependant on the user and is difficult to determine.

The same can be said when evaluating the performance of thewaveform postprocessor. Familiarity governs the ability of a user tomanipulate the output data into a desirable viewing form. All of the

10 Chapter Two

postprocessors have similar features, and therefore, accessing the per-formance of a particular postprocessor depends on the preferences ofthe user.

Basic Overview of SPICE

SPICE starts a simulation by making an initial guess at the circuitsnode voltages and then, using the nodal equations of the circuit,calculates the mesh currents. The mesh currents are then used torecalculate the node voltages, and the cycle begins. This iterativeprocess continues until the nodal equations have been solved withinspecified tolerance limits. These limits can be set by using .OPTIONparameters (Reltol, Vntol, and Abstol). As the difference between eachiteration approaches zero, the simulation approaches convergence towhat it deems is the final answer. SPICE uses the NewtonRaphsonalgorithm to solve the matrix of nodal equations if the circuit containsa nonlinear device. For a circuit containing only linear devices, SPICEuses Gaussian elimination to solve the matrix.

SPICE syntax and tutorial

The first line of any SPICE netlist is the title line. It is used for docu-mentation purposes only. The next few lines usually tell SPICE whichanalysis will be performed and what the bounds of that analysis willbe. For example, we may be requesting a time domain analysis of a cir-cuit (called a transient analysis). The information as to how long thewaveform is and what increments and what section of it are of inter-est is defined in this section of the code. SPICE netlists generally haveone function, command, or element per line (Fig. 2.1). Also defined up-front are global constants, subcircuits (models) used repeatedly in themain circuit, and instructions on which nodes are of interest in the finalsolution, though this structure is not mandatory.

The middle section of the code defines the circuit itself. The structureof each component is roughly similar. The first variable is the referencedesignator. The next variable is the number of nodes that the component

*EXAMPLE CIRCUIT #1.TRAN 1U 100U 10U 2U UIC.OPTIONS METHOD=GEAR.PRINT TRAN V(2).IC V(7)=12

Figure 2.1 Typical lines of the beginning of a SPICE netlist.


R1 1 0 100KL1 1 2 10UQ1 2 3 4 2N2222AV INPUT 4 0 10I OUT 3 0 PULSE 0 1 1U 100N 100N 10U 20U

Figure 2.2 Typical lines of the middle of a SPICE program.

is connected to. The remaining variables define the parameters of thatcomponent.

A simple example is a resistor:

R1 1 2 100K

In this line, resistor R1 is defined as a resistor connected from node 1 tonode 2 with a value of 100 k. Several rules apply in defining compo-nents. Node 0 is reserved for ground. All circuits must have at least oneground connection. Also, reference designators are limited to alphanu-meric characters (Fig. 2.2). Longer statements may be continued on thefollowing line by using a + symbol as the first character to indicate acontinuation from the previous line.

The final line of any SPICE program must be the .END statement.Several basic analyses are used in this book. An explanation of each

is given in the following paragraphs.

DC analysis

Before SPICE performs any specified simulation, a DC operating pointanalysis, .OP, is performed. This establishes the DC bias point of thecircuit. There generally must be convergence of this simulation beforeany other specified simulation can be performed. SPICE calculates theDC operating point by replacing all inductors with shorts, and it treatsall capacitors as open circuits. SPICE must determine the DC oper-ating point within a specified number of iterations, otherwise a non-convergence warning is generated and the simulation is aborted. Thedefault .OPTIONS statement used to determine the DC iteration limitis

.OPTIONS ITL1=100For nonconvergence, the value of ITL1 should be increased to greaterthan 500, which increases the maximum allowed number of iterationsto determine the solution.

Simulators today sport many DC convergence options that are gener-ally invoked automatically when the basic method fails. These includeGMIN stepping, source stepping, initial capacitor voltage stepping, and

12 Chapter Two

pseudotransient. Several convergence helpers are discussed below, andthey apply to all Berkeley SPICE compatible programs.

A .NODESET statement can also be used to reduce the number ofiterations required for convergence. The DC voltage of a node can bespecified by the user, and it will be used by SPICE in the initial guess ofthe simulation. This can greatly reduce the number of iterations thatare required for convergence.

If convergence is not attained by using a nodeset and increasingthe ITL1 statement, then an ITL6 statement can be used. By settingITL6 = 100, or any nonzero value, a source stepping algorithm is used,which decrements the voltage sources down to zero, or until conver-gence is reached, and then they are stepped back up to their assignedvoltage levels. This appears to be the solution to all DC bias point con-vergence problems. However, there are bugs associated with the ITL6function, and so it should be used only as a last resort.

If the circuit contains semiconductor devices, then it contains regionsof zero conductance. This can result in a divide-by-zero error. To elim-inate this problem, every PN junction in every SPICE semiconductordevice has a GMIN transconductance in parallel with every PN junc-tion. GMIN is assigned globally and has a default value of 100 p. Thelarger the value of GMIN, the faster the NewtonRaphson algorithmwill converge to a solution. Raising GMIN decreases the size of theshunt resistor. The accuracy of the simulation is not affected as long asthe current generated in the shunt resistors is lower than the relativeerror tolerance current resolution (Kielkowski 1995). A suggested valuefor setting GMIN is given in the following statement:

.OPTIONS GMIN=1n

Transient analysis

A transient time domain analysis begins with a DC operating pointanalysis unless SPICE is specifically told to skip it. SPICE calculatesthe DC operating point by replacing all inductors with shorts, and allcapacitors with open circuits. SPICE must determine the DC operatingpoint within a specified number of iterations, otherwise a nonconver-gence warning is generated and the simulation is aborted. The solutionto the DC operating point determines the node voltages at the timeT = 0. SPICE then assigns the instantaneous I-V relationship of induc-tors or capacitors and uses a numeric integration routine to create anequivalent nodal matrix. The nodal matrix changes for every time stepin the transient analysis. Each NewtonRaphson iteration that followsstarts with an initial guess at the previous set of node voltages. Thisexpedites the iterative process, which continues until the solution isfound or the maximum allowed iterations are exceeded. The maximum


number of iterations is determined by the setting the .OP-TIONS statement ITL4. The default .OPTIONS statement is givenbelow:

.OPTIONS ITL4=10 ; use ITL4=1500 if transient convergenceproblems occur

When the simulation steps to the next point in time, the tran-sient solver determines the operating point at that moment in time. Ifthe simulation does not reach convergence at this point in time, thenthe time step is reduced by one-eighth. This is repeated until conver-gence is achieved or the maximum number of times that the time stepcan be reduced, which is specified by ITL4, is reached. A large timestep, which is also user defined, in a transient simulation can result inconvergence difficulties. This is particularly true for switching circuits.The time step must be small enough to provide enough resolution toidentify switching voltage levels. Large voltage transitions or devicemodel discontinuities must be taken into account when assigning thetransient simulation parameters. An example of a transient simulationstatement is given below:

.Tran Tstep Tstop Tstop Tmax UIC

.Tran 10u 10m 0 20u UIC

The time step Tstep = 10u determines each point in time starting fromzero that the transient solver will calculate a solution. A safe estimationof the time step is an order of magnitude less than the period of aswitching waveform. For example, the time step for a 100 kHz oscillator(period = 10 s) should be approximately 1 s. Tmax, the maximumtime step, can be left out (at default) or specified to increase (decreaseTMAX) or decrease (increase TMAX) simulation accuracy. This allowsthe simulator to take larger steps when the voltage levels in the circuitexperience little change. A transient time domain analysis can prove tobe the most difficult to get to converge.

AC analysis

An AC analysis begins by determining the DC bias point of the circuit.This can be critical, because it determines the state of the active devices.For instance, the output of a linear regulator or operational amplifier isdifferent if it is operating in the linear region, or if it is operating in thesaturated region. After SPICE determines the DC operating point, thelarge signal transistor and diode models are converted into linear small-signal models. All nonlinear effects of the circuit will not be accountedfor in the AC frequency sweep, which generates a Bode plot or frequencyresponse. Magnitude and phase (real or imaginary) data are produced.

14 Chapter Two

Simulation Types and Data Acquisition

All of the simulators have the ability to perform the following analyses:

DC Operating Point Analysis

DC Small-Signal Transfer Function

DC Sweep Analysis

Sensitivity Analysis

AC Analysis

Noise Analysis

Transient Analysis

Fourier Analysis

Monte Carlo Analysis

Temperature Analysis

The reference manual that accompanies each simulator provides suffi-cient information to perform any of the above analyses.

Convergence Problems

Convergence problems can be the most perplexing aspect in perform-ing a simulation (Sandler 2006). There is a methodology that comeswith experience. This section will provide a structured attack thatshould cure most convergence problems. The convergence suggestionsshould be performed in the order that they are listed. They are prior-itized so that the first few will be of the most benefit. Begin with theobvious.

These adjustments are based on the most commonly available.OPTIONS parameters and features in all of the simulators. Each sim-ulator has several more convergence-related parameters that can beadjusted. Please see the individual syntax manuals for your programfor more details on how to handle convergence problems.

Steps to avoid common mistakes

Verify that all circuit connections are valid, the component polarityis proper, and there is a DC path from every node to ground.

Verify that all components have the correct values (i.e., mega insteadof milli for 1E6). Components with no assigned value may be set toa default value determined by the simulator.

Verify that all model parameters are realistic, especially if the modelwas created or altered by you.

Verify that every node has two connections. Verify that voltage or current generators have the correct syntax and

appropriate values.


Use a series equivalent in place of capacitors or current sources thatare placed in series.

Verify that the letter O was not used in place of the number zero(0).

If behavioral expressions or elements are used in the circuit, verifythat division by zero cannot occur.

Verify that dependent source gains are correct.

DC convergence solutions

1. Set ITL1 = 500 in the .OPTIONS statement. This setting increasesthe number of iterations that SPICE will perform before generatinga nonconvergence warning and aborting the simulation.

2. Add .NODESETs. Voltages can be assigned to the nodes of the top-level schematic. The initial guess made by SPICE to determine theDC bias point incorporates the nodesets. This can greatly reducethe number of iterations required to converge. Improper nodesetscan result in inaccurate results or nonconvergence. Care should betaken in setting the .NODESET statements.

3. Use pulse statements to turn on DC power supplies.Example: V1 3 0 5 DC becomes V1 3 0 PULSE 0 5

This allows the user to turn on the power supplies. A rise time mayalso be used to provide a realistic turn-on.

4. Set GMIN in the .OPTIONS statement. Set GMIN = 1n or 0.1n.Larger values are not recommended. This sets the minimum con-ductance across all semiconductor devices.

5. Set RSHUNT in the .OPTIONS statement, if available. This optionplaces a resistor, with the value assigned globally by RSHUNT, fromevery node in the circuit to ground. A solution obtained using thisconvergence technique could be made at an incorrect operating point.The solution should be carefully examined.

6. Set ILT6 = 100 in the .OPTIONS statement. Source stepping de-creases all DC stimuli until a DC bias point is determined, or theyare reduced to 0 V. The voltages are then gradually stepped fromthe DC bias point that converged, which may be at ground, backto the assigned value. The source stepping algorithm uses gradualincreases in voltage, to establish a new DC bias point, taking theprevious DC bias point as the initial guess. This process continuesuntil a DC bias point has been established for the assigned values ofthe stimuli of the circuit.

16 Chapter Two

Transient convergence solutions

1. Verify that DC convergence has been achieved. View the error state-ments in the text editor to verify that the convergence problempertains exclusively to the transient simulation.

2. Verify that the time step provides an appropriate resolution. Thetime step must be small enough to provide appropriate resolutionof the switching waveforms generated by the simulation. The timestep should be assigned to an order of magnitude smaller than theshortest period in the simulation. For example, in a 100 kHz oscil-lator, the period is 10 s. The time step should be set to 1 s.

.TRAN 1u 3m

Other factors such as the on time or the duty cycle should be consid-ered when determining the time step. Once convergence has beenachieved, this value can be maximized to reduce simulation time.

3. For oscillating or switching circuits, set METHOD = GEAR in the.OPTIONS statement. This statement selects the type of integrationmethod that SPICE uses to solve the transient equations. Gear in-tegration should be used for all switching circuitry. The default in-tegration, trapezoidal, has a tendency to produce oscillations. Note:Gear integration is not available in all simulators.

4. Add UIC (Use Initial Conditions) to the .TRAN statement. Thisstatement causes SPICE to bypass the DC operating point anal-ysis. Initial conditions should be placed on capacitors at their ex-pected operating voltage. Just as with the use of incorrect nodesets,incorrect initial condition values can produce incorrect solutions ornonconvergence. Results should be verified for validity.

5. Set ITL4 = 500 in the .OPTIONS statement. This statement in-creases the number of iterations performed by SPICE, before anonconvergence warning is issued and the simulation is aborted.

6. Set RELTOL = .01 in the .OPTIONS statement. This statement de-creases the accuracy of the simulation by increasing the relativeerror tolerance required for convergence. This value should not beset lower than .01. The simulation run time is also reduced by in-creasing RELTOL. Remember as a general rule that every order ofdecrease in magnitude of the relative tolerance results in doublingthe simulation run time.

7. Reduce the rise and fall times of PULSE sources. Drastic changesin voltage can result in nonconvergence problems. Soften the edgesof the pulse source by increasing the rise time and fall time of thepulse waveform.


8. Set TRTOL = 40 in the .OPTIONS statement. This statement isproportional to the step size used when performing a transientsimulation. The accuracy of the simulation can be compromisedby changing TRTOL from the default setting of TRTOL = 7.

9. Reduce the accuracy of ABSTOL/VNTOL if current and/or volt-age levels permit. The default value of ABSTOL = 1pA, and VN-TOL = 1uV, should be set to about eight orders of magnitude belowthe level of the maximum current and voltage.

10. Set RAMPTIME = 10nSec in the .OPTIONS statement, if available.This statement ramps all independent sources up from zero at thebeginning of the transient analysis. The statement is beneficial ifthe transient analysis will not start. Take care to allow enough timefor sources to ramp up, otherwise this statement could do moreharm than good.

AC convergence solutions

1. Do not use steps 35 of the DC convergence solutions. Using thesesteps may not produce a valid DC operating point, which is essentialfor SPICE to linearize the circuit. See the AC analysis description.Once DC convergence is achieved, the AC analysis will also converge.

Convergence failures are not always a function of SPICE and there-fore cannot always be fixed using .OPTIONS statements or other con-vergence techniques. Convergence failures may result from hardwareproblems.

Bibliography

Kielkowski, Ron. 1995. Inside SPICE. New York: McGraw-Hill.Sandler, Steven M. 2006. Switch-Mode Power Supply Simulation with PSpice and

SPICE 3. New York: McGraw-Hill.

Chapter

3Filter Circuits

Filter circuits form the initial building block for many different systems.Communications circuits require only certain signal frequencies to bepassed on to transmitter and receiver circuits. Power converters use fil-ters on the input bus to filter out spurious noise and on the output lineto smooth the rectified signal. Digital logic circuits use bypass capaci-tors and RC networks to filter supply voltages that must travel somedistance before reaching the IC. Filters can provide the time delays re-quired in some circuits. Filter circuits are very important to these andmany other circuits because of the simple function they perform. Theyallow desirable signals to pass while blocking undesirable signals.

For most of the circuits, the transient response of the filter is matchedto hardware results. For a select few filters, a network analyzer is uti-lized to measure the frequency response of the filter.

Although filters perform a simple function, the circuits and designparameters used to design filters can be much more complex. Filterscan be optimized for a low Q in the pass band (Butterworth type) or ahigh attenuation in the stop band and steeper roll-off near the cut-offfrequency (Chebyshev type). Filters that are used primarily for delaysin circuitry might use the BesselThomson type of filter. The expansiveset of filter design types is matched by the wide range of filter designapplications that use them.

Fourth-Order Butterworth Low Pass Filter

The first filter in the chapter is one of the most popular. The schematicof the fourth-order Butterworth response low pass filter is shown inFig. 3.1. The frequency response of the filter to an AC sweep is shownin Fig. 3.2. Note the flat response in the pass band and the stop bandfrequency of 100 kHz.

19


20 Chapter Three

VCC

VEE

VCC

VEE

V4C2.01U

C3.005U

R120K

C4.01U

R220K

R320K

R420K

X4OPAMP

X5OPAMP

C1.005U

V_20

V_33 4

511

4

9

20

4 6

5 9

5

6

5

1

20

11

20

1

2

6

5 55

20 20

20

20 20

9

1

1

2

1

1

2

2

1111

Figure 3.1 Schematic of a fourth-order Butterworth low pass filter.

Unfortunately, the lab used in the creation of the circuits in this bookclosely resembles the lab of other engineering companies around theworld. We use 5% tolerance resistors and 10% tolerance capacitors thatare either soldered to a vector board or plugged into a solderless bread-board. This introduces various parasitics and inaccuracies in the re-sults. In order to be more precise in showing the accuracy of SPICEsimulation software, we frequently run the simulations with the statedvalues of the resistors or capacitors used in our lab breadboards. Themeasured values for each resistor and capacitor used in our breadboardconfiguration which may be different, are shown in Fig. 3.3.

In order to correlate the breadboard to the SPICE circuit, a 5 V pulsereplacements was applied with a rise time of 100 ns by using the fol-lowing command in a V source:

PULSE 0 5 750 U 100N

This command creates a delay of 750 s to allow the filter to be at steadystate when the pulse is applied. The step response of the breadboard

1

1K 10K 100K 1MEG

FREQUENCY in Hz

20.00

20.00

60.00

100.00

140.0

Gai

n in

dB

(V

olts

)

Figure 3.2 AC filter response.

Filter Circuits 21

R121.3K

R221.3K

C1.00512U

C2.0102U R3

21.3KR421.3K

C3.005U

C4.0102U

VCC

VEE

X4 OPAMP

VCC

VEE

X5 OPAMP

V4PULSE

0 -13.9 -4.10M

-13.9-13.9 -4.20M

-13.9

15.0

-15.0

3 64

59 11

20

1

2

Figure 3.3 Breadboard configuration of fourth-order Butterworth filter.

circuit is shown in Fig. 3.4a, while that of the IsSpice model is shownin Fig. 3.4b. The top trace is the 5 V pulse, while the bottom trace is thefilter response measured at the output of op-amp X5.

SPICE tip SPICE automatically precedes the AC and transient analyseswith two operating point analysis, one for AC and one for the transient.The operating point values are used to set the biasing for the AC analysisand the initial starting point for the transient analysis. For the AC analysisthe operating point analysis is often called the small signal bias solution.

Figure 3.4a Breadboard filter response to step input.

22 Chapter Three

1

750.0U 1.250M 1.750M 2.250M 2.750MTIME in Secs

8.000

6.000

4.000

2.000

0

V(2

0) in

Vol

ts10.000

0

10.000

20.00

30.00

V(3

) in

Vol

ts

2

Figure 3.4b IsSpice filter response to step input.

For the transient analysis the operating point is often called the initialtransient solution. They are different. In fact, depending on nodeset values,initial conditions, .OPTIONS settings, and so on, one operating point canfail while the other can succeed. The operating point analysis is critical togetting the right information out of the AC and transient analyses, and itmust converge if the subsequent analysis is to run.

The circuit was also simulated on Micro-Cap and PSpice. The Micro-Cap results are shown in Figs. 3.5a and 3.5b, while the PSpice resultsare shown in Figs. 3.6a and 3.6b.

Figure 3.5a Micro-Cap AC filter response.

Filter Circuits 23

Figure 3.5b Micro-Cap filter response to a step input.

Simulation tip Note that in the results of the Micro-Cap voltage step response simula-

tion, the magnitude of the output voltage was incorrect. The reason forthis is unknown; however, the lesson here is that you must know the lim-itations of your models. Many times, these libraries can be provided byIC manufacturers or the SPICE software company. It is very importantto remember that these models may not be accurate for the operatingrange or temperature settings you are interested in. People often makedifferent models to represent different aspects of the parts operation,rather than one all encompassing model. In most cases, the model ex-hibits only a subset of the actual device performance characteristics, al-beit, hopefully the most important ones. For example, some models may

Figure 3.6a PSpice AC filter response.

24 Chapter Three

Figure 3.6b PSpice filter response to a step input.

have noise rejection modeled accurately, or AC characteristics, or inputcurrent draw, whereas some may not model any of these. If the modeldoes not accurately reflect the characteristic you are interested in, thenthis does not necessarily mean the model is useless or wrong (althoughthis is a possibility).

Run time summary (s)

IsSpice v 8.11 PSpice v 10.5 Micro-Cap v8.07.25 5.02 13.734

Advantages: Moderate parts count, flat response in the pass bandDisadvantages: Filter Q greater than that of other filter types

File names: lp fltr (IsSpice), lp fltr (PSpice), lpflt (Micro-Cap)

Fourth-Order Butterworth High Pass Filter

A quick modification to the circuit in Fig. 3.1 produces a high pass filterresponse. The schematic for the high pass filter is shown in Fig. 3.7,and its AC response is shown in Fig. 3.8.

The same pulse as in the low pass filter was applied to the highpass filter. The breadboard results are shown in Fig. 3.9. These may becompared with the IsSpice results shown in Fig. 3.10. The top trace isthe 5 V pulse, while the bottom trace is the filter response measured atthe output of op-amp X6.

This circuit was also simulated using Micro-Cap and PSpice. Theresults of these simulations are shown below (Figs. 3.11 to 3.14).

R221.3K

C1 .005UC2 .01U

VCC

VEE

X4 OPAMP

R121.3K

R521.3K

C5 .005UC6 .01U

V(11)OUT

VCC

VEE

X6 OPAMP

R621.3K

V(4)IN

5 64

31

2

10 9

11

-9.99M -11.0M0

-9.99M15.0

-15.0

-9.99M -11.0M

-9.99M

Figure 3.7 Schematic of fourth-order Butterworth high pass filter.

1

1K 10K 100K

FREQUENCY in Hz

40.00

0

40.00

80.00

120.0

todB

of O

UT

in d

B (

Vol

ts)




Advantages: Moderate parts count, flat response in the pass bandDisadvantages: Filter Q greater than that of other filter types

File names: hp fltr (IsSpice), hp flt (PSpice), hpflt (Micro-Cap)

Fourth-Order Butterworth Band Pass Filter

The schematic in Fig. 3.15 shows the configuration for a Butterworthband pass filter. The AC characteristic of the filter is shown in Fig. 3.16.

25

26 Chapter Three

Figure 3.9 Breadboard filter response to a step input.

The breadboard circuit was pulsed with a 5 V step. The response ofthe band pass filter to the step input is shown in Fig. 3.17. The toptrace is the input step, and the bottom trace is the filter response at theoutput of X5. The IsSpice circuit response to the step input is shown inFig. 3.18.

This circuit was also simulated using PSpice and Micro-Cap. Theresults of these simulations are shown below (Figs. 3.19 to 3.22).

1

2

500.0U 1.000M 1.500M 2.000M 2.500M

TIME in Secs

5.000

5.000

15.00

25.00

35.00

IN in

Vol

ts

7.000

5.000

3.000

1.000

1.000

OU

T in

Vol

ts

Figure 3.10 IsSpice filter response to a step input.

Filter Circuits 27

Figure 3.11 PSpice AC filter response.

Figure 3.12 PSpice filter response to a step input.



Advantages: Moderate parts countDisadvantages: Filter Q greater than that of other filter types

File names: bp fltr (IsSpice), bp flt (PSpice), bpflt (Micro-Cap)

BesselThompson Delay Low Pass Filter

The primary purpose of this filter is to add a delay to a pulse or datasequence. The use of the RC time constant allows this delay to be addedto both the rising and the falling edge of the pulse. The ideal response

Figure 3.13 Micro-Cap AC filter response.

Figure 3.14 Micro-Cap filter response to a step input.

R1 20K

R240K C1

.005U

C2 .01U

R3 20K

R440KC3

.005U

C4 .01U

V(20)OUT

V(3)IN

VCC

VEE

X4 OPAMP

VCC

VEE

X5 OPAMP

V4AC

R520K

R620K

4 63

5

9 10

20

1

2

Figure 3.15 Schematic of a fourth-order Butterworth band pass filter.

28

1

100 1K 10K

FREQUENCY in Hz

0

20.00

40.00

60.00

80.00

todB

of O

UT

in d

B (

Vol

ts)



2

1

750.0U 1.750M 2.750M 3.750M 4.750MTIME in Secs

1.000

600.0M

200.0M

-200.0M

-600.0M

OU

T in

Vol

ts

5.000

5.000

15.00

25.00

35.00

IN in

Vol

ts


29

30 Chapter Three


of the filter is a perfect reproduction of the input delayed by a spec-ified time constant. The time delay of the BesselThompson filter ismeasured by the time for which the pulse occurs until the time theresponse is 50% of the input step height.

A BesselThompson filter was designed to have a delay close to 500s. The design procedure followed gave exact values for all of the ca-pacitors and resistors. These values are rounded to the nearest value ofcapacitor available. The SPICE packages are used to determine whatthe implemented delay will be. Measured values of all the componentsused in the hardware are used. The schematic and the breadboard re-sults are shown as Figs. 3.23 and 3.24, respectively.


Filter Circuits 31


IsSpice had an LM124 model in its library. The simulation responseto a step input is shown in Fig. 3.25, and the AC simulation results areshown in Fig. 3.26.

PSpice has a model for LM324, but the the UA741 op-amp model wasused in its place. The operation amplifier does not play a critical rolein this circuit because of its slow response. The limiting parameter ofthe delay time is the RC time constant and not the slew rate or drivecapability of the operational amplifier. The PSpice model response toa step input is shown in Fig. 3.27, and the AC results are shown inFig. 3.28.

Micro-Cap also had an LM124 model. The model response to a stepinput is shown as Fig. 3.29, and the AC results are shown as Fig. 3.30.


32 Chapter Three

VCC

VEE

VCC

VEE

V5

C331N

R12.16K

V6

C4103N

R22.16K

C569N

R32.16K

R42.16K

X1LM124N

X2LM124N

V1

V2

V3

C169N V_25

V_3

V_4

10

7

3 811

4 1

8 2

8 5

5 44 7

2

512

6

5 7

110

11

1

3

12

62

5

55 5

5

5

558

8 2 2

88

1

11 1

1

1

114

4 7 7

44

1

3

4

1

1

5

5

Figure 3.23 BesselThompson delay filter.




Advantages: Adds controlled delay to a given signal with moderate parts countDisadvantages: Rounds off signal and places importance on detection device

File names: bessel (IsSpice), bes ps (PSpice), besmc5 (Micro-Cap)

Filter Circuits 33

BesselThompson Delay Low Pass Filterwith Pulse Shaper

A simple pulse-shaping modification can be added to the BesselThompson delay filter by using an additional operational amplifier.Resistors are used to divide down the supply voltage to half the outputvoltage of the delay filter, and its response is then compared with thedelay filters response, which results in a time-delayed square wave.The schematic of this circuit is shown in Fig. 3.31. This simulationalso allows us to compare the operational amplifier models that camewith each software package. The response of this circuit is driven fromrail to rail, providing the saturation voltages of the models. Also, theslew rate of the output should be consistent with the measured and

100.00U2.423M

519.6U1.000

1

100.00U 300.0U 500.0U 700.0U 900.0UTIME in Secs

4.000

3.000

2.000

1.000

0

2.000

1.000

0

1.000

2.000

INP

UT

in V

olts

2

BE

SS

ELO

UT

in V

olts


1

100 1K 10K 100K

WFM.1 BESSELOUT vs. FREQUENCY in Hz

40.00

0

40.00

80.00

120.0

todB

of B

ES

SE

LOU

T in

dB

(V

olts

)

Figure 3.26 IsSpice AC filter response.




34

Filter Circuits 35


published data. Keep in mind that these parameters may not be con-sistent between brands and between lots, but they should be consistentwith the average data from the manufacturer.

The parameters that will be measured in each of the softwarepackages and the hardware are the minimum and maximum volt-ages, the rise and fall time of the output, and the effective pulsewidth. The response of the IsSpice model is shown as Fig. 3.32.Micro-Cap results are shown as Fig. 3.33. PSpice results are dis-played in Fig. 3.34, and the hardware measurements are shown asFig. 3.35.

R12.16K

R22.16K

C169N

VCC

VEEX1LM124N1

ULSE

V210

V3-10

R32.16K

R42.16K

C331N

C4103N

VCC

VEEX2LM124N

V510

V6-10

C569N

R1011.93K

R1199.8K

V1310

VCC

VEE

V14-10

3 8 2

512

6

14

47

10

11 13

27

1

15

Figure 3.31 BesselThompson delay filter with shape reformation.

553.0U10.49U

1.443M-3.878U

1

200.0U 600.0U 1.000M 1.400M 1.800M

TIME in Secs

20.00

10.000

0

10.000

20.00

Pul

se s

hapi

ng r

espo

nse

in v

olts

x = 890.4U y= 0

Figure 3.32 IsSpice simulation results. Note: Vout(max) = 8.4 V,Vout(min) = 10.7 V, rise time = 53.3 s, fall time = 53.3 s,pulse width = 890 s.

Figure 3.33 Micro-Cap simulation results. Note: Vout(max) = 7.4 V,Vout(min) = 10.7 s, rise time = 49 s, fall time = 52 s, pulsewidth = 833 s.

Figure 3.34 PSpice simulation results. Note: Vout(max) = 9.08 V,Vout(min) = 10.47 V, rise time = 84 s, fall time = 71 s, pulsewidth = 851 s.

36

Filter Circuits 37

Figure 3.35 Breadboard data. Note: Vout(max) = 9.1 V, Vout(min) = 10 V,rise time = 49 s, fall time = 50 s, pulse width = 780 s.



Advantages: Moderate part count, pulse delay and reshaperDisadvantages: May require additional voltage source and op-amp package to reshapevoltage to a specification

File names: bess shap (IsSpice), bes shap (PSpice), bes lpshap (Micro-Cap)

Inverted BesselThompson DelayHigh Pass Filter

A quick modification to the BesselThompson filter leaves us with ahigh pass filter. This filter does not have the built-in delay like the lowpass version, but it does provide an interesting response. The schematicand the breadboard results are shown in Fig. 3.36 and Fig. 3.37, respec-tively. The measurements that will be made for comparison purposesare the step response height and the time until the second cross of thezero axis.

For each filter, an AC analysis was run for comparison between thedifferent software packages. These results are displayed along with thestep response from each of the filters. The results of the IsSpice modelare displayed in Figs. 3.38 and 3.39. The PSpice results are shown inFigs. 3.40 and 3.41. The results from the Micro-Cap model are shownin Figs. 3.42 and 3.43.

38 Chapter Three

R15.56K

R24.65K

C110.28N

VCC

VEEX1LM124N

V110

V2-10

R38.21K

R43.24K

C210.5N

C310.25N

VCC

VEEX2LM124N

V310

V4-10

C410N

5

ULSE

2

34

5

6

7

8

9

10

11

12

Figure 3.36 High pass filter inverse BesselThompson.

Figure 3.37 Breadboard results of step response.



Advantages: Moderate parts countDisadvantages: Underdamped response

File names: hpbessel (IsSpice), bess hp (PSpice), bes mic5 (Micro-Cap)

Filter Circuits 39

Chebyshev Band Pass Filter

The Chebyshev filter response offers higher attenuation and a steeperroll-off near the cutoff frequency than the Butterworth filter response.There is a tradeoff to achieve the higher attenuation. The cost of utiliz-ing a Chebyshev filter is higher values of Q, which leads to difficulties inhardware realization, and nonlinear phase characteristics, which canresult in difficulties in predicting circuit performance. The followingMathCAD file was used to design a Chebyshev band pass filter withunity gain in the pass band. The filter is comprised of two identicalcascaded stages.

1

100.00U 300.0U 500.0U 700.0U 900.0U

TIME in Secs

2.500

1.500

500.0M

500.0M

1.500

Res

pons

e in

Vol

ts

Figure 3.38 IsSpice step response results.

1

100 1K 10K 100KFREQUENCY in Hz

50.00

50.00

150.0

250.0

350.0

Gai

n in

dB

(V

olts

)

50.00

50.00

150.0

250.0

350.0

VP

(7)

in D

eg

2

Figure 3.39 IsSpice AC filter response.

Figure 3.40 PSpice step response results.


Figure 3.42 Micro-Cap step response results.

40

Filter Circuits 41


Design specifications in rad/s, where rad/s = 2 Hz:2 := 2950 2 max := 0.5 3 := 1500 24 := 3500 2 1 := 2050 2 min := 22

02 = 12

0 := 12 0 = 1.545 104

0freq := 02 0freq = 2.459 103

BW := 2 1 BW = 5.655 103

qc = 0BWqc := 0

2 1 qc = 2.732

s := 4 32 1 s = 2.222

p := [

(22) + 022(2 1)

]p = 1

max := 10

ln

cosh

(n acosh

(s

p

))2+ 10

1

10 min

1

cosh(

n acosh(

s

p

))2

ln(10)

42 Chapter Three

max = 0.5

min := 10

ln

cosh

(n acosh

(s

p

))2 10

1

10 max

+ 1 cosh(

n acosh(

s

p

))2ln(10)

max = 22

n :=

acosh

10

min

10 1

10

max

10 1

12

acosh(

s

p

)

n = 2.975

Round up to an integer.ceil(n) = 3n := ceil(n)

:=

1802n

ifn2

= floor(n

2

)180

notherwise

= 60 :=

180 = 1.0 := (10 max10 1) 12 = 0.349The pole locations are now determined:qc = 2.732a := 1

n asinh

(1

)a = 0.59138

Real Poles:For = 0; n odds := |sinh(a)| s = 0.626

Complex Poles:For = (, +/ 2, +/ 3 . . .)k := | sinh (a) cos()| k = 0.3k := | cosh (a) sin()| k = 1.0

Filter Circuits 43

The half-power (3 dB) frequency is determined by

hp := cosh(

1ceil(n)

acosh(

1

))hp = 1.1

:= |k| = 0.3 := |k| = 1.0C := 2 + 2 C = 1.1D := 2

qcD = 0.229

E := 4 + Cqc2

E = 4.153

G := E2 4D2 G = 4.128

Q := 1D

12

(E + G) Q = 8.875

K := Qqc

K = 1.01739

W := K + K2 1 W = 1.2046902 := W0 02 = 1.861 104

Qo := qcs

Qo = 4.362

01 := 1W 0 01 = 1.283 104

Set all values of capacitors to be equal:

C := 107

Km1 := 12 QC01 Km1 = 43.924

Km2 := 12 QoC0 Km2 = 74.19

Km3 := 12 QC02 Km3 = 30.266

Stage 1:

R1 := (T1) Km1 R1 = 1.99

R2 := 11 1T1

Km1 R2 = 44.

R3 := 4 Q2Km1 R3 = 1.3

44 Chapter Three

Stage 2:

R4 := T2 Km2 R4 = 2.8

R5 := 11 1T2

Km2 R5 = 76

R6 := 4Qo2Km2 R6 = 5.6

Stage 3:

R7 := (T3) Km3 R7 = 1.3

R8 := 11 1T3

Km3 R8 = 30.948

R9 := 4Q2Km3 R9 = 9.536 103

The schematic in Fig. 3.44 of the Chebyshev band pass filter utilizedthe predicted values from the MathCAD file, where lab resourcesallowed. Close approximations were used, to which the circuit per-formance was extremely sensitive. Any deviations from the valuespredicted in the MathCAD file resulted in gain in the pass band. UsingSPICE to test possible circuit realizations greatly reduces the time toimplement hardware. SPICE will predict if a given circuit realizationwill perform as desired with available parts, before actual hardwaremeasurements are made. This is helpful because Chebyshev circuitrealization can be difficult: small changes in the circuit elements can re-sult in undesired performance. The simulated AC results from IsSpice,PSpice, and Micro-Cap are shown in Figs. 3.45, 3.46, and 3.47, respec-tively. The measured breadboard AC response of the filter is shown

V(5)VCC

V(9)VEE

R1013.68K

C7.1U

C8.1U

R1143.1

R121.99K

R135.644K

C9.1U

C10.1U

R1476.7

R152.88K

V(9)VEE

V(5)VCC R16

9.77K

C11.1U

C12.1U

R1729.5

R181.374K

V(9)VEE

V(5)VCCVCC

VEE VCC

VEE VCC

VEE

5

9

1

6

1114

15

16

17

18

19

22

Figure 3.44 Chebyshev band pass filter.

2.445K183.6M

200 500 1K 2K 5K 10K 20K 50K

FREQUENCY in Hz

0

20.00

40.00

60.00

80.00

GN

IA n

i Vst

ol

.881 dB Maximum x = 97.55K y = -120.2

Figure 3.45 IsSpice-simulated Chebyshev band pass filter response.

Figure 3.46 PSpice-simulated Chebyshev band pass response.

Figure 3.47 Micro-Cap simulated Chebyshev band pass response.

45

46 Chapter Three

TABLE 3.1 Summary of Results

Condition Hardware Micro-Cap IsSpice PSpice

Center frequency (kHz) 2.45 2.42 2.4 2.44Maximum attenuation (dB) 0 0.316 0.44 0.886File name NA BP Cheby1 BP n2Run time AC analysis (s) NA 2.422 3.083 4.67

For more accuracy, increase the number of points per division.

in Fig. 3.48, and the measured transient response in shown Fig. 3.49.The simulated transient response is shown in Figs. 3.50 and 3.52. Allof the simulators correlated well to the hardware.

Chebyshev Low Pass Filter

The Chebyshev low pass filter shown in Fig. 3.53 was constructed inall three simulators as well as in hardware. The circuit values in Fig.3.53 were used in all cases. A MathCAD file that was used to designthe Chebyshev low pass filter is located in the Chebyshev directory ofthe CD, which accompanies this book. This file can easily be modifiedto accommodate designs that use a SallenKey circuit for each stageof the filter (see Fig. 3.54). The schematic of the circuit that was usedin each simulator is shown in Fig. 3.53. The measured breadboard re-sults are shown in Fig. 3.55, and the simulated results are shown inFigs. 3.56, 3.57, and 3.58.

Figure 3.48 Measured Chebyshev band pass filter response.

Filter Circuits 47

Figure 3.49 2500 Hz square-wave input, and sine-wave output.

1

6.325M3.234

6.525M-3.227

2

6.138M 6.338M 6.538M 6.738M 6.938MWFM.2 OUTPUT vs. TIME in Secs

12.00

8.000

4.000

0

-4.000

OU

TP

UT

in V

olts

6.000

2.000

2.000

6.000

10.000

INP

UT

in V

olts

x = 200.0U y = -6.461

Figure 3.50 IsSpice 2500 Hz square-wave input, and sine-wave output.

Figure 3.51 Micro-Cap 2500 Hz square-wave input, and sine-wave output.

Figure 3.52 PSpice 2500 Hz square-wave input, and sine-wave output.

VCC

VEE

VCC

VEE

VCC

VEE

R11.469K

C195N

R21.467K

R31.478K

C321N

R41.467K

R51.467K

C54.4N

C2.104U C4

.3U

V215

V315

V(3)VEE

V(3)VEE

V(3)VEE

V(8)VCC

V(8)VCC

V(8)VCC

V(8)VCC

5

28

3

7

11

12

1

4

6

10

Figure 3.53 Chebyshev low pass filter.

48

VCC

VEE

1/2Q

11

V21VIN

Vout

2Q

Sallen-Key Circuit

5

4

2

61

Figure 3.54 SallenKey circuit.

Figure 3.55 Chebyshev low pass filter, measured data.

Figure 3.56 PSpice Chebyshev low pass filter results.

49

50 Chapter Three

2.700K2.180

1

2K 3K 4K 5K 6K 7K 8K 9K

FREQUENCY in Hz

0

20.00

40.00

60.00

80.00

GA

IN in

Vol

ts

x = 16.98K y = -97.98

Figure 3.57 IsSpice Chebyshev low pass filter results.

Figure 3.58 Micro-Cap Chebyshev low pass filter results.

C1.1U

R32.35K

VCC

VEE

C3.1U

C4.1U

R646.5K

R71.32K

V2AC

V315

V415

V(6)VCC

V(8)VEE

V(6)VCC

V(5)OUT

VCC

VEE

V(6)VCC

4 10

7

56

83 2

Figure 3.59 Chebyshev high pass filter.

Filter Circuits 51

Figure 3.60 Chebyshev high pass filter measured results.

Figure 3.61 Chebyshev high pass filter measured results.

TABLE 3.2 SPICE Statistics

Simulator File name Maximum attenuation Run time (s)

Hardware NA 2.03 dB at 2.76 kHz NAPSpice Lp 2 2.22 dB at 2.75 kHz 1Micro-Cap Lp 2.13 dB at 2.67 kHz 0.329IsSpice Lp n5 2.18 dB at 2.70 kHz 0.333

52 Chapter Three

1

2

20 50 100 200 500 1K 2K 5K FREQUENCY in Hz

0

100.00

200.0

300.0

400.0

PH

AS

E in

Deg

0

20.00

40.00

60.00

80.00

GA

IN in

Vol

ts

Figure 3.62 IsSpice Chebyshev high pass filter.

Chebyshev High Pass Filter

The Chebyshev filter offers higher attenuation and a steeper roll-offnear the cutoff frequency than the Butterworth filter. There is a trade-off to achieve the higher attenuation. The cost of utilizing a Cheby-shev filter is higher values of Q, which leads to difficulties in hardwarerealization, and nonlinear phase characteristics, which can result indifficulties in predicting circuit performance.

A Chebyshev high pass filter was constructed with the componentvalues shown in the schematic in Fig. 3.59. The measured results areshown in Figs. 3.60 and 3.61.

The results from the three simulators are shown in Figs. 3.62, 3.63,3.64, and 3.65. All of the simulators accurately predict the phase andgain of the Chebyshev high pass circuit.

Electromagnetic Interference (EMI) Filter

The last filter that will be looked at in this chapter is the EMI filter.This filter is commonly used on the input of a power circuit to reduceconducted and reflected emissions. For instance, a flyback convertercan draw current from the bus that looks like a sawtooth waveform with

TABLE 3.3 Spice Statistics

Simulator File name Run time (s)

PSpice hp 2 1Micro-Cap hp 0.375IsSpice hp n2 0.233

1

100 1K 10K 100K

FREQUENCY in Hz

0

20.00

40.00

60.00

80.00

GA

IN in

Vol

ts

Figure 3.63 IsSpice Chebyshev high pass filter.

Figure 3.64 PSpice Chebyshev high pass filter.

Figure 3.65 Micro-Cap Chebyshev high pass filter.

53

C110U;13.4

C269U;60.2

R13.7

R2 10KR3 .28 L1 417U

R4.4

1

5 4

23 6

Figure 3.66 EMI filter model (linear).

1.585K11.65

1

200 500 1K 2K 5K 10K 20K 50K

FREQUENCY in Hz

20.00

10.000

0

10.000

20.00

Out

put I

mpe

danc

e in

dB

(V

atts

)

x = 98.42K y = -19.86

Figure 3.67 IsSpice nonlinear core results of output impedance.

Figure 3.68 Measured results of filter output impedance.

54

Filter Circuits 55

a peak amplitude that is dependent on the load. An EMI filter can bedesigned to smooth these large spikes down to where they are nearlyinvisible to the bus. The EMI filter presented in this chapter is designedfor the flyback topology that converts as low as a 10 V input to a 5 Voutput.

They are several concerns when designing an EMI filter. The param-eters of the EMI filter examined in this book reflect these concerns.If the EMI filter is to be used on a converter, the input impedanceof the converter must be greater than the output impedance of thefilter at all frequencies. It is good practice to allow 6 dB of margin forthis parameter. If the output impedance of the filter gets too close tothe input impedance of the converter, there can be problems with thestability of the converter. It may be important to note here that thisoutput impedance is sensitive to the effective series resistance (ESR) ofthe output capacitors. For the hardware data taken for this unit, tan-talum capacitors, which have unspecified ESR, were used. The ESR ofa similar capacitor was measured for the simulations.

Other important characteristics of the converter are the reflected rip-ple attenuation and the turn-on characteristics. It is expected that theturn-on characteristics will be difficult to simulate because of the non-linear characteristics of a saturating core. A nonsaturating core is sim-ply described by Faradays law, and it can be easily modeled by anyof the SPICE simulators. The model used for the EMI filter is shownin Fig. 3.66, and the results of each of the simulators output and themeasured impedance plots are shown in Figs. 3.67 to 3.70.

Figure 3.69 PSpice filter output impedance results.

56 Chapter Three

Figure 3.70 Micro-Cap filter output impedance results.

The inrush current of an EMI filter is usually examined to ensurethat no parts are overstressed during power-up. If the inductor doesnot saturate, the inrush current is described by Faradays law and caneasily be modeled by mathematics or a simple SPICE model. It is alsonot too difficult to determine if a core is saturated during turn-on. Aslightly more difficult calculation is to determine what the maximumcurrent will be under a given turn-on condition. The hardware usedfor measurements used a transformer made of two stacked 55025 cores

C110U;13.4

C269U;60.2

R23.7

R410000

R5.4

9

3 4

1 8

5 6

7

Figure 3.71 IsSpice nonlinear core model.

Filter Circuits 57

35.00U22.33

1

50.00U 150.0U 250.0U 350.0U 450.0UTIME in Secs

30.00

20.00

10.000

0

10.000

Inru

sh C

urre

nt in

Am

ps

x = 465.0U y = 20.98

Figure 3.72 IsSpice results of nonlinear model for inrush current simulation.

Figure 3.73 Measured results of inrush current.

58 Chapter Three

1

4.730M 4.740M 4.750M 4.760M 4.770M TIME in Secs

3.000

2.000

1.000

0

1.000

2

3.000

2.000

1.000

0

1.000

Out

put c

urre

nt in

Am

ps

Inpu

t Cur

rent

in A

mps

Figure 3.74 IsSpice attenuation results (nonlinear model).

with 40 turns around them. This was modeled in IsSpice, as shown inFig. 3.71.

Note that a current probe was used to measure the inrush current(Figs. 3.72 and 3.73). It was set on 10 mA/mV, which means that theplot above the yaxis settings are in 5 A/div. It was only measured forFig. 3.73, and it is 5A/div for the y scale.

This filter was designed to have an attenuation of 60 dB. The atten-uation is calculated as 20log(Iout/Iin). Figure 3.74 shows the inputversus output current waveforms to demonstrate the lowest reportedattenuation.

TABLE 3.4 Comparison of Results

IsSpice IsSpice Micro- HardwareParameter Conditions (nonsaturating) (saturating) PSpice Cap data

Outputimpedance(dB)

11.74 11.65 11.71 11.7 11.1

Maximuminrushcurrent (A)

Turn-on 6.17 22.33 6.11 6.16 23.6

Attenuation(dB)

f = 170 kHzIout = 2.5 A(max) Dutycycle = 50%

56.7 46.7 58.2 58.4 59.3

Filter Circuits 59

Note the saturating core model is available in both PSpice andIsSpice. In PSpice the core is available as part of the AEi Systems PowerIC Model Library for PSpice. This figure is shown to give a visual rep-resentation of the effects of an EMI filter.



Advantages: Attenuates noise on bus for power converters.Disadvantages: Requires an inductor that is physically a large and expensive part.

File names: Filter (IsSpice), non emi (IsSpice), PS emi (PSpice), MC5EMI (Micro-Cap)

Bibliography

Parker, Sybil, ed. 1984. Concise Encyclopedia of Science and Technology. New York:McGraw-Hill.

Van Valkenburg, M. E. 1982. Analog Filter Design. New York: Harcort Brace JovanovichCollege Publishers.

Chapter

4Power Conversion Circuits

Power converter circuits are often the most overlooked aspect of a sys-tem. During the engineering phase, power is not a concern. There areplenty of bench power supplies scattered around the laboratory for usein breadboarding. Even in SPICE, the trusty voltage source elementprovides infinite voltage and infinite current for new circuit designs.

Unfortunately, when the time comes to put the system together, with-out circuits to condition the power to the system, the system is of littleuse to anyone. Operational amplifiers frequently need positive and neg-ative DC voltages to operate correctly and amplifiers need both AC andDC voltages, sometimes at high currents, in order to perform their func-tions. Window comparators and precision sensors need highly accurateAC and DC voltages for the circuit to succeed in its mission. What willpower the system when the bench supplies are gone?

Luckily, there are circuits that fill all of the power requirements listedabove and more. SPICE can be an indispensable tool for designing,troubleshooting, and characterizing power conversion circuits.

A simple definition of a power conversion circuit is a circuit that con-verts a power source of a certain characteristic (e.g., 110 V AC batteryvoltage, spacecraft bus) into a power source with a more desirable char-acteristic (e.g., regulated +5V DC for digital logic, constant currentsources). A wide variety of these circuits are presented in this chapter.

LM117 Three-Terminal Linear Regulator

Three-terminal linear regulator devices have been popular for sometime. The combination of simplicity, small package, good regulation,versatility, and reasonable price is attractive to engineers looking tooptimize designs. When examining the operation of a three-terminal

61


62 Chapter Four

IN OUT

ADJUST

VIN22

+

C410 uF

R1270

R23.3K

+RLOAD3.3K

C_COMPTBD

C_Load

1 uF

LM 1171

2

3

Figure 4.1 Typical application for an LM117 three-terminal linearregulator.

regulator, simulation may not make much sense. An input voltagebegets a regulated output voltage. Why simulate this? The answer isexplained below.

The following circuit (Fig. 4.1) is a typical application configurationfor an LM117 circuit. The input voltage is 22 V DC. Resistors R1 andR2 set the regulated output voltage at 16.7 V.

One interesting measurement that can be made on this circuit wouldbe the stability. In order to measure the stability in the lab, a specialtest configuration is used. This test set up is shown in Fig. 4.2. Theinjection signal must be kept very small (700 V is suggested), and themeasurement probes should be placed at R and A on the diagram in

IN OUT

ADJUST

V422

+

C410 uF

R8270

R93.3K

+R103.3K

C3TBD

C_Load

1 uF

LM 117

R_INJ 6.8

Oscillator

RA

4

7

5

6

98

Figure 4.2 Stability measurement setup for three-terminal regulator.

Power Conversion Circuits 63

LOL

10

COL10

C410u

R1ESR210m

R37.1

R1268

R23.24K

RESR1100MC_COMP

10u

CLOAD1U

V1

AC =TRAN =

DC = 22

VINJAC = 1

TRAN =DC =

v out

0

0

0

I25mdc

U1LM317TI1 1

2

233

V

Figure 4.3 SPICE stability measurement setup for three-terminal regulators.

Fig. 4.2, as shown, with the ground referenced to the output (makesure the power supply in not tied to earth ground).

Using the test setup of Fig. 4.2, several configurations were measuredin the lab. The cases will be considered one at a time, with comparisonsto the SPICE results in each case. The first case is the recommendedoperational use by the Linear Databook (Linear Technology R 1990, pp.4137), which recommends a 1 F tantalum input bypass capacitor, a1 F capacitor at the output, and a 10 F capacitor at the adjustmentpin. The recommended type of capacitor is a solid tantalum. The SPICEconfiguration for testing stability is shown in Fig. 4.3.

The resulting breadboard measurement is shown in Fig. 4.4. TheIsSpice result for the same test configuration is shown in Fig. 4.5.

1-28-98V

IN = 22.1V

VO = 16.67V

Ccomp = 1 F MMCcomp = 10 F MM

Figure 4.4 Breadboard Bode plot (C Comp = 10 F).

64 Chapter Four

1

1K 10K 100K

FREQUENCY in Hz

40.00

20.00

0

-20.00

-40.00

Gai

n in

dB

(V

olts

)

420.0

300.0

180.0

60.00

-60.00

Pha

se in

Deg

2

Figure 4.5 IsSpice Bode plot (C Comp = 10 F).

Comparing the results of Figs. 4.4 and 4.5, it was found that thephase margin is 21.4 in the breadboard plot and 15.85 in the IsSpiceplot. The crossover in the breadboard plot was 27.7 kHz, compared with53.7 kHz in the IsSpice plot. The general shapes of the curves are alsovery similar.

SPICE tip There are three models of LM117 in the Intusoft model library.One model gave the correct DC output voltage and the correct Bode re-sponse. One gave an incorrect DC output voltage but the correct Boderesponse, and one did not converge. Surprisingly, all three models aretransistor level. This is just another example of the necessity of testingpreviously unused models against their data sheet performance in orderto ensure model accuracy. Incidentally, the model used in these simulationsis the LM317TI model.

The LM117 configuration was also tested without a C COMP capaci-tor. The breadboard results are shown in Fig. 4.6, and the IsSpice resultsare shown in Fig. 4.7.

The breadboard phase margin and crossover frequency are 7 and7.4 kHz, respectively. The SPICE simulation phase margin andcrossover frequency are 1.7 and 14.7 kHz, respectively. Good engineer-ing practice suggests a minimum phase margin of 45. The final con-figuration approaches this value. The C COMP capacitor is changed to4700 pF. The breadboard measurements are shown in Fig. 4.8, whilethe IsSpice results are shown in Fig. 4.9.

Power Conversion Circuits 65

1-28-98V

IN = 22.1V

VO = 16.67V

Ccomp = 1 F MMCcomp = Open

Figure 4.6 Breadboard Bode plot (C Comp = open).

The breadboard phase margin and crossover frequency are 41.7 and8.3 kHz, respectively. The IsSpice simulation results show a phasemargin of 44.6 and an 11 kHz crossover. Examining the results ofthe testing and simulation, we can conclude that there is an opti-mal value of the C COMP capacitor that maximizes phase margin and

2

1

1K 10K 100KFREQUENCY in Hz

40.00

20.00

0

20.00

40.00

Gai

n in

dB

(V

olts

)

420.0

300.0

180.0

60.00

60.00

Pha

se in

Deg

Figure 4.7 IsSpice Bode plot (C Comp = open).

66 Chapter Four

OdB

Odeg

1-28-98V

IN = 22.1V

VO = 16.66V

Ccomp = 1 F MMCcomp = 4700 pF

Figure 4.8 Breadboard Bode plot (C Comp = 4700 pF).

creates an optimally stable three-terminal regulator. An excellent toolfor determining this optimal capacitance is SPICE.

SPICE tip The optimizer function of the SPICE simulators is tailor madefor this problem. The optimization feature can be performed in Micro-Cap by using the STEPPING feature in the AC menu, and in PSpiceby using the PARAMETRIC sweep in

spice circuit handbook

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