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The Influence of Calibration Pattern Coverage for Lumped Parameter Resist Models on OPC Convergence Martin Niehoff a , Shumay Shang b , Olivier Toublan c a Mentor Graphics, Muenchen, Germany b Mentor Graphics, San Jose, USA c Mentor Graphics, Grenoble, France ABSTRACT Besides models describing the exposure tool optical system, lumped parameter resist models are the other important model used during OPC. This combination is able to deliver the speed and accuracy required during OPC. Lumped parameter resist models are created by fitting a polynomial to empirical data. The parameters of this polynomial are usually image parameters (maximum and minimum intensity, slope, curvature) taken from the optical simulation for each measured structure. During calibration of such models, it is very important to pay attention to the parameter space covered by the calibration pattern used. We analyze parameter space coverage for standard calibration patterns, real layout situation post OPC correction as well as pre OPC correction. Taking this one step further, the influence of parameter space coverage during model calibration on OPC convergence is also studied. Keywords: VT5, parameter space coverage, OPC, lumped parameter resist model. INTRODUCTION Lithography process modeling for OPC is usually divided into two steps: First, physically based models are used to predict the influence of optical imaging on patterning. Ideally, those models yield an accurate prediction of the aerial image as it is created in the actual exposure system. Figure 1 shows a piece of layout and the result of the aerial image simulation of that layout. opticalsystem 0.193 0.650 magnification 4. hoodpix 2.56 kerngrid 0.005 illumtype COMPOSITE ANN sigma 0.855 sigma_in 0.533 film 0.19 1.696 -0.022 “Resist" film 0.051 1.591 -0.512 "BARC" film 0.023 1.306 -3.017 “Metal" substrate 0.881 -2.764 beamfocus 0.05 Figure 1: An arbitrary piece of layout is simulated applying an optical model only. The white line shows how a simple printing result can be obtained by thresholding the image at a certain level. Design and Process Integration for Microelectronic Manufacturing IV, edited by Alfred K. K. Wong, Vivek K. Singh, Proc. of SPIE Vol. 6156, 615619, (2006) · 0277-786X/06/$15 · doi: 10.1117/12.657536 Proc. of SPIE Vol. 6156 615619-1 Downloaded from SPIE Digital Library on 31 Jul 2012 to 128.118.88.243. Terms of Use: http://spiedl.org/terms

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Page 1: SPIE Proceedings [SPIE SPIE 31st International Symposium on Advanced Lithography - San Jose, CA (Sunday 19 February 2006)] Design and Process Integration for Microelectronic Manufacturing

The Influence of Calibration Pattern Coverage for Lumped Parameter Resist Models on OPC Convergence

Martin Niehoffa, Shumay Shangb, Olivier Toublanc

aMentor Graphics, Muenchen, Germany bMentor Graphics, San Jose, USA

cMentor Graphics, Grenoble, France

ABSTRACT Besides models describing the exposure tool optical system, lumped parameter resist models are the other important model used during OPC. This combination is able to deliver the speed and accuracy required during OPC. Lumped parameter resist models are created by fitting a polynomial to empirical data. The parameters of this polynomial are usually image parameters (maximum and minimum intensity, slope, curvature) taken from the optical simulation for each measured structure. During calibration of such models, it is very important to pay attention to the parameter space covered by the calibration pattern used. We analyze parameter space coverage for standard calibration patterns, real layout situation post OPC correction as well as pre OPC correction. Taking this one step further, the influence of parameter space coverage during model calibration on OPC convergence is also studied. Keywords: VT5, parameter space coverage, OPC, lumped parameter resist model.

INTRODUCTION Lithography process modeling for OPC is usually divided into two steps: First, physically based models are used to predict the influence of optical imaging on patterning. Ideally, those models yield an accurate prediction of the aerial image as it is created in the actual exposure system. Figure 1 shows a piece of layout and the result of the aerial image simulation of that layout.

opticalsystem 0.193 0.650

magnification 4.

hoodpix 2.56

kerngrid 0.005

illumtype COMPOSITE

ANN sigma 0.855 sigma_in 0.533

film 0.19 1.696 -0.022 “Resist"

film 0.051 1.591 -0.512 "BARC"

film 0.023 1.306 -3.017 “Metal"

substrate 0.881 -2.764

beamfocus 0.05

opticalsystem 0.193 0.650

magnification 4.

hoodpix 2.56

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illumtype COMPOSITE

ANN sigma 0.855 sigma_in 0.533

film 0.19 1.696 -0.022 “Resist"

film 0.051 1.591 -0.512 "BARC"

film 0.023 1.306 -3.017 “Metal"

substrate 0.881 -2.764

beamfocus 0.05

Figure 1: An arbitrary piece of layout is simulated applying an optical model only. The white line shows how a simple printing result can be obtained by thresholding the image at a certain level.

Design and Process Integration for Microelectronic Manufacturing IV, edited by Alfred K. K. Wong, Vivek K. Singh, Proc. of SPIE Vol. 6156, 615619, (2006) · 0277-786X/06/$15 · doi: 10.1117/12.657536

Proc. of SPIE Vol. 6156 615619-1

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Page 2: SPIE Proceedings [SPIE SPIE 31st International Symposium on Advanced Lithography - San Jose, CA (Sunday 19 February 2006)] Design and Process Integration for Microelectronic Manufacturing

In a second step, a lumped parameter resist model is applied to characterize the complex influence of resist and developer chemistry on final printed geometries. A lumped parameter resist model, for example the VT5 model used by Mentor Graphics Calibre OPC software [1,2], is created by fitting a polynomial to many empirical data points (usually from SEM measurements). The parameters used in this polynomial are usually image parameters, sometimes extended by density parameters extracted from the image predicted by the optical simulation. Figure 2 shows how those parameters are derived from the aerial image:

• First, sites (simulation cutlines) are placed on the edges of the layout to be simulated. Along those sites, an optical simulation is performed for a certain number of points.

• From the aerial image that is the result of this simulation, certain image parameters are extracted: Minimum and maximum intensity, the slope of the aerial image and the local curvature of the aerial image.

• Those parameters are then used as input into the VT5 resist polynomial.

This VT5 polynomial builds a variable threshold: Finding the point where the optical image crosses this ‘printing threshold’ yields the edge placement error (EPE) for the edge the site originally was created on. When calibrating such models, it has been shown that it is very important to pay attention to the parameter space covered by the calibration pattern used [3,5]. Measuring to many redundant points can explode the time needed to calibrate a model, measuring not enough points or points insignificant for the target layout can result in ill-fittin g models. The traditional approach to solve this issue has been to implement a “bounding box” approach as part of the model. In this approach a validity area is calculated during model calibration. If the image parameters extracted from the aerial image measurements fall outside of this bounding box, the model is automatically restricted to predicting the threshold according to the parameters found at the edge of this bounding box (see Figure 3a). It has been shown that by analyzing the parameter space coverage of test patterns one can reduce the measurement effort required for model calibration by removing points with similar or identical location in parameter space [4]. It has also been shown that lumped parameter resist models may not predict very well for regions in parameter space where they have not been calibrated. Comparing parameter space coverage between calibration pattern and the layout to be corrected can identify areas in parameter space with weak or no test pattern coverage and thus help in developing more robust models. An example for this is shown in Figure 3b. In this work, we try to take this analysis one step

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Figure 2: Image parameters used for the VT5 resist model are extracted from the aerial image and input into the resist polynomial to determine the actual printing threshold.

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further by including parameter space data for the full process window as well as looking at the influence of parameter space coverage on OPC convergence.

EXPERIMENTAL

There are a couple of fundamental questions that need to be answered before parameter space coverage can be analyzed successfully not only for calibration patterns, but also for real layout situations. Those questions are mainly:

1. How to extract the data required for the analysis for the calibration pattern as well as for real layout situations? 2. How to analyze parameter space coverage? 3. How to visualize the coverage in a meaningful way?

During resist model generation, the image parameters for the points measured need to be extracted in order to use them for fitting, so tools to do this extraction are available by default in Calibre. For real layout situations, this is not necessarily the case – here image parameters are extracted within the OPC batch tool and not easily accessible to the user. Fortunately Calibre offers an API interface that can be used to access the simulation engine and write the parameters determined for each simulation site into a simple ASCII text file. This text file is then read and processed further. At this point, the next question needs to be addressed. The image parameters extracted from each simulation site describe simply a point in parameter space. In order to analyze coverage, it is necessary to get from those discrete points to some sort of density. The approach chosen for this study was to simply count the number of data points that fell into a certain 4-dimensional interval, thus determining the density in this interval as one constant value. Finally, this multi-dimensional data needs to be visualized in a way that is intuitive and both easy to understand and interpret. The approach taken to do this is described in Figure 4. The idea here is to pick two of the 4 dimensions and divide the plane described by those two dimensions into intervals. Then for each of those intervals, all data points falling into the interval are collected and plotted on a second coordinate system spanning the remaining two dimensions.

referenceThreshold 0.1bound IMAX 0.116965 0.51024bound SLOPE 0 2.70111bound IMIN 0.00465402 0.103791bound FACTOR -0.677767 3.09501hoodpix 2.56kerngrid 0.01

TPAR SLOPE IMAX FACTOR IMINTTERM 0.1711994TTERM 0.00696287 SLOPE 1TTERM -0.0107671 SLOPE 2TTERM 0.014 IMAX 1TTERM 0.00718352 IMAX 2TTERM -0.0165336 FACTOR 1TTERM 0.000296373 FACTOR 2TTERM -0.00968927 IMIN 1TTERM -0.000964233 IMIN 2

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TPAR SLOPE IMAX FACTOR IMINTTERM 0.1711994TTERM 0.00696287 SLOPE 1TTERM -0.0107671 SLOPE 2TTERM 0.014 IMAX 1TTERM 0.00718352 IMAX 2TTERM -0.0165336 FACTOR 1TTERM 0.000296373 FACTOR 2TTERM -0.00968927 IMIN 1TTERM -0.000964233 IMIN 2

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Figure 3: a) “Bounding box” implementation for assuring the model is only applied in the adequate parameter space. b) Even with this bounding box implemented, there can still be uncalibrated areas that can result in inaccurate predictions.

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Page 4: SPIE Proceedings [SPIE SPIE 31st International Symposium on Advanced Lithography - San Jose, CA (Sunday 19 February 2006)] Design and Process Integration for Microelectronic Manufacturing

Those tools were first applied by looking at the parameter space coverage given by the calibration pattern used for a current metal layer model. This was compared to the parameter space the actual layout pre-OPC correction would require. The results are shown in Figure 5. For this case, it is obvious that while the calibration pattern covers the parameter space found in the layout where most of the sites are located, there are some points in the layout far out of the coverage offered by the calibration pattern.

The question immediately arising from this result is whether the post-OPC layout still shows the same situation. This is analyzed in Figure 6. It is obvious that also post-OPC the model calibration test pattern does not cover all of the parameter combinations required by the layout. However, some change due to OPC can be observed – the extreme combinations of high Imin with high Imax encountered in the pre-OPC layout have been reduced. In general, the coverage has shifted towards lower Imin values. This can be interpreted as a first indicator for successful OPC corrections – small lines exhibiting a large Imin value were printing to small. After OPC correction they are printing bigger and closer to target, thus reducing the minimum intensity observed in their aerial image.

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(developed by Mohamed Imam, Mentor Graphics) Imin

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Each square contains the Slope vs. Factor distribution for the Imax/Imin interval

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Each square contains the Slope vs. Factor distribution for the Imax/Imin interval

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Each square contains the Slope vs. Factor distribution for the Imax/Imin interval

(developed by Mohamed Imam, Mentor Graphics) Figure 4: How 4-dimensional data can be visualized in two dimensions. Two dimensions of the image parameter space are divided into intervals, then within each of those intervals the extent of the remaining two dimensions is plotted.

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Figure 5: comparing the parameter space coverage required by the pre-OPC layout to the one offered by the calibration pattern.

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Page 5: SPIE Proceedings [SPIE SPIE 31st International Symposium on Advanced Lithography - San Jose, CA (Sunday 19 February 2006)] Design and Process Integration for Microelectronic Manufacturing

Still, it is clear that in the situation analyzed in this work the calibration pattern does not offer adequate coverage for all layout situations encountered. Since this can potentially cause insufficient OPC correction, it is important to find ways to improve parameter space coverage for the calibration pattern. The most rigorous way to do this would be to find a

way to trace back the points in the real layout showing insufficient coverage and analyze the layout situation exhibiting

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Figure 6: Comparison of parameter space coverage between pre- and post-OPC layouts

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Figure 7: parameter space coverage of the calibration pattern through process window

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this combination of image parameters. One could then hope to find a test pattern based on the layout situation showing the same combination of image parameters and giving the required coverage. However, this is not trivial and was not implemented at the time this study was conducted. An easier approach to extend the parameter space covered by the current calibration pattern is to measure the printing CDs of the calibration pattern used for model building not only at the optimal process condition, but also at various combinations of defocus and under- respectively overexposure. The results of this approach are shown in Figure 7. Measuring the calibration pattern through process window seems to improve the coverage compared to best point, but not up the point that would be required to cover all situations encountered in the full layout. After studying the parameter space coverage offered by the calibration pattern in relation to the one required for the full layout, the main question we wanted to answer was whether and how the coverage during model creation would affect convergence during the OPC run. Our hypothesis was that models that were calibrated to be predictive over a wider range of parameter space should lead to faster and better convergence during OPC, since the EPE prediction for fragments would be more accurate. We conducted the following experiment:

1. build three different models with different parameter space coverage during calibration: a. a standard model by using only the best-point calibration pattern measurements (BP model) b. a process window model by including data from out-of-focus exposures as well as under- and

overexposures (PW model) c. and finally a constant threshold model offering theoretically the best coverage, since this model does

not depend on image parameters for the prediction at all (CTR model) 2. run OPC with all of those models, varying the number of iterations 3. for each OPC run, check the result by running OPCverify to extract the CD-distribution of the corrected layout.

This verification is done using the same model used for OPC, so that self-consistency is maintained. Unfortunately, a real OPC setup file was not available for this process. We used a standard setup file not optimized for accuracy, since we were only interested in relative performance of the three models anyhow. The results of this experiment are shown in Figure 8.

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Figure 8: OPC convergence using different models – CD histogram for the first 4 iterations

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Page 7: SPIE Proceedings [SPIE SPIE 31st International Symposium on Advanced Lithography - San Jose, CA (Sunday 19 February 2006)] Design and Process Integration for Microelectronic Manufacturing

Even though the overall convergence with the non-optimized setup file is not convincing, differences between the results are visible. To be better able to judge convergence, the data can be plotted in a different way as shown in Figure 9. Here the total wire length in the OPC-corrected layout within the chosen specification (in this case +/-50nm) is shown by iteration. This chart shows several interesting results:

• the CTR model gives the best overall convergence, as predicted due to the insensitivity against parameter space coverage issues. This is of course only true when the results are evaluated against the CTR model again, since it is clear that this model in a real application would not offer sufficient accuracy for OPC.

• On first glimpse, the BP model seems to outperform the PW model. This is unexpected, since the PW model offers more parameter space coverage.

• However, when one looks closer, the PW model only seems to have a problem with stability (when used with this specific non-optimized setup file). If one ignores the oscillation visible in the results, the PW model on every second iteration shows the potential to give better overall convergence than the BP model.

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Figure 9: OPC convergence comparison between three models with different parameter space coverage by iteration

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Page 8: SPIE Proceedings [SPIE SPIE 31st International Symposium on Advanced Lithography - San Jose, CA (Sunday 19 February 2006)] Design and Process Integration for Microelectronic Manufacturing

RESULTS AND DISCUSSION

We compared parameter space coverage for calibration patterns versus real layouts. This showed that the specific calibration pattern used has adequate coverage for most situations encountered in a real layout, but could be improved to also cover less frequently occurring layout situations that are currently out of the calibrated parameter space. Those situations occur more frequently in pre-OPC layout than in post-OPC results, showing that it is necessary to look at pre-OPC parameter space requirements when designing a comprehensive test pattern. It was shown that parameter space coverage of existing test patterns can be extended by taking measurements through process window into account. Finally this study seems to indicate that the parameter space going into model calibration shows an influence on OPC convergence. However, further investigations with a more stable combination of setup file and model need to be conducted to come to a final conclusion on this.

CONCLUSIONS AND OUTLOOK In order to be able to accurately target improvements in calibration patterns to cover specific layout situations, it is still necessary to implement a methodology to trace back from outlying points in parameter space to the actual layout situations causing those outliers. Once this is accomplished, it will be possible to design models with specific parameter space coverage compared to the layout, including full coverage of pre-OPC layout parameters. Those will be needed in order to get conclusive data on the dependency between parameter space coverage and OPC convergence. A further option recently introduced for calibrating VT5 resist models is to use SEM pictures to provide EPE measurements useable for model calibration [6]. This might lead to a very quick way to extend parameter space coverage to layout situations that simply could not be covered until now, such as asymmetrical situations or complex 2-dimensional features. We will try to make use of those possibilities in future works to get conclusive results not only on the influence of parameter space coverage on convergence, but also on OPC stability and accuracy. The authors would like to thank many colleagues for providing input for and lively discussion on this paper, especially Dr. Christof Bodendorf at Infineon Technologies München.

REFERENCES 1. Y. Granik et al., New Process Models for OPC at sub -90nm Nodes, Proc. of SPIE Vol. 5040, pp 1166 (2003) 2. Y. Granik et al., Universal Process Modelling with VTRE for OPC, Proc. of SPIE Vol. 4691, pp 377 (2002) 3. T. Roessler et al., Improvement of empirical OPC Model Robustness using Full-Chip Aerial Image Analysis, Proc.

of SPIE Vol. 5256, pp 222 (2003) 4. K. Patterson et al., Improving Model-Based OPC Performance for the 65nm Node Through Calibration Set

Optimization, Proc. of SPIE Vol. 5756, pp 294 (2005) 5. Ralph Schlief, Effects of data selection and noise on goodness of OPC model fit, Proc. of SPIE Vol. 5754, pp 1147-

1158 (2005) 6. G. Bailey et al., Intensive 2D SEM model calibration for 45nm and beyond, Proc. of SPIE Vol. 6154 (2006)

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