spring 2007w. rhett davis with minor modification by dean brock unca ece 406slide 1 ece 406 –...
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Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406 Slide 1
ECE 406 – Design of Complex ECE 406 – Design of Complex Digital SystemsDigital Systems
Lecture 7: Design Example, Lecture 7: Design Example, Modeling Flip-FlopsModeling Flip-Flops
Spring 2007Spring 2007W. Rhett DavisW. Rhett Davis
NC State UniversityNC State Universitywith significant material from Paul Franzon, Bill Allen, & Xun with significant material from Paul Franzon, Bill Allen, & Xun
LiuLiu
Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406 Slide 2
Conditional Statements: if-else
if - else if - else has the following syntax.
if (<expression 1>) <statement 1>;
else if (<expression 2>) <statement 2>;
else <statement 3>;
• If the logical value of <expr 1> is true, <stmt 1> is executed.
• If the logical value of <expr 1> is false and the logical value of <expr 2> is true then <stmt 2> is executed.
• If the logical values of both <expr 1> and <expr 2> are false, then <stmt 3> is executed.
Sutherland guide 10.3
Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406 Slide 3
ALU Example: if-else
Code fragment of a 16-bit arithmetic logic unit (ALU) that performs one of 5 operations.
if (alu_ctrl == 0) // alu_ctrl is 3 bits ALU_OUT = ALU_IN1 + ALU_IN2; // add else if (alu_ctrl == 1) ALU_OUT = ALU_IN1 - ALU_IN2; // subtract else if (alu_ctrl == 2) ALU_OUT = ALU_IN1 & ALU_IN2; // and else if (alu_ctrl == 3) ALU_OUT = ALU_IN1 | ALU_IN2; // orelse if (alu_ctrl == 4) ALU_OUT = ALU_IN1 ^ ALU_IN2; // exorelse ALU_OUT = 16’d0; // other 3 undefined
Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406 Slide 4
Conditional Statements: case
The syntax of the case statement is:case (<expression>) <alternative 1>: <statement 1*>; <alternative 2>: <statement 1*>; • • • <alternative n>: <statement n*>; default: <default statement*>;endcase
The value of <expression> is matched to <alternatives> in sequence, For the first <alternative> that matches, the corresponding <statement> is executed. If no alternatives match, <default statement> is executed.
Sutherland guide 10.3
Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406 Slide 5
ALU Example: case
Using the previous example of an ALU, the corresponding implementation using a case statement is:
case (alu_ctrl) 3’d0: ALU_OUT = ALU_IN1 + ALU_IN2; 3’d1: ALU_OUT = ALU_IN1 - ALU_IN2; 3’d2: ALU_OUT = ALU_IN1 & ALU_IN2; 3’d3: ALU_OUT = ALU_IN1 | ALU_IN2; 3’d4: ALU_OUT = ALU_IN1 ^ ALU_IN2; default: ALU_OUT = 16’d0;
Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406 Slide 6
case: Comparison Details
The case statement literally compares 0, 1, x and z values in the conditional expression bit-by-bit with the alternatives.
Thus if the case expression is 4’b10xz, the comparison is looking for an alternative of 4’b10xz. In other words an exact match is required.
Also, if the sizes of the evaluated expression and the alternative pattern are unequal, the shortest field is extended with zeros so the sizes are equal.
Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406 Slide 7
Alternatives: casex, casez
There are two variants of the case statement defined by the keywords casex and casez.
• casex treats all x and z values in the case expression or alternatives as don’t cares.
• casez treats all z values in the case expression or alternatives as don’t care’s.
The casex is useful when the state of certain bit positions is immaterial in some of the alternatives. By using casex in such situations, it is possible to reduce the number of alternatives needed. Sutherland guide 10.3
Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406 Slide 8
Procedural Examples Muxes and Data Selectors
reg [1:0] in1, in2, out;
reg in3;
always@(in1 or in2 or in3)
if (in3) out = in1;
else out = in2;
in1[0]
in2[0]
in1[1]
in2[1]
in3
out[0]
out[1]
1
0
in1[0]in1[1]in1[2]in1[3]in2
0123
out
reg [3:0] in1;
reg out;
reg [1:0] in2;
always@(in1 or in2)
case (in2)
2’b00 : out = in1[0];
2’b01 : out = in1[1];
2’b10 : out = in1[2];
2’b11 : out = in1[3];
endcase
Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406 Slide 9
Procedural Examples Priority Selector or Encoder
always@(A or B or C) casex(A)
3’b1xx : out = B; 3’b01x : out = C; default : out = 2’b0;
endcase
Decoder
always@(address)
case (address)
2’b00 : line = 4’b0001;
2’b01 : line = 4’b0010;
2’b10 : line = 4’b0100;
2’b11 : line = 4’b1000;
endcase
Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406 Slide 10
Latches
Complete the behavior below:
always@(clock or D)
if (clock) Q = D;
clock
D
Q
We will not intentionally build latches in this class Instead, we’ll stick to one type of timing element
(edge triggered flip-flops)
Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406 Slide 11
Inferred (Unintentional) Latches
What is happening here?
always@(A or B or C) begin
D = B & C;if (D) E = C;
end
Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406 Slide 12
Procedural Examples
What about this?
always@(A or B)
casex (A)
2’b00 : C = B;
2’b01 : C = ~B;
endcase
Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406 Slide 13
Procedural Examples
Will this simulate correctly?
always@(A)
C = A | B;
Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406 Slide 14
D Flip-Flop Timing Diagram
D
clock
Qclock
D
Q
Don’t know(Don’t care)“x”
Glitches at inputdo not appear at output.F/F only samples ‘D’ atpositive clock edge.
Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406 Slide 15
D Flip-Flop Verilog Description
D
clock
Qmodule flipflop (D, clock, Q);input D, clock;output Q;reg Q;always@(posedge clock)
Q = D; endmodule
• posedge & negedge are keywords
Could also be written as
Q <= D;
(what’s the difference?)
Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406 Slide 16
Blocking vs. Non Blocking = is referred to as a blocking
assignment, because execution of subsequent code is blocked until the assignment is made.
<= is referred to as non-blocking assignment. Essentially, all non-blocking right-hand-sides are evaluated but no assignments are made until the end of the procedural block.
Example: What’s the difference between the two code fragments to the right?
T&M 1.3.3, Sutherland guide 10.2
always@(posedge clk)
begin A = Y;
B = A;
end
always@(posedge clk)
begin A <= Y;
B <= A;
end
Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406 Slide 17
Inferring Hardware from Assignments
When given an always@(posedge clock) behavior and asked to draw a schematic, I follow these steps:
» For every left-hand side of an assignment, draw a flip-flop whose output is connected to that signal
» For non-blocking assignments (<=), set the input of each flip-flop to be the right-hand side of the last assignment for each variable
» For blocking assignments (=), work back from the end to figure out the inputs to the flip-flops
When writing your own behavior, it is suggested that you use non-blocking assignments (<=), so that you don’t have to work back from the end.
Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406 Slide 18
Blocking vs. Non Blocking
What hardware would be synthesized for this example?
A = Y;B = A;
A <= Y;B <= A;
Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406 Slide 19
Example
•reg A, B, C, D;•always@(posedge clock)• begin• C = A;• B = C;• C = D;• end
Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406 Slide 20
Example
•reg A, B, C, D;•always@(posedge clock)• begin• C <= A;• B <= C;• C <= D;• end
Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406 Slide 21
Example
•reg A, B, C, D;•always@(posedge clock)• begin• if (A) • D <= B;• else• D <= C;• C <= D;• end
Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406 Slide 22
Procedural Examples
Is there anything wrong with this code?
always@(A or B)
casex (A)
2’b00 : C = B;
2’b01 : C = ~B;
endcase
Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406 Slide 23
Design Example
Design a module named “ALU”. It has three 3-bit inputs A, B, and C and a 1-bit
input E. It has a 3-bit output R and a 1-bit output O. When E is 1, » R is the bit-wise XOR of A and B, and » O is 1.
When E is 0, » R is the sum of B and C (both are assumed to be
signed integers), and » O is the non-overflow indicator, which is 0 when
signed overflow happens.
Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406 Slide 24
A Word About Overflow
Unsigned Overflow occurs when Carry-Out is 1
Signed Overflow occurs when» the sum of positive numbers is negative OR» the sum of negative numbers is positive
…or, equivalently…
» the MSBs of the operands are equal AND» the MSB and Carry-Out of the result differ
Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406 Slide 25
Design Example
Draw a schematic to represent the hardware
Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406 Slide 26
Design Example
Write the Verilog module using Data-Flow (continuous assignments) ONLY.
Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406 Slide 27
Design Example Write a procedural Verilog description (with always @).
Spring 2007W. Rhett Davis with minor modification by Dean Brock UNCA ECE 406 Slide 28
Summary
How do you model a flip-flop?
What is the difference between blocking and non-blocking assignments?
How do you infer flip-flops for an always@(posedge clock) procedure with blocking or non-blocking assignments?
Is it better to use blocking or non-blocking assignments in an always@(posedge clock) procedure? Why?