sprugn4m am dm37x multimedia device

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AM/DM37x Multimedia Device Silicon Revision 1.xVersion M

Technical Reference Manual

Literature Number: SPRUGN4M May 2010 Revised July 2011

WARNING: EXPORT NOTICERecipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled product restricted by other applicable national regulations, received from Disclosing party under this Agreement, or any direct product of such technology, to any destination to which such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorisation from U.S. Department of Commerce and other competent Government authorities to the extent required by those laws. This provision shall survive termination or expiration of this Agreement. According to our best knowledge of the state and end-use of this product or technology, and in compliance with the export control regulations of dual-use goods in force in the origin and exporting countries, this technology is classified as follows: US ECCN: 3E991 EU ECCN: EAR99 And may require export or re-export license for shipping it in compliance with the applicable regulations of certain countries.

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ContentsPreface 1

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.................................................................................................................................... Introduction .................................................................................................................... 1.1 Overview .................................................................................................................. 1.2 Environment .............................................................................................................. 1.3 Description ................................................................................................................ 1.3.1 MPU Subsystem ................................................................................................ 1.3.2 IVA2.2 Subsystem .............................................................................................. 1.3.3 On-Chip Memory ................................................................................................ 1.3.4 External Memory Interfaces ................................................................................... 1.3.5 DMA Controllers ................................................................................................. 1.3.6 Multimedia Accelerators ........................................................................................ 1.3.7 Comprehensive Power Management ......................................................................... 1.3.8 Peripherals ....................................................................................................... 1.4 Package-On-Package Concept ........................................................................................ 1.5 AM/DM37x Family ....................................................................................................... 1.5.1 Device Features ................................................................................................. 1.5.2 Device Identification ............................................................................................ 1.5.3 General Recommendations Relative to Unavailable Features/Modules ................................. Memory Mapping ............................................................................................................. 2.1 Introduction ............................................................................................................... 2.2 Global Memory Space Mapping ....................................................................................... 2.3 L3 and L4 Memory Space Mapping ................................................................................... 2.3.1 L3 Memory Space Mapping ................................................................................... 2.3.2 L4 Memory Space Mapping ................................................................................... 2.3.2.1 L4-Core Memory Space Mapping ...................................................................... 2.3.2.2 L4-Wakeup Memory Space Mapping .................................................................. 2.3.2.3 L4-Peripheral Memory Space Mapping ................................................................ 2.3.2.4 L4-Emulation Memory Space Mapping ................................................................ 2.3.3 Register Access Restrictions .................................................................................. 2.4 IVA2.2 Subsystem Memory Space Mapping ......................................................................... 2.4.1 IVA2.2 Subsystem Internal Memory and Cache Allocation ............................................... 2.4.1.1 IVA2.2 Subsystem Memory Hierarchy ................................................................. 2.4.1.2 IVA2.2 Cache Allocation ................................................................................. 2.4.2 DSP Access to L2 Memories .................................................................................. 2.4.2.1 DSP Access to L2 ROM ................................................................................. 2.4.2.2 DSP Access to L2 RAM ................................................................................. 2.4.3 DSP and EDMA Access to Memories and Peripherals .................................................... 2.4.4 L3 Interconnect View of the IVA2.2 Subsystem Memory Space ......................................... 2.4.5 DSP View of the IVA2.2 Subsystem Memory Space ....................................................... 2.4.6 EDMA View of the IVA2.2 Subsystem Memory Space .................................................... Power, Reset, and Clock Management ................................................................................ 3.1 Introduction to Power Managements .................................................................................. 3.1.1 Goal of Power Management ...................................................................................ContentsCopyright 20102011, Texas Instruments Incorporated

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3.2

3.3

3.4

3.5

3.1.2 Power-Management Techniques ............................................................................. 3.1.2.1 Dynamic Voltage and Frequency Scaling ............................................................. 3.1.2.2 SmartReflex Adaptive Voltage Scaling (AVS) ........................................................ 3.1.2.3 Dynamic Power Switching ............................................................................... 3.1.2.4 Standby Leakage Management ......................................................................... 3.1.2.5 DPS Versus SLM ......................................................................................... 3.1.2.6 Adaptive Body Bias (ABB) ............................................................................... 3.1.2.7 Combining Power-Management Techniques ......................................................... 3.1.3 Architectural Blocks for Power Management ................................................................ 3.1.3.1 Clock Domain ............................................................................................. 3.1.3.2 Power Domain ............................................................................................ 3.1.3.3 Voltage Domain ........................................................................................... 3.1.4 Device Power-Management Architecture .................................................................... 3.1.4.1 Module Interface and Functional Clocks ............................................................... 3.1.4.2 Autoidle Clock Control ................................................................................... 3.1.5 SmartReflex Voltage-Control Overview ...................................................................... 3.1.5.1 Manual SmartReflex Voltage Control .................................................................. 3.1.5.2 Automatic SmartReflex Voltage Control ............................................................... PRCM Overview ......................................................................................................... 3.2.1 Introduction ...................................................................................................... 3.2.2 PRCM Features ................................................................................................. PRCM Environment ...................................................................................................... 3.3.1 External Clock Signals ......................................................................................... 3.3.2 External Reset Signals ......................................................................................... 3.3.3 External Power Signals ........................................................................................ PRCM Integration ........................................................................................................ 3.4.1 Power-Management Scheme, Reset, and Interrupt Requests ............................................ 3.4.1.1 Power Domain ............................................................................................ 3.4.1.2 Resets ...................................................................................................... 3.4.1.3 Interrupt Requests ........................................................................................ PRCM Functional Description .......................................................................................... 3.5.1 PRCM Reset Manager Functional Description .............................................................. 3.5.1.1 Overview ................................................................................................... 3.5.1.2 General Characteristics of Reset Signals ............................................................. 3.5.1.2.1 Scope .................................................................................................. 3.5.1.2.2 Occurrence ............................................................................................ 3.5.1.2.3 Source Type .......................................................................................... 3.5.1.3 Reset Sources ............................................................................................ 3.5.1.3.1 Global Reset Sources ............................................................................... 3.5.1.3.2 Local Reset Sources ................................................................................. 3.5.1.4 Reset Distribution ......................................................................................... 3.5.1.5 Power Domain Reset Descriptions ..................................................................... 3.5.1.5.1 MPU Power Domain ................................................................................. 3.5.1.5.2 NEON Power Domain ............................................................................... 3.5.1.5.3 IVA2 Power Domain ................................................................................. 3.5.1.5.4 CORE Power Domain ............................................................................... 3.5.1.5.5 DSS Power Domain .................................................................................. 3.5.1.5.6 CAM Power Domain ................................................................................. 3.5.1.5.7 USBHOST Power Domain .......................................................................... 3.5.1.5.8 SGX Power Domain ................................................................................. 3.5.1.5.9 WKUP Power Domain ............................................................................... 3.5.1.5.10 PER Power Domain ................................................................................. 3.5.1.5.11 SmartReflex Power Domain ........................................................................

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3.5.1.5.12 DPLL Power Domains ............................................................................... 3.5.1.5.13 EFUSE Power Domain .............................................................................. 3.5.1.5.14 BANDGAP Logic ..................................................................................... 3.5.1.5.15 External Warm Reset Assertion .................................................................... 3.5.1.6 Reset Logging ............................................................................................. 3.5.1.6.1 PRCM Reset Logging Mechanism ................................................................. 3.5.1.6.2 SCM Reset Logging ................................................................................. 3.5.1.7 Reset Management Overview ........................................................................... 3.5.1.8 Reset Summary ........................................................................................... 3.5.1.9 Reset Sequences ......................................................................................... 3.5.1.9.1 Power-Up Sequence ................................................................................. 3.5.1.9.2 Global Warm Reset Sequence ..................................................................... 3.5.1.9.3 IVA2.2 Subsystem Power-Up Sequence .......................................................... 3.5.1.9.4 IVA2 Software Reset Sequence .................................................................... 3.5.1.9.5 IVA2 Global Warm Reset Sequence .............................................................. 3.5.1.9.6 IVA2 Power Domain Wake-Up Cold Reset Sequence .......................................... 3.5.2 PRCM Power Manager Functional Description ............................................................. 3.5.2.1 Overview ................................................................................................... 3.5.2.1.1 Introduction ............................................................................................ 3.5.2.1.2 Device Partitioning ................................................................................... 3.5.2.1.3 Memory and Logic Power Management .......................................................... 3.5.2.1.4 Retention Till Access (RTA) Memory Feature .................................................... 3.5.2.1.5 Power Domain States ............................................................................... 3.5.2.1.6 Power State Transitions ............................................................................. 3.5.2.1.7 Device Power Modes ................................................................................ 3.5.2.1.8 Isolation Between Power Domains ................................................................ 3.5.2.2 Power Domain Implementation ......................................................................... 3.5.2.2.1 Device Power Domains .............................................................................. 3.5.2.2.2 Power Domain Memory Status ..................................................................... 3.5.2.2.3 Power Domain State Transition Rules ............................................................ 3.5.2.2.4 Power Domain Dependencies ...................................................................... 3.5.2.2.5 Power Domain Controls ............................................................................. 3.5.3 PRCM Clock Manager Functional Description .............................................................. 3.5.3.1 Overview ................................................................................................... 3.5.3.1.1 Interface and Functional Clocks .................................................................... 3.5.3.2 External Clock I/Os ....................................................................................... 3.5.3.2.1 External Clock Inputs ................................................................................ 3.5.3.2.2 External Clock Outputs .............................................................................. 3.5.3.2.3 Summary .............................................................................................. 3.5.3.3 Internal Clock Generation ............................................................................... 3.5.3.3.1 PRM .................................................................................................... 3.5.3.3.2 CM ..................................................................................................... 3.5.3.3.3 DPLLs .................................................................................................. 3.5.3.3.4 DPLL Clock Summary ............................................................................... 3.5.3.3.5 Summary .............................................................................................. 3.5.3.4 Clock Distribution ......................................................................................... 3.5.3.4.1 Power Domain Clock Distribution .................................................................. 3.5.3.4.2 Clock Distribution Summary ........................................................................ 3.5.3.5 External Clock Controls .................................................................................. 3.5.3.5.1 Clock Request (sys_clkreq) Control ............................................................... 3.5.3.5.2 System Clock Oscillator Control .................................................................... 3.5.3.5.3 External Output Clock1 (sys_clkout1) Control .................................................... 3.5.3.5.4 External Output Clock2 (sys_clkout2) Control ....................................................SPRUGN4M May 2010 Revised July 2011Copyright 20102011, Texas Instruments Incorporated

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3.5.3.6 DPLL Control .............................................................................................. 3.5.3.6.1 DPLL Multiplier and Divider Factors ............................................................... 3.5.3.6.2 DPLL Modes .......................................................................................... 3.5.3.6.3 DPLL Low-Power Mode ............................................................................. 3.5.3.6.4 DPLL Clock Path Power Down ..................................................................... 3.5.3.6.5 Recalibration .......................................................................................... 3.5.3.6.6 DPLL Programming Sequence ..................................................................... 3.5.3.7 Internal Clock Controls ................................................................................... 3.5.3.7.1 PRM Source-Clock Controls ........................................................................ 3.5.3.7.2 CM Source-Clock Controls .......................................................................... 3.5.3.7.3 Common Interface Clock Controls ................................................................. 3.5.3.7.4 DPLL Source-Clock Controls ....................................................................... 3.5.3.7.5 SGX Power Domain Clock Controls ............................................................... 3.5.3.7.6 CORE Power Domain Clock Controls ............................................................. 3.5.3.7.7 EFUSE Power Domain Clock Controls ............................................................ 3.5.3.7.8 DSS Power Domain Clock Controls ............................................................... 3.5.3.7.9 CAM Power Domain Clock Controls ............................................................... 3.5.3.7.10 USBHOST Power Domain Clock Controls ....................................................... 3.5.3.7.11 WKUP Power Domain Clock Controls ............................................................ 3.5.3.7.12 PER Power Domain Clock Controls ............................................................... 3.5.3.7.13 SMARTREFLEX Power Domain Clock Controls ................................................. 3.5.3.8 Clock Configurations ..................................................................................... 3.5.3.8.1 Processor Clock Configurations .................................................................... 3.5.3.8.2 Interface and Peripheral Functional Clock Configurations ...................................... 3.5.4 PRCM Idle and Wake-Up Management ..................................................................... 3.5.4.1 Overview ................................................................................................... 3.5.4.2 Sleep Transition ........................................................................................... 3.5.4.3 Wakeup .................................................................................................... 3.5.4.4 Device Wake-Up Events ................................................................................. 3.5.4.5 Sleep and Wake-Up Dependencies .................................................................... 3.5.4.5.1 Sleep Dependencies ................................................................................. 3.5.4.5.2 Wake-Up Dependencies ............................................................................ 3.5.4.6 USBHOST/USBTLL Save-and-Restore Management ............................................... 3.5.4.6.1 USBHOST SAR Sequences ........................................................................ 3.5.4.6.2 USB TLL SAR Sequences .......................................................................... 3.5.5 PRCM Interrupts ................................................................................................ 3.5.6 PRCM Voltage Management Functional Description ...................................................... 3.5.6.1 Overview ................................................................................................... 3.5.6.2 Voltage Domains .......................................................................................... 3.5.6.3 Voltage Domain Dependencies ......................................................................... 3.5.6.4 Voltage-Control Architecture ............................................................................ 3.5.6.5 VDD1 and VDD2 Control ................................................................................ 3.5.6.5.1 Direct Control With VMODE Signals ............................................................... 3.5.6.5.2 Direct Voltage Control With I2C Interface ......................................................... 3.5.6.5.3 Voltage Controller and Dedicated SmartReflex I2C Interface .................................. 3.5.6.5.4 SmartReflex Voltage Control ....................................................................... 3.5.6.6 Analog Cells, LDOs, and Level Shifter Controls ...................................................... 3.5.6.6.1 ABB LDOs Control ................................................................................... 3.5.6.6.2 SRAM Voltage Control .............................................................................. 3.5.6.6.3 Wake-Up and Emulation Voltage Control ......................................................... 3.5.7 PRCM Off-Mode Management ................................................................................ 3.5.7.1 Overview ................................................................................................... 3.5.7.2 Device Off-Mode Configuration .........................................................................6 ContentsCopyright 20102011, Texas Instruments Incorporated

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3.6

3.5.7.2.1 Overview .............................................................................................. 3.5.7.2.2 I/O Wake-Up Mechanism ........................................................................... 3.5.7.3 CORE Power Domain Off-Mode Sequences ......................................................... 3.5.7.3.1 Sleep Sequences (Transition From On to Retention/Off) ....................................... 3.5.7.3.2 Wake-Up Sequences (Transition From Retention/Off to On) .................................. 3.5.7.4 Device Off-Mode Sequences ............................................................................ 3.5.7.4.1 Sleep Sequences .................................................................................... 3.5.7.4.2 Wake-Up Sequences ................................................................................ PRCM Basic Programming Model ..................................................................................... 3.6.1 Global Registers ................................................................................................ 3.6.1.1 Revision Information Registers ......................................................................... 3.6.1.2 PRCM Configuration Registers ......................................................................... 3.6.1.3 Interrupt Configuration Registers ....................................................................... 3.6.1.3.1 MPU Interrupt Event Sources ...................................................................... 3.6.1.3.2 MPU Interrupt Registers ............................................................................. 3.6.1.3.3 IVA2.2 Interrupt Event Sources .................................................................... 3.6.1.3.4 IVA2 Interrupt Registers ............................................................................. 3.6.1.4 Event Generator Control Registers ..................................................................... 3.6.1.5 Output Signal Polarity Control Registers .............................................................. 3.6.1.5.1 CM_POLCTRL (CM Polarity Control Register) ................................................... 3.6.1.5.2 PRM_POLCTRL (PRM Polarity Control Register) ............................................... 3.6.1.6 SRAM Precharge Time Control Register .............................................................. 3.6.1.6.1 PRM_SRAM_PCHARGE (Voltage SRAM Precharge Counter Register) ..................... 3.6.2 Clock Management Registers ................................................................................. 3.6.2.1 System Clock Control Registers ........................................................................ 3.6.2.1.1 PRM_CLKSRC_CTRL (Clock Source Control Register) ........................................ 3.6.2.1.2 PRM_CLKSETUP (Source-Clock Setup Register) .............................................. 3.6.2.1.3 PRM_CLKSEL (Source-Clock Selection Register) .............................................. 3.6.2.2 External Clock Output Control Registers .............................................................. 3.6.2.2.1 PRM_CLKOUT_CTRL (Clock Out Control Register) ............................................ 3.6.2.2.2 CM_CLKOUT_CTRL (Clock Out Control Register) .............................................. 3.6.2.3 DPLL Clock Control Registers .......................................................................... 3.6.2.3.1 CM_CLKSELn_PLL_ processor_name (Processor DPLL Clock Selection Register) ....... 3.6.2.3.2 CM_CLKSELn_PLL (DPLL Clock Selection Register) .......................................... 3.6.2.3.3 CM_CLKEN_PLL_processor_name (Processor DPLL Clock Enable Register) ............. 3.6.2.3.4 CM_CLKEN_PLL (DPLL Enable Register) ....................................................... 3.6.2.3.5 CM_AUTOIDLE_PLL_ processor_name (Processor DPLL Autoidle Register) .............. 3.6.2.3.6 CM_AUTOIDLE_PLL (DPLL Autoidle Register) ................................................. 3.6.2.3.7 CM_AUTOIDLE1_PLL (DPLL5 Autoidle Register) .............................................. 3.6.2.3.8 CM_IDLEST_CKGEN (Source-Clock Idle-Status Register) .................................... 3.6.2.3.9 CM_IDLEST2_CKGEN (DPLL5 Source-Clock Idle-Status Register) .......................... 3.6.2.3.10 CM_IDLEST_PLL_ processor_name (Processor DPLL Idle-Status Register) ............... 3.6.2.4 Power-Domain Clock Control Registers ............................................................... 3.6.2.4.1 CM_CLKSEL_ domain_name (Clock Select Register) .......................................... 3.6.2.4.2 CM_FCLKEN_ domain_name (Functional Clock Enable Register) ........................... 3.6.2.4.3 CM_ICLKEN_ domain_name (Interface Clock Enable Register) .............................. 3.6.2.4.4 CM_AUTOIDLE_ domain_name (Autoidle Register) ............................................ 3.6.2.4.5 CM_IDLEST_ domain_name (Idle-Status Register) ............................................. 3.6.2.4.6 CM_CLKSTCTRL_ domain_name (Clock State Control Register) ............................ 3.6.2.4.7 CM_CLKSTST_ domain_name (Clock State Status Register) ................................. 3.6.2.4.8 CM_SLEEPDEP_ domain_name (Sleep Dependency Control Register) ..................... 3.6.2.5 Domain Wake-Up Control Registers ................................................................... 3.6.2.5.1 PM_WKEN_ domain_name (Wake-Up Enable Register) .......................................ContentsCopyright 20102011, Texas Instruments Incorporated

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3.7

.......................................................................................................... 420 PRM_VC_SMPS_CMD_RA (Voltage Controller SMPS Command Register Address Register) .......................................................................................................... 420 3.6.5.2.4 PRM_VC_CMD_VAL_0 and PRM_VC_CMD_VAL_1 (Voltage Controller Command and Voltage Value Register 0 and 1) ................................................................... 420 3.6.5.2.5 PRM_VC_CH_CONF (Voltage Controller Channel Configuration Register) ................. 420 3.6.5.2.6 PRM_VC_I2C_CFG (Voltage Controller I2C Interface Configuration Register) .............. 420 3.6.5.2.7 PRM_VC_BYPASS_VAL (Voltage Controller Bypass Command Register) .................. 420 3.6.5.3 Voltage Processor Registers ............................................................................ 421 3.6.5.3.1 PRM_VP_CONFIG (Voltage Processor Configuration Register) .............................. 421 3.6.5.3.2 PRM_VP_VSTEPMIN (Voltage Processor Minimum Voltage Step) ........................... 421 3.6.5.3.3 PRM_VP_VSTEPMAX (Voltage Processor Maximum Voltage Step) ......................... 421 3.6.5.3.4 PRM_VP_VLIMITTO (Voltage Processor Voltage Limit and Time-Out) ...................... 421 3.6.5.3.5 PRM_VP_VOLTAGE (Voltage Processor Voltage Register) ................................... 422 3.6.5.3.6 PRM_VP_STATUS (Voltage Processor Status Register) ...................................... 422 3.6.6 Generic Programming Examples ............................................................................. 422 3.6.6.1 Clock Control .............................................................................................. 422 3.6.6.1.1 Enabling and Disabling the Functional Clocks ................................................... 422 3.6.6.1.2 Enabling and Disabling the Interface Clocks ..................................................... 424 3.6.6.1.3 Enabling and Disabling the Inactive State ........................................................ 425 3.6.6.1.4 Processor Clock Control ............................................................................ 426 3.6.6.2 Reset Management ....................................................................................... 429 3.6.6.3 Wake-Up Control ......................................................................................... 429 3.6.6.4 SmartReflex Module Initialization Basic Programming Model ...................................... 430 3.6.6.5 Voltage Processor Initialization Basic Programming Model ......................................... 433 3.6.6.6 Voltage Controller Initialization Basic Programming Model ......................................... 437 3.6.6.7 Changing OPP Using the SmartReflex Module ....................................................... 440 3.6.6.8 Changing OPP Using Only the Voltage Processor Module ......................................... 442 3.6.6.9 Event Generator Programming Examples ............................................................. 444 PRCM Register Manual ................................................................................................. 445 3.7.1 CM Module Registers .......................................................................................... 445 3.7.1.1 CM Instance Summary ................................................................................... 445 3.7.1.2 IVA2_CM Registers ...................................................................................... 445 3.7.1.2.1 IVA2_CM Register Summary ....................................................................... 4453.6.5.2.3SPRUGN4M May 2010 Revised July 2011Copyright 20102011, Texas Instruments Incorporated

3.6.2.5.2 PM_WKST_ domain_name (Wake-Up Status Register) ........................................ 3.6.2.5.3 PM_WKDEP_ domain_name (Wake-Up Dependency Register) .............................. 3.6.2.5.4 PM_ processor_name GRPSEL_ domain_name (Processor Group Selection Register) .. 3.6.3 Reset Management Registers ................................................................................. 3.6.3.1 Reset Control .............................................................................................. 3.6.3.1.1 PRM_RSTTIME (Reset Time Register) ........................................................... 3.6.3.1.2 RM_RSTCTRL_ domain_name (Reset Control Register) ...................................... 3.6.3.1.3 RM_RSTST_ domain_name (Reset Status Register) ........................................... 3.6.4 Power Management Registers ................................................................................ 3.6.4.1 PM_PWSTCTRL_ domain_name (Power State Control Register) ................................. 3.6.4.2 PM_PWSTST_ domain_name (Power State Status Register) ..................................... 3.6.4.3 PM_PREPWSTST_ domain_name (Previous Power State Status Register) .................... 3.6.5 Voltage Management Registers ............................................................................... 3.6.5.1 External Voltage Control Register Descriptions ...................................................... 3.6.5.1.1 PRM_VOLTSETUP (Voltage Setup Time Register) ............................................. 3.6.5.1.2 PRM_VOLTOFFSET (Voltage Offset Register) .................................................. 3.6.5.1.3 PRM_VOLTCTRL (Voltage Source Control Register) ........................................... 3.6.5.2 Voltage Controller Registers ............................................................................ 3.6.5.2.1 PRM_VC_SMPS_SA (Voltage Controller SMPS Slave Address Register) .................. 3.6.5.2.2 PRM_VC_SMPS_VOL_RA (Voltage Controller SMPS Voltage Register Address Register)

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3.7.1.2.2 IVA2_CM Registers .................................................................................. 3.7.1.3 OCP_System_Reg_CM Registers ..................................................................... 3.7.1.3.1 OCP_System_Reg_CM Register Summary ...................................................... 3.7.1.3.2 OCP_System_Reg_CM Registers ................................................................. 3.7.1.4 MPU_CM Registers ...................................................................................... 3.7.1.4.1 MPU_CM Register Summary ....................................................................... 3.7.1.4.2 MPU_CM Registers .................................................................................. 3.7.1.5 CORE_CM Registers .................................................................................... 3.7.1.5.1 CORE_CM Register Summary ..................................................................... 3.7.1.5.2 CORE_CM Registers ................................................................................ 3.7.1.6 SGX_CM Registers ....................................................................................... 3.7.1.6.1 SGX_CM Register Summary ....................................................................... 3.7.1.6.2 SGX_CM Registers .................................................................................. 3.7.1.7 WKUP_CM Registers .................................................................................... 3.7.1.7.1 WKUP_CM Register Summary ..................................................................... 3.7.1.7.2 WKUP_CM Registers ................................................................................ 3.7.1.8 Clock_Control_Reg_CM Registers ..................................................................... 3.7.1.8.1 Clock_Control_Reg_CM Register Summary ..................................................... 3.7.1.8.2 Clock_Control_Reg_CM Registers ................................................................ 3.7.1.9 DSS_CM Registers ....................................................................................... 3.7.1.9.1 DSS_CM Register Summary ....................................................................... 3.7.1.9.2 DSS_CM Registers .................................................................................. 3.7.1.10 CAM_CM Registers ...................................................................................... 3.7.1.10.1 CAM_CM Register Summary ....................................................................... 3.7.1.10.2 CAM_CM Registers .................................................................................. 3.7.1.11 PER_CM Registers ....................................................................................... 3.7.1.11.1 PER_CM Register Summary ....................................................................... 3.7.1.11.2 PER_CM Registers .................................................................................. 3.7.1.12 EMU_CM Registers ...................................................................................... 3.7.1.12.1 EMU_CM Register Summary ....................................................................... 3.7.1.12.2 EMU_CM Registers .................................................................................. 3.7.1.13 Global_Reg_CM Registers .............................................................................. 3.7.1.13.1 Global_Reg_CM Register Summary .............................................................. 3.7.1.13.2 Global_Reg_CM Registers ......................................................................... 3.7.1.14 NEON_CM Registers .................................................................................... 3.7.1.14.1 NEON_CM Register Summary ..................................................................... 3.7.1.14.2 NEON_CM Registers ................................................................................ 3.7.1.15 USBHOST_CM Registers ............................................................................... 3.7.1.15.1 USBHOST_CM Register Summary ................................................................ 3.7.1.15.2 USBHOST_CM Registers ........................................................................... 3.7.2 PRM Module Registers ......................................................................................... 3.7.2.1 PRM Instance Summary ................................................................................. 3.7.2.2 IVA2_PRM Registers ..................................................................................... 3.7.2.2.1 IVA2_PRM Register Summary ..................................................................... 3.7.2.2.2 IVA2_PRM Registers ................................................................................ 3.7.2.3 OCP_System_Reg_PRM Registers .................................................................... 3.7.2.3.1 OCP_System_Reg PRM Register Summary ..................................................... 3.7.2.3.2 OCP_System_Reg_PRM Registers ............................................................... 3.7.2.4 MPU_PRM Registers Registers ........................................................................ 3.7.2.4.1 MPU_PRM Registers Register Summary ......................................................... 3.7.2.4.2 MPU_PRM Registers ................................................................................ 3.7.2.5 CORE_PRM Registers ................................................................................... 3.7.2.5.1 CORE_PRM Register Summary ...................................................................SPRUGN4M May 2010 Revised July 2011Copyright 20102011, Texas Instruments Incorporated

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3.7.2.5.2 CORE_PRM Registers .............................................................................. 3.7.2.6 SGX_PRM Registers ..................................................................................... 3.7.2.6.1 SGX_PRM Register Summary ..................................................................... 3.7.2.6.2 SGX_PRM Registers ................................................................................ 3.7.2.7 WKUP_PRM Registers .................................................................................. 3.7.2.7.1 WKUP_PRM Register Summary ................................................................... 3.7.2.7.2 WKUP_PRM Registers .............................................................................. 3.7.2.8 Clock_Control_Reg_PRM Registers ................................................................... 3.7.2.8.1 Clock_Control_Reg_PRM Register Summary .................................................... 3.7.2.8.2 Clock_Control_Reg_PRM Registers ............................................................... 3.7.2.9 DSS_PRM Registers ..................................................................................... 3.7.2.9.1 DSS_PRM Register Summary ..................................................................... 3.7.2.9.2 DSS_PRM Registers ................................................................................ 3.7.2.10 CAM_PRM Registers .................................................................................... 3.7.2.10.1 CAM_PRM Registers ................................................................................ 3.7.2.10.2 CAM_PRM Registers ................................................................................ 3.7.2.11 PER_PRM Registers ..................................................................................... 3.7.2.11.1 PER_PRM Register Summary ..................................................................... 3.7.2.11.2 PER_PRM Registers ................................................................................ 3.7.2.12 EMU_PRM Registers .................................................................................... 3.7.2.12.1 EMU_PRM Register Summary ..................................................................... 3.7.2.12.2 EMU_PRM Registers ................................................................................ 3.7.2.13 Global_Reg_PRM Registers ............................................................................ 3.7.2.13.1 Global_Reg_PRM Register Summary ............................................................. 3.7.2.13.2 Global_Reg_PRM Registers ........................................................................ 3.7.2.14 NEON_PRM Registers ................................................................................... 3.7.2.14.1 NEON_PRM Register Summary ................................................................... 3.7.2.14.2 NEON_PRM Registers .............................................................................. 3.7.2.15 USBHOST_PRM Registers ............................................................................. 3.7.2.15.1 USBHOST_PRM Register Summary .............................................................. 3.7.2.15.2 USBHOST_PRM Registers ......................................................................... 3.7.3 SR Registers ..................................................................................................... 3.7.3.1 SR Instance Summary ................................................................................... 3.7.3.2 SR Registers .............................................................................................. 3.7.3.2.1 SR Register Summary ............................................................................... 3.7.3.2.2 SR Registers ..........................................................................................

561 577 577 578 581 581 582 586 586 587 588 588 588 593 593 593 597 597 597 610 610 610 612 612 613 636 636 636 640 640 640 647 647 647 647 647 660 660 660 662 663 663 664 666 666 666 666 666 667 667 667 667

4

MPU Subsystem4.1

.............................................................................................................. 659

4.2

MPU Subsystem Overview ............................................................................................. 4.1.1 Introduction ...................................................................................................... 4.1.2 Features .......................................................................................................... MPU Subsystem Integration ............................................................................................ 4.2.1 MPU Subsystem Clock and Reset Distribution ............................................................. 4.2.1.1 Clock Distribution ......................................................................................... 4.2.1.2 Reset Distribution ......................................................................................... 4.2.2 ARM Subchip .................................................................................................... 4.2.2.1 ARM Overview ............................................................................................ 4.2.2.2 ARM Description .......................................................................................... 4.2.2.2.1 ARM Cortex-A8 Instruction, Data, and Private Peripheral Port ................................ 4.2.2.2.2 MPU Subsystem Features .......................................................................... 4.2.2.3 Clock, Reset, and Power Management ................................................................ 4.2.2.3.1 Clocks .................................................................................................. 4.2.2.3.2 Reset ................................................................................................... 4.2.2.3.3 Power Management .................................................................................

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4.3

4.4

4.2.3 Local Interconnect .............................................................................................. 4.2.3.1 Description ................................................................................................. 4.2.3.2 Clocks, Reset, and Power Management .............................................................. 4.2.3.2.1 Clocks .................................................................................................. 4.2.3.2.2 Reset ................................................................................................... 4.2.3.2.3 Power Management ................................................................................. 4.2.4 Interrupt Controller .............................................................................................. 4.2.4.1 Clocks ...................................................................................................... 4.2.4.2 Reset ....................................................................................................... 4.2.4.3 Power Management ...................................................................................... MPU Subsystem Functional Description .............................................................................. 4.3.1 Interrupts ......................................................................................................... 4.3.2 Power Management ............................................................................................ 4.3.2.1 Power Domains ........................................................................................... 4.3.2.2 Power States .............................................................................................. 4.3.2.3 Power Modes .............................................................................................. 4.3.2.4 Transitions ................................................................................................. MPU Subsystem Basic Programming Model ......................................................................... 4.4.1 MPU Subsystem Initialization Sequence .................................................................... 4.4.2 Clock Control .................................................................................................... 4.4.3 MPU Power Mode Transitions ................................................................................ 4.4.3.1 Basic Power-On Reset ................................................................................... 4.4.3.2 MPU Into Standby Mode ................................................................................. 4.4.3.3 MPU Out of Standby Mode .............................................................................. 4.4.3.4 MPU Power-On From a Powered-Off State ........................................................... 4.4.4 ARM Programming Model ..................................................................................... IVA2.2 Subsystem Overview ........................................................................................... 5.1.1 IVA2.2 Subsystem Key Features ............................................................................. IVA2.2 Subsystem Integration .......................................................................................... 5.2.1 Clocking, Reset, and Power-Management Scheme ........................................................ 5.2.1.1 Clocks ...................................................................................................... 5.2.1.1.1 IVA2.2 Clocks ......................................................................................... 5.2.1.2 Resets ...................................................................................................... 5.2.1.2.1 Hardware Resets ..................................................................................... 5.2.1.2.2 Software Resets ...................................................................................... 5.2.1.3 Power Domain ............................................................................................ 5.2.2 Hardware Requests ............................................................................................. 5.2.2.1 DMA Requests ............................................................................................ 5.2.2.2 Interrupt Requests ........................................................................................ IVA2.2 Subsystem Functional Description ............................................................................ 5.3.1 DSP Megamodule ............................................................................................... 5.3.1.1 DSP Overview ............................................................................................. 5.3.1.2 Program Memory Controller Overview ................................................................. 5.3.1.3 DMC Overview ............................................................................................ 5.3.1.4 UMC Overview ............................................................................................ 5.3.1.5 EMC Overview ............................................................................................ 5.3.1.6 Memory Protection Overview ........................................................................... 5.3.1.7 INTC ........................................................................................................ 5.3.1.7.1 Event Type ............................................................................................ 5.3.1.7.2 Event Behavior ....................................................................................... 5.3.1.7.3 Event Detection ....................................................................................... 5.3.1.7.4 Event Selection .......................................................................................ContentsCopyright 20102011, Texas Instruments Incorporated

667 667 667 667 667 668 668 668 668 668 669 669 669 669 670 670 672 674 674 674 674 674 674 675 675 675 678 678 680 681 681 681 681 681 683 683 685 685 686 690 690 691 692 692 693 694 694 694 696 696 697 69711

5

IVA2.2 Subsystem5.1 5.2

............................................................................................................ 677

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5.4

5.3.1.7.5 Event Combination ................................................................................... 5.3.1.7.6 Interrupt Event Error ................................................................................. 5.3.1.7.7 PDC Overview ........................................................................................ 5.3.1.8 Other DSP Reference Documents ..................................................................... 5.3.2 DMA Engines .................................................................................................... 5.3.2.1 EDMA ...................................................................................................... 5.3.2.1.1 Third-Party Channel Controller ..................................................................... 5.3.2.1.2 Third-Party Transfer Controller ..................................................................... 5.3.2.1.3 EDMA Hardware Parameters ....................................................................... 5.3.2.2 EDMA Access to Video Accelerator/Sequencer ...................................................... 5.3.2.3 IDMA ....................................................................................................... 5.3.3 MMU .............................................................................................................. 5.3.3.1 MMU VA-to-PA Translation .............................................................................. 5.3.3.2 MMU Configuration ....................................................................................... 5.3.4 Video Accelerator/Sequencer Local Interconnect .......................................................... 5.3.5 SL2 Interface .................................................................................................... 5.3.5.1 BWO ........................................................................................................ 5.3.5.2 Arbiter ...................................................................................................... 5.3.5.3 Restrictions on SL2 Memory Usage .................................................................... 5.3.5.4 Error Management ........................................................................................ 5.3.6 Wake-Up Generator ............................................................................................ 5.3.6.1 Interrupts, DMA Requests, and Event Management ................................................. 5.3.6.1.1 Event Generation ..................................................................................... 5.3.6.1.2 Individual Event Masking ............................................................................ 5.3.6.1.3 Individual Event Mask Clear ........................................................................ 5.3.6.2 Idle Handshake ........................................................................................... 5.3.7 SYSC Module ................................................................................................... 5.3.7.1 Divided Clock Generation ............................................................................... 5.3.7.2 Clock Management, Power-Down, and Wake-Up .................................................... 5.3.7.3 Boot Configuration ........................................................................................ 5.3.7.4 Interconnect Optimization ................................................................................ 5.3.7.5 Video Accelerator/Sequencer SYSC ................................................................... 5.3.7.5.1 Reset ................................................................................................... 5.3.7.5.2 Power Management ................................................................................. 5.3.7.5.3 Interrupt Handler ..................................................................................... 5.3.8 Local Memories ................................................................................................. 5.3.8.1 ROM Overview ............................................................................................ 5.3.8.2 RAM Overview ............................................................................................ 5.3.9 Local Interconnect Network .................................................................................... 5.3.9.1 Endianness ................................................................................................ 5.3.10 Error Reporting ................................................................................................. IVA2.2 Subsystem Basic Programming Model ....................................................................... 5.4.1 IVA2.2 Boot ...................................................................................................... 5.4.1.1 IVA2.2 Boot Configuration ............................................................................... 5.4.1.1.1 IDLE Boot Mode ...................................................................................... 5.4.1.1.2 Wait in Self-Loop Mode ............................................................................. 5.4.1.1.3 Default Config Cache Mode ........................................................................ 5.4.1.1.4 User Defined Bootstrap Mode ...................................................................... 5.4.1.2 Example of IVA2.2 Boot ................................................................................. 5.4.1.2.1 Boot Under MPU Control ............................................................................ 5.4.1.2.2 Autonomous Boot .................................................................................... 5.4.2 Sequencer Boot/Reset ......................................................................................... 5.4.3 Cache Management ............................................................................................

698 698 698 698 700 700 701 706 709 710 711 711 712 713 714 715 716 717 717 717 717 718 718 719 720 721 721 722 722 723 723 723 723 723 724 724 726 726 726 727 727 728 728 728 729 729 729 730 730 730 732 733 733

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5.4.3.1 Cache-Size Configuration ............................................................................... 5.4.3.2 Cache Mode Configuration .............................................................................. 5.4.3.3 Cacheability Settings ..................................................................................... 5.4.3.4 Coherence Maintenance ................................................................................. 5.4.3.4.1 Memory-Mapped L1P and L1D Coherence ....................................................... 5.4.3.4.2 Memory-Mapped L2 Coherence ................................................................... 5.4.3.4.3 Device Memory Coherence ......................................................................... 5.4.3.4.4 Global Cache Management ......................................................................... 5.4.3.4.5 Block Cache Management .......................................................................... 5.4.3.4.6 Write-Back Completion .............................................................................. 5.4.3.4.7 Performance Consideration Timing ................................................................ 5.4.4 DMA Management .............................................................................................. 5.4.4.1 Transfers From/to Device Memories/Peripherals (EDMA) .......................................... 5.4.4.2 Internal Memory-to-Memory Transfer (IDMA) ......................................................... 5.4.4.3 Programming an EDMA Transfer ....................................................................... 5.4.4.4 Defining a Logical Channel .............................................................................. 5.4.4.4.1 Single Logical Channel Definition .................................................................. 5.4.4.4.2 Controlling Submission Granularity ................................................................ 5.4.4.4.3 Linking to Another Logical Channel ................................................................ 5.4.4.4.4 Chaining Logical Channel ........................................................................... 5.4.4.5 Prioritizing Defined Transfers ........................................................................... 5.4.4.5.1 Mapping Between DMA/QDMA Events and Event Queues .................................... 5.4.4.5.2 Mapping a Queue to a Transfer Controller ....................................................... 5.4.4.5.3 Handling Priority ...................................................................................... 5.4.4.5.4 Aged Priority .......................................................................................... 5.4.4.5.5 Optimizing 2D Transfers ............................................................................ 5.4.4.6 Starting the Transfer ..................................................................................... 5.4.4.6.1 Assigning a Logical Channel to a Trigger Event ................................................. 5.4.4.6.2 Manual Trigger (Software-Synchronized Transfers) ............................................. 5.4.4.6.3 Hardware Trigger (Hardware-Synchronized Transfers) ......................................... 5.4.4.6.4 Automatic Trigger (QDMA) .......................................................................... 5.4.4.6.5 Offloaded Configuration (Using IDMA) ............................................................ 5.4.4.6.6 Direct Configuration to Transfer Channel (Not Recommended) ............................... 5.4.4.6.7 DMA Completion Mode .............................................................................. 5.4.4.6.8 Partial Versus Total Completion .................................................................... 5.4.4.6.9 Tracking DMA Completion .......................................................................... 5.4.4.6.10 DMA Interrupt Service Routine ..................................................................... 5.4.4.6.11 Benchmarking ........................................................................................ 5.4.5 IVA2.2 Extended Function Interface .......................................................................... 5.4.5.1 Overview ................................................................................................... 5.4.5.2 C64x+ EFI Instructions ................................................................................... 5.4.5.3 C64x+ EFI Use in IVA2.2 ................................................................................ 5.4.5.3.1 Read Registers Using the EFI Programming Model ............................................. 5.4.5.3.2 Write Registers Using the EFI Programming Model ............................................. 5.4.6 iME and iLF Basic Programming Model ..................................................................... 5.4.6.1 Typical Use ................................................................................................ 5.4.7 iVLCD Basic Programming Model ............................................................................ 5.4.7.1 Setting Up Registers for Q/IQ Operation .............................................................. 5.4.7.1.1 Q/IQ Matrix Setup - Inverse Quantizer Matrix .................................................... 5.4.7.1.2 Q/IQ Rounding ........................................................................................ 5.4.7.1.3 Q/IQ Offset ............................................................................................ 5.4.7.1.4 Q/IQ Threshold ....................................................................................... 5.4.7.2 Setting Up Registers for VLC Operation ...............................................................SPRUGN4M May 2010 Revised July 2011Copyright 20102011, Texas Instruments Incorporated

733 735 736 736 736 736 736 737 738 739 741 741 741 741 742 742 742 743 743 744 744 744 744 745 745 745 745 746 746 746 746 747 747 748 748 749 749 750 750 750 750 754 754 755 756 756 757 759 759 759 759 759 75913

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5.5

5.4.7.3 Setting Up Registers for VLD Operation ............................................................... 5.4.7.4 Calculating the Number of Bits Processed During a VLD Run ..................................... 5.4.7.5 Setting Up Registers for CAVLC Operation ........................................................... 5.4.8 Interrupt Management .......................................................................................... 5.4.8.1 Interrupt Flow in IVA2.2 Subsystem .................................................................... 5.4.8.2 Event Combined Programming Sequence ............................................................ 5.4.8.3 Event Interrupt Mapping Programming Sequence .............................................. 5.4.8.4 Interrupt Exception Programming Sequence .......................................................... 5.4.8.5 Interrupt Controller Basic Programming Model for Power Down of IVA2.2 Subsystem ......... 5.4.8.6 Interrupt Controller Basic Programming Model for Power On of IVA2.2 Subsystem ............ 5.4.8.7 Video and Sequencer Module interrupt Handling .................................................... 5.4.8.7.1 Sequencer Interrupt .................................................................................. 5.4.8.7.2 DSP Megamodule Interrupt ......................................................................... 5.4.9 Memory Management .......................................................................................... 5.4.9.1 External Memory .......................................................................................... 5.4.9.1.1 Cacheability ........................................................................................... 5.4.9.1.2 Virtual Addressing .................................................................................... 5.4.9.2 Internal Memory ........................................................................................... 5.4.9.2.1 Memory Protection ................................................................................... 5.4.9.2.2 Bandwidth Management ............................................................................. 5.4.9.3 SL2 Memory Management .............................................................................. 5.4.9.3.1 SL2 Performance Optimizations ................................................................... 5.4.9.3.2 SL2 Performance Limitations ....................................................................... 5.4.9.3.3 SL2 Illegal Accesses ................................................................................. 5.4.10 IVA2.2 Power Management .................................................................................. 5.4.10.1 Clock Management ....................................................................................... 5.4.10.1.1 Clock Configuration .................................................................................. 5.4.10.1.2 Clock Gating .......................................................................................... 5.4.10.2 Reset Management ....................................................................................... 5.4.10.3 Power-Down and Wake-Up Management ............................................................. 5.4.10.4 Powering Down L2$ Memory While IVA2 is Active .................................................. 5.4.10.5 Video and Sequencer Module Management .......................................................... 5.4.10.5.1 Module Dynamic Power Savings .................................................................. 5.4.10.5.2 System Dynamic Power Savings .................................................................. 5.4.11 Error Identification Process ................................................................................... 5.4.11.1 Error Reporting for IDMA Module ....................................................................... 5.4.11.2 Error Reporting for EDMA Module ..................................................................... 5.4.11.3 Error Reporting for the L3 Interconnect ................................................................ 5.4.12 Recommendations for Static Settings ....................................................................... IVA2.2 Subsystem Register Manual ................................................................................... 5.5.1 IC Registers ...................................................................................................... 5.5.1.1 IC Register Mapping Summary ......................................................................... 5.5.1.2 IC Register Descriptions ................................................................................. 5.5.2 SYS Registers ................................................................................................... 5.5.2.1 SYS Register Mapping Summary ...................................................................... 5.5.2.2 SYS Register Descriptions .............................................................................. 5.5.3 IDMA Registers .................................................................................................. 5.5.3.1 IDMA Register Mapping Summary ..................................................................... 5.5.3.2 IDMA Register Descriptions ............................................................................. 5.5.4 XMC Registers .................................................................................................. 5.5.4.1 XMC Register Mapping Summary ...................................................................... 5.5.4.2 XMC Register Descriptions .............................................................................. 5.5.5 TPCC Registers .................................................................................................

761 763 763 764 764 766 766 766 767 767 770 770 770 772 772 772 772 772 772 777 779 779 779 779 780 780 780 780 780 781 784 785 785 785 786 786 786 787 787 788 788 789 789 797 797 797 800 800 800 812 812 813 838

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5.5.5.1 TPCC Register Mapping Summary .................................................................... 838 5.5.5.2 TPCC Register Descriptions ............................................................................ 841 5.5.6 TPTC0 and TPTC1 Registers ................................................................................. 938 5.5.6.1 TPTC0 and TPTC1 Register Mapping Summary ..................................................... 938 5.5.6.2 TPTC0 and TPTC1 Register Descriptions ............................................................ 940 5.5.7 SYSC Registers ................................................................................................. 963 5.5.7.1 SYSC Register Mapping Summary .................................................................... 963 5.5.7.2 SYSC Register Descriptions ............................................................................ 965 5.5.8 WUGEN Registers .............................................................................................. 969 5.5.8.1 WUGEN Register Mapping Summary ................................................................. 969 5.5.8.2 WUGEN Register Descriptions ......................................................................... 970 5.5.9 iVLCD Registers ................................................................................................ 988 5.5.9.1 iVLCD Register Mapping Summary .................................................................... 988 5.5.9.2 iVLCD Register Descriptions ............................................................................ 990 5.5.10 SEQ Registers ................................................................................................ 1028 5.5.10.1 SEQ Register Mapping Summary ..................................................................... 1028 5.5.10.2 SEQ Register Descriptions ............................................................................ 1028 5.5.11 Video System Controller Registers ........................................................................ 1035 5.5.11.1 Video System Controller Register Mapping Summary ............................................. 1035 5.5.11.2 Video System Controller Register Descriptions ..................................................... 1035 5.5.12 iME Registers ................................................................................................. 1041 5.5.12.1 iME Register Mapping Summary ...................................................................... 1041 5.5.12.2 iME Register Descriptions .............................................................................. 1042 5.5.13 iLF Registers .................................................................................................. 1052 5.5.13.1 iLF Register Mapping Summary ....................................................................... 1052 5.5.13.2 iLF Register Descriptions .............................................................................. 1053 5.5.14 IA_GEM Registers ........................................................................................... 1063 5.5.14.1 IA_GEM Register Mapping Summary ................................................................ 1063 5.5.14.2 IA_GEM Register Descriptions ........................................................................ 1063 5.5.15 IA_EDMA Registers .......................................................................................... 1064 5.5.15.1 IA_EDMA Register Mapping Summary .............................................................. 1064 5.5.15.2 IA_EDMA Register Descriptions ...................................................................... 1064 5.5.16 IA_SEQ Registers ............................................................................................ 1065 5.5.16.1 IA_SEQ Register Mapping Summary ................................................................. 1065 5.5.16.2 IA_SEQ Register Descriptions ........................................................................ 1065

6

Camera Image Signal Processor6.1 6.2

...................................................................................... 1069

Camera ISP Overview ................................................................................................. 1070 6.1.1 Camera ISP Features ......................................................................................... 1072 Camera ISP Environment ............................................................................................. 1075 6.2.1 Camera ISP Functions ........................................................................................ 1075 6.2.2 Camera ISP Signal Descriptions ............................................................................ 1076 6.2.3 Camera ISP Connectivity Schemes ......................................................................... 1077 6.2.4 Camera ISP Protocols and Data Formats .................................................................. 1080 6.2.4.1 Camera ISP Parallel Generic Configuration Protocol and Data Format (8, 10, 11, 12 Bits) .. 1080 6.2.4.2 Camera ISP Parallel Generic Configuration: JPEG Sensor Connection on the Parallel Interface ............................................................................................................. 1081 6.2.4.3 Camera ISP ITU-R BT.656 Protocol and Data Formats (8, 10 Bits) ............................. 1081 6.2.4.4 Camera ISP CSI1/CCP2 Protocol and Data Formats .............................................. 1083 6.2.4.4.1 Camera ISP CSI1/CCP2 Pixel Data Format .................................................... 1086 6.2.4.5 Camera ISP CSI2 Protocol and Data Format ....................................................... 1096 6.2.4.5.1 Camera ISP CSI2 Lane Merger .................................................................. 1096 6.2.4.5.2 Camera ISP CSI2 Protocol Layer ................................................................ 1097 6.2.4.5.3 Camera ISP CSI2 Pixel Data Format ............................................................ 1104ContentsCopyright 20102011, Texas Instruments Incorporated


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6.3

6.4

Camera ISP Integration ................................................................................................ 6.3.1 Camera ISP Clocking, Reset, and Power-Management Scheme ....................................... 6.3.1.1 Camera ISP Clocks ..................................................................................... 6.3.1.1.1 Camera ISP Clock Tree ............................................................................ 6.3.1.1.2 Camera ISP Clock Descriptions .................................................................. 6.3.1.1.3 Camera ISP Clock Configuration ................................................................. 6.3.1.2 Camera ISP Power Management ..................................................................... 6.3.1.2.1 Camera ISP Local Power Management ......................................................... 6.3.1.2.2 Camera ISP System Power Management ....................................................... 6.3.1.3 Camera ISP Power Domain ........................................................................... 6.3.1.4 Camera ISP Resets ..................................................................................... 6.3.1.4.1 Camera ISP Hardware Reset ..................................................................... 6.3.1.4.2 Camera ISP Software Reset ...................................................................... 6.3.2 Camera ISP Hardware Requests ............................................................................ 6.3.2.1 Camera ISP Interrupt Requests ....................................................................... Camera ISP Functional Description .................................................................................. 6.4.1 Camera ISP Block Diagram .................................................................................. 6.4.1.1 Camera ISP Possible Data Paths Inside the module .............................................. 6.4.1.1.1 Camera ISP RGB RAW Data ..................................................................... 6.4.1.1.2 Camera ISP YUV4:2:2 Data ....................................................................... 6.4.1.1.3 JPEG Data ........................................................................................... 6.4.2 Camera ISP CSI1/CCP2B Receiver ........................................................................ 6.4.2.1 Camera ISP CSI1/CCP2B Receiver Features ...................................................... 6.4.2.2 Camera ISP CSI1/CCP2B Receiver Functional Description ...................................... 6.4.2.2.1 Camera ISP CSI1/CCP2B Overview ............................................................. 6.4.2.2.2 Camera ISP CSI1/CCP2B Associated PHY ..................................................... 6.4.2.2.3 Camera ISP CSI1/CCP2B Physical Layer ...................................................... 6.4.2.2.4 Camera ISP CSI1/CCP2B Protocol Layer ....................................................... 6.4.2.2.5 Camera ISP CSI1/CCP2B Memory Read Channel ............................................ 6.4.2.2.6 Camera ISP CSI1/CCP2B Image Data Operating Modes and Alignment Constraints .... 6.4.3 Camera ISP CSI2 Receiver .................................................................................. 6.4.3.1 Camera ISP CSI2 Receiver Features ................................................................ 6.4.3.2 Camera ISP CSI2 Receiver Block Diagram ......................................................... 6.4.3.3 Camera ISP CSI2 Physical Layer Lane Configuration ............................................. 6.4.3.4 Camera ISP CSI2 ECC and Checksum Generation ................................................ 6.4.3.4.1 Camera ISP CSI2 ECC ............................................................................ 6.4.3.4.2 Camera ISP CSI2 Checksum ..................................................................... 6.4.3.5 Camera ISP CSI2 RAW Image Transcoding with DPCM and A-law Compression ............ 6.4.3.6 Camera ISP CSI2 Short Packet ....................................................................... 6.4.3.7 Camera ISP CSI2 Virtual Channel and Context .................................................... 6.4.3.8 Camera ISP CSI2 DMA Engine ....................................................................... 6.4.3.8.1 Camera ISP CSI2 Progressive Frame to Progressive Storage ............................... 6.4.3.8.2 Camera ISP CSI2 Interlaced Frame to Progressive Storage ................................. 6.4.3.9 Camera ISP CSI2 PHYs ............................................................................... 6.4.3.10 Camera ISP CSI2 Data Decompression ............................................................. 6.4.3.11 Camera ISP CSI2 EndOfFrame and EndOfLine Pulses ........................................... 6.4.4 Camera ISP Timing Control .................................................................................. 6.4.4.1 Camera ISP Timing Control Features ................................................................ 6.4.4.2 Camera ISP Timing Control Overview ............................................................... 6.4.4.2.1 Camera ISP Timing Control Generator .......................................................... 6.4.4.2.2 Camera ISP Timing Control Control-Signal Generator ........................................ 6.4.5 Camera ISP Bridge-Lane Shifter ............................................................................ 6.4.6 Camera ISP Video-Processing Front End ..................................................................

1123 1123 1123 1124 1124 1125 1126 1126 1126 1127 1127 1127 1128 1128 1128 1138 1138 1140 1141 1142 1142 1143 1143 1143 1143 1144 1144 1145 1149 1157 1160 1160 1160 1161 1161 1161 1162 1162 1166 1166 1167 1168 1168 1169 1171 1171 1172 1172 1172 1172 1172 1176 1176

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6.4.6.1 Camera ISP CCDC ..................................................................................... 1177 6.4.6.1.1 Camera ISP CCDC Features ..................................................................... 1177 6.4.6.1.2 Camera ISP CCDC Block Diagram .............................................................. 1177 6.4.6.1.3 Camera ISP CCDC Functional Operations ...................................................... 1179 6.4.6.1.4 Camera ISP CCDC DMA .......................................................................... 1190 6.4.6.1.5 Camera ISP CCDC Memories .................................................................... 1190 6.4.7 Camera ISP Video-Processing Back End .................................................................. 1190 6.4.7.1 Camera ISP VPBE Preview Engine Features ....................................................... 1190 6.4.7.1.1 Camera ISP VPBE Preview Block Diagram ..................................................... 1190 6.4.7.1.2 Camera ISP VPBE Preview Input Interface ..................................................... 1191 6.4.7.1.3 Camera ISP VPBE Preview Input Formatter/Averager ........................................ 1192 6.4.7.1.4 Camera ISP VPBE Preview Dark-Frame Write ................................................. 1192 6.4.7.1.5 Camera ISP VPBE Preview Inverse A-Law ..................................................... 1192 6.4.7.1.6 Camera ISP VPBE Preview Dark-Frame Subtract or Shading Compensation ............. 1193 6.4.7.1.7 Camera ISP VPBE Preview Horizontal Median Filter .......................................... 1193 6.4.7.1.8 Camera ISP VPBE Preview Noise Filter and Faulty Pixel Correction ....................... 1193 6.4.7.1.9 Camera ISP VPBE Preview White Balance ..................................................... 1193 6.4.7.1.10 Camera ISP VPBE Preview CFA Interpolation ................................................. 1194 6.4.7.1.11 Camera ISP VPBE Preview Black Adjustment ................................................. 1194 6.4.7.1.12 Camera ISP VPBE Preview RGB Blending ..................................................... 1194 6.4.7.1.13 Camera ISP VPBE Preview Gamma Correction ............................................... 1195 6.4.7.1.14 Camera ISP VPBE Preview RGB to YCbCr Conversion, Luminance Enhancement, Chr

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