Spurs Suppression and Deterministic Jitter Correction in All-Digital Frequency Synthesizers,

Current State and Future Directions Paul P. Sotiriadis

Sotekco Electronics LLC, USA pps (at) ieee (dot) org

Abstract—All-digital frequency synthesizers are favored by modern nano-scale CMOS technologies but suffer from strong frequency spurs and timing irregularities. This paper reviews the time-domain-correction and spurs-suppression techniques for all-digital frequency synthesizers, identifies their strengths and weaknesses and provides new research directions.

I. INTRODUCTION Efforts to develop All-Digital Frequency Synthesizers (ADFS)

can be traced at least three decades back. The main motivation has been the advantages of the digital circuits with respect to the analog ones, which include (at least partially) automated design and layout, short specs to product time and easy technology migration.

ADFS are based on Numerically Controlled Oscillators (NCO) and therefore their core is a Finite State Machine (FSM) driven by a clock signal, which can be a single- or a multi-phase one. Despite their name ADFS may include some basic analog blocks, e.g. a DLL to generate multiple phases from a single-phase reference clock, or, other simple blocks used to improve the output spectrum quality.

ADFS can be partially classified into Digital-to-Frequency Converters (DFC) and Digital-to-Period Converters (DPC) where the first ones typically are ADFS whose synthesized (average output) frequency is proportional to the Frequency Control Word (FCW), whereas, the second ones are ADFS whose synthesized (average output) period is proportional to the FCW. [The output is not a regular periodic waveform for most FCW values, so, the average output frequency is used defined as the average rate of output cycles.]

The core of DFC and DPC typically is a phase accumulator, which in DFC is similar to that used in standard Direct Digital Synthesizers (DDS), [1]. Typical examples of DFCs and DPCs are the Pulse Direct Digital Synthesizer (PDDS) [2], shown in Figs. 1, 4 and the Flying Adder (FA) synthesizer [3]-[8], shown in Fig. 6.

Additional advantages of ADFS compared to standard DDS are that they do not use a ROM Look Up Table (LUT) neither a DAC like standard DDS do, while they have similar frequency range, instantaneous frequency hopping, significantly lower power consumption, higher maximum operational frequency and require much smaller chip area.

Since DFC and DPC are essentially synchronous FSM their output pulses must begin and end at the rising (and/or falling) edges of the reference clock, clkf , or at the rising (and/or falling) edge of a clock-phase in the case of a multi-phase clock. This limitation implies

that only output frequencies of the form /clkf N (or /clkf M N⋅ , where M is the number of clock-phases) result in “perfect” periodic output waveform, i.e. when the DFC and DPC behave like integer frequency dividers. For all other synthesized (average) output frequencies, the output waveforms are irregular and the corresponding spectra contain strong spurious frequency components.

This paper reviews the developments in time-domain correction and spurs-suppression techniques for ADFS in an effort to identify their strengths and weaknesses and provide new research directions.

II. SPURS AND DETERMINISTIC JITTER IN ADFS DFC type ADFS are typically based on the phase accumulator

shown in Fig. 1, also called PDDS, [2] or on a variation of it.

Figure 1: Pulse DDS with overflow output

At the k-th rising edge of the clock (assume the register is rising-edge-triggered) the register’s value is ( )mod2n

kx k w= ⋅ and the

output is 1kv = when there is an overflow, i.e. when

( ) ( )( )div 2 1 div 2n nk w k w⋅ > − ⋅ , and 0kv = otherwise. Typical waveforms are shown in Fig. 2 along with the ideal waveform of the same output frequency and the values of the register.

2n

12n−

22n−

1τ 2τ 3τ 4τ

Figure 2: Typical waveforms of PDDS [modified figure from [16]]

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In Fig. 2 notice the time offsets jτ between the pulses of the ideal and those of the output waveform. The first ones appear when the continuous linear phase-segments cross 2n whereas the second ones appear at the first next rising edge of the clock.

The pulses of the overflow signal ( )v t are typically converted to a squarewave using a D-Flip-Flop with feedback as in Fig. 3 which behaves as a frequency divider by 2.

Figure 3: D-FF converts overflow signal to squarewave

Alternatively, one can use the MSB of the register as the output, as it is shown in Fig. 4. In this case the FCW must be 12nw −≤ .

Figure 4: Pulse DDS with MSB output

The spectrum of the output ( )y t has many strong spurs as shown in Fig. 5 in agreement with the irregular output ( )v t , Fig. 2.

Figure 5: Typical spectrum of MSB-output PDDS

The Flying Adder (FA) [3]-[8] is one of the popular DPC type ADFS. Its basic structure is shown in Fig. 6. Note that it requires a multi-phase clock ( 2m phases) which if not given, it must be generated using a PLL (e.g. with ring oscillator) or a DLL.

2m

Figure 6: The basic Flying Adder is an example of DPC type ADFS

Figure 7: The Flying Adder DPC: Ideal output, Real output y(t), and,

Combined edges of the multi-phase clock

As seen in Fig. 7, FA suffers from timing irregularity similar to that of PDDS, [6]. The spectrum of FA, has a large number of strong spurs as shown in Fig. 8 similarly to PDDS as well [8].

Figure 8: Typical spectrum of the Flying Adder (4-phase clock)

One would agree that although basic DFC and DPC, like the PDDS and FA can in many cases be useful in clocking digital circuits, their applicability to RF and wireless systems is probably limited if no care is taken to suppress the spurs in their spectra.

III. SPURS SUPPRESSION AND JITTER CORRECTION There are several approaches to reduce the timing irregularities of

ADFS and/or suppress the spurious spectral components of them. They can be roughly classified as follows.

A. Retiming using Analog Delay Elemen(s) The accumulator’s output (see Fig. 2) is passed through an

adjustable-delay element. Every pulse 1,2,3,...j = is delayed by

clk jT τ− , where jτ is the time elapsed between the rising edge of the j-th pulse of the ideal signal (appearing first) and that of the j-th pulse of the output as shown in Fig. 2.

When analog adjustable-delay element(s) is used, the high level architecture of the pulse retiming circuit is shown in Fig. 9. Note that the offset time clk jT τ− can be easily calculated by the support logic.

Figure 9: Typical pulse retiming using analog adjustable-delay element(s)

The adjustable transmission line approximation circuit in Fig. 10 has been proposed for implementing the delay element [9]-[10]. The main difficulty of this approach is to map the desired delay values to the delay control voltage of the DAC. Temperature and other variations would require further adjustments.

Figure 10: Transmission line approximation circuit for implementing the

delay element for pulse retiming [9]-[10]. [modified figure from [9]]

Another way for converting digital values clk jT τ− to delays is by charging a capacitor, from zero (or other fixed) initial condition, using a fixed current, up to a certain voltage level. As illustrated in Fig. 11 the capacitor starts charging up when the 1-st pulse of PDDS

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arrives; the threshold voltage 1u is chosen so that it takes time

1 1clkd T τ= − for the capacitor’s voltage to reach it; when the threshold is crossed, a mono-stable circuit is triggered and the capacitor is discharged, and so on.

Figure 11: A: capacitor’s voltage, B: PDDS output pulse sequence, C:

delayed pulses of (B).

Instead of adjusting the threshold voltage to get the desirable delay one can adjust the charging current (current switching circuits are popular in DAC). The concept has been used in [11]-[13].

B. Retiming using Digital Delay Line One can replace the analog adjustable delay in Fig. 9 with a

digital delay line as in Fig. 12, following [14]. Since the delay line has only a finite number of taps, certain quantization of the delay values are imposed (it depends on the frequency synthesized w.r.t. reference one). Delay quantization implies that this approach is conceptually a time-resolution enhancement rather that a complete retiming of the output signal.

Tuning the delay gates to achieve a specific delay value per tap may not be easy to do over a wide temperature range (and process variation in an integrated circuit design). Finally, the accumulated random delay due to the jitter of the delay gates (typically series of inverters) causes degradation of the signal.

Figure 12: Digital delay-line for pulse retiming [14]. (no phase-locking)

C. Time Resolution Enhancement using DLL To minimize the issues of delay variation over process and

temperature, and jitter, one can phase-lock the last tap to the reference clock as in Fig. 13. The concept was proposed in [15] and [16] for spurs suppression. To deal with the finite resolution of the digital delay line an additional random dithering mechanism was used, in both [15] and [16], which reduces the remaining spurs but also raises the noise floor as a side effect. The concept of DLL was also used in [17] as a coarse timing correction, supplemented by the free running digital delay line approach in Section III-B.

Figure 13: Phase-locked digital delay-line for pulse retiming, [14]-[17],

D. Cleanup PLL The approach of using a PLL to clean the spectrum of a signal

from far-out frequency spurs has been used successfully for decades [18]. In [19] it was proposed to do so for PDDS, as in Fig. 14.

Figure 14: PDDS followed by cleanup PLL, [19].

The idea here is that if the PLL has a linear Phase-Frequency Detector (PFD) (or a simpler Phase Detector) and the PLL’s filter (following the PFD) cutoff frequency is smaller than the offset frequency of the most near-in spur, as shown in Fig 15, then the output of the PLL is a clean signal. A similar concept has been used in [17] but with the PDDS used as a feedback divider inside a PLL.

Figure 15: The cleanup PLL acting as a narrow-band filter centered at the desirable (typically the average-) frequency component of PDDS’ output.

1) PLL Loop with Analog Phase-Error Correction An improvement of the cleanup PLL concept is shown in Fig. 16.

Figure 16: Cleanup PLL with timing error compensation in the PFD

In Section III-D our assumption was that PLL’s filter was narrow and steep enough to remove the spurious frequency components which are down-converted to baseband by the PFD. The requirements for the filter and the PLL in general can be alleviated if the architecture in Fig. 16 is used instead. Here the instantaneous non-zero output of the PFD, due to the timing irregularities of PDDS, is canceled by the DAC which is driven by the timing error calculator.

The concept is very similar to classical error compensation in Fractional-N PLL, [20], [21]. The architecture in Fig. 16 has been used in [9] and [22].

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E. Random Phase-Dithering Random phase-dithering is a classical approach for removing

periodic patterns and increasing effective resolution in standard DDS, Fractional-N PLLs and other devices. As a side effect it raises the noise floor, this is alleviated by noise shaping techniques, [23], [24].

Figure 17: PDDS with random phase dithering

A PDDS with phase dithering is shown in Fig. 17. The concept was proposed in [25] and has been used in several similar architectures including [15]-[16]. Moreover, a similar approach is used to reduce the spurious content of the Flying Adder [26].

IV. RESULTS OF THE APPROACHES Due to space limitation we consider results only of: approach C

with additional random dithering between the delay taps, shown in Fig. 18, 1-original spectrum, 2-with spur suppression, and approach E used for the FA in Fig. 18, 3-original, 4-with spur suppression.

Figure 18: Plots 1-without, 2-with approach C and randomization, [27].

Plots 3-without, 4-with approach E applied to the FA.

In both cases the randomization helps reducing the spurs level but raises the noise floor. It can be seen that the effectiveness of approaches A-E depends significantly on the specific parameters of the synthesizer and the ratio of the output to reference frequencies.

V. CONCLUSIONS A brief survey of spurs’ suppression and deterministic jitter

correction approaches for all-digital frequency synthesizers has been presented. Two major questions need to be addressed in the framework of nano-scale CMOS: A) What frequency synthesis requirements favor each of the approaches? B) How process and temperature variations impact each of the approaches and how can we compensate for them?

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