STATCOMDr. Biswarup Das

Department of Electrical Engineering

IIT Roorkee

12-pulse inverter using delta/open and star/open connection of six-pulse units.

12-pulse waveforms created from two sets of six-pulse waveforms

True 48 pulse configuration

True 48 pulse STATCOM waveform

Diagram of quasi-48 pulse STATCOM

Voltage waveforms of two six-pulse converters (V1Y, V1Δ) and

four phase-shifted 12-pulse converters (Va1, Va2, Va3, Va4)

Quasi-48-pulse STATCOM waveforms.

Multi-pulse STATCOM

• For true 48 pulse, 8 zig-zag transformers

with tertiary winding are needed

• In quasi 48 pulse, ordinary transformers

are sufficient

• Transformer complexity and cost is more

in true 48 pulse than in quasi 48 pulse

• Indirect control of multi-pulse STATCOM

Multi-level inverters

• Diode clamped

• Flying capacitor

• Cascaded H-bridge

H-Bridge Multilevel Inverter

Basic Module Output voltage

Constraint: S1 ≠ S2; S3 ≠ S4

Types of H-bridge Multilevel Inverters

1. Cascade H-Bridge

2. Hybrid H-Bridge

3. Quasilinear

4. New Hybrid (Trinary)

Cascade H-Bridge multilevel Inverter

Level Number= 2S+1

Where,

S= Number of stages

All DC source

voltages are of

equal ratings

Cascade H-bridge Inverter

a) Circuit diagram b) waveform showing 9-level converter phase voltage

Cascade H-bridge Inverter

• For an M-level inverter (M-1)/2 Full Bridge

Inverters (FBI) are required

• The output phase voltage is synthesized by

the sum of all inverter outputs

3- stage Cascade H-bridge

Possible combinations for 3-stage Cascade

H-bridge Inverter

VDC

Vout

-3V -2 V -1 V 0 V 1 V 2 V 3 V

1 V

1 V

1 V

N

N

N

N N 0

N 0 N

0 N N

N N P 0 0 N

N P N 0 N 0

P N N N 0 0

0 0 N P N P 0

N P 0 0 P N 0

P N P N 0 0 0

P 0 0 N P P

0 P 0 P N P

0 0 P P P N

0 P P

P 0 P

P P 0

P

P

P

Cascade seven level 3 phase inverter

Waveform of cascade seven level inverter

Hybrid (binary) H-Bridge Multilevel

Inverter

Level Number

= 2s+1 – 1

(a) 3-stage BMVSI (b) output waveform

Possible combinations for 3-stage

Hybrid H-bridge Inverter

VDC

Vout

-7 -6 -5 -4 -3 -2 -1 0 1 2 3

1 V

2 V

4 V

N

N

N

0

N

N

P N

N 0

N N

0

0

N

P N N

0 N P

N 0 N

0 0

N P

0 N

N P P

0 N P

0 0 N

0

0

0

P N N

0 P N

0 0 P

0 0

P N

0 P

P N P

P 0 N

0 P P

4 5 6 7

0

0

P

P N

0 P

P P

0

P

P

P

P

P

Binary seven level 3 phase inverter

Waveforms of binary seven level inverter

Advantages

• Stage with higher DC link voltage has Lower number of commutations

Lower associated switching loss

• Higher DC link voltage consists of lower switch frequency component (IGCT)

• Lower DC link voltage consists of higher switching frequency components (IGBT)

Quasi-linear multilevel inverter

3 stage quasi-linear inverter: a) circuit diagram b) waveform

Possible combinations for 3-stage

Quasilinear inverter

VDC Vout

-9 -8 -7 -6 -5 -4 -3 -2 -1

1V

2V

6V

N

N

N

0

N

N

P N

N 0

N N

0

0

N

P N

0 P

N N

0

P

N

P N

P N

N 0

0

N

0

P N

N 0

0 0

0 1 2 3 4 5 6 7 8 9

0

0

0

P N

0 P

0 0

0

P

0

P N

P N

0 P

0

N

P

P N

N 0

P P

0

0

P

P N

0 P

P P

0

P

P

P

P

P

Terniary multilevel inverter

3-Stage New Hybrid Inverter

Possible combinations for 3-stage Terniary

Inverter

VDC

Vout

-13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1

1V

3V

9V

N

N

N

0

N

N

P

N

N

N

0

N

0

0

N

P

0

N

N

P

N

0

P

N

P

P

N

N

N

0

0

N

0

P

N

0

N

0

0

0 1 2 3 4 5 6 7 8 9 10 11 12 13

0

0

0

P

0

0

N

P

0

0

P

0

P

P

0

N

N

P

0

N

P

P

N

P

N

0

P

0

0

P

P

0

P

N

P

P

0

P

P

P

P

P

V K(max) V out (max)Level number

Cascade VDCS VDC 2S + 1

Hybrid 2 S - 1 VDC (2S-1) VDC 2S+1 - 1

Quasi-linear 2 * (3 S-2) VDC (3S – 1) VDC 2*3S-1 + 1

New Hybrid 3S-1 VDC ((3S-1)/2) VDC 3S

Reference

1. Y. S. Lai and F. S. Shyu, “Topology for

hybrid multilevel inverter”, IEE proc.-Electr.

Power Appl., Vol. 149, No. 6, November 2002.

Page(s): 449-458.

Cascaded multilevel inverter

Solution procedure

Chain-link converter based STATCOM

Basic circuit

Voltage waveform of a 3 link (7 level) chain converter

(2N+1) level output phase voltage waveform of a CLS with “N” links per phase.

References

1. J. D. Ainsworth et al., “Static VAr compensator

(STATCOM) based on single-phase chain circuit

converters”, IEE Proc. Generation,

Transmission, Distribution, Vol. 145. No. 4, July

I998, pp: 381-386.

2. Nikunj M. Shah, Vijay K. Sood and Venkat

Ramachandran, “EMTP Simulation of a Chain-

Link STATCOM”, IEEE TRANSACTIONS ON

POWER DELIVERY,VOL. 23, NO. 4,OCTOBER

2008, pp: 2148-2159.

Basic indirect control scheme (Fig. HG_5.35)

Direct control scheme (Fig. HG_5.36)

Operating V-I characteristics of STATCOM (Fig. HG_5.37)

Loss Vs. output characteristics of a 48 pulse, 100 MVAR STATCOM

(Fig. HG_5.38)

Combined characteristics of a STATCOM-FC (Fig. HG_5.39)

Combined characteristics of a STATCOM-fixed reactor (Fig. HG_5.40)

Combined characteristics of a STATCOM-TSC-TCR SVC (Fig. HG_5.41)

Loss Vs. output characteristics of different static VAR generator systems

(Fig. HG_5.42)

General control scheme of a static VAR generator (Fig. HG_5.43)

Implementation of the slope in the V-I characteristics of a STATCOM

(Fig. HG_5.44)

V-I characteristics of a SVC and STATCOM (Fig. HG_5.45)

VAR reserve control

Diagrammatic representation of the concept of VAR reserve control (Fig. HG_5.56)

Equal area criterion to demonstrate improvement of transient stability with

shunt compensation (Fig. HG_5.5

Improvement of transient stability by STATCOM and SVC;

a) STATCOM and b) SVC (Fig. HG_5.62)

VS VR

P+jQ

jX

2 4 2 2 2( 2 ) 4 4

2

s s s

R

V QX V QXV P XV

Voltage stability limit of a radial line without any compensation

VS VR

P+jQ

jX

STATCOM

Voltage stability limit of a radial line with shunt compensation