State-Based Design Implementation issues

School of Electrical Engineering

Department of Electrical Engineering and Automation

ELEC 8102 Distributed and Intelligent Automation Systems

Valeriy Vyatkin, Igor Buzhinsky

Lecture plan

• Implementation of state-based design in PLCs– SFC– ST– UML SC– LD

• Use of counters and timers in the state-based design

• Initial state• Limitations

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Recap: finite-state machines (FSMs)

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• Initial state (shown with double circle)

• The next state depends on the current state and current input signals

• The outputs either depend on the current state and input signals (Mealy machines) or on the current state only (Moore machines)

• Which kind of state machine is shown on the left?

Recap: why state-based design

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Recap: why state-based design

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• Decomposing the program into meaningful parts whose correctness can be checked independently

• Also with formal verification methods!

• Graphical program representation• And, possibly, code generation from state diagrams

• State machines can also be used to represent specifications and plant/environment models

• Thus, consistency of notation

Tl

STATE

...

...

STATEi1

STATEiM

Ti1

TiM

To1

ToN

STATEoN

STATEo1

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• Tl – condition defining when the FSM remains in the state STATE

• It can be defined explicitly or implicitly (else)

successor states

predecessor states

Implementation of FSM with Boolean variables

𝑇! =#"#$

%

𝑇"&

Implementation algorithm

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1. Mark every state with a Boolean state variable, e.g., 𝑆𝑇𝐴𝑇𝐸!.

2. Define the state transition function (see the next slides).3. Assign output signals depending on the state (the one after

the transition). In Boolean logic: if 𝐼 is the tuple of input signals and 𝑠! is the 𝑗-th state, then 𝑜" ≔∑!#$% 𝑆𝑇𝐴𝑇𝐸! ⋅ 𝐺 𝐼, 𝑠! ‒ the logical sum on all states where the signal is to be TRUE.

4. Add initialization section defining which state is true initially and what are values of variables then.

Moore:𝑂! = 𝐺(𝑆!),𝑆!"# = 𝐹(𝐼! , 𝑆!).

where 𝑡 and 𝑡 + 1 are two consecutive moments of discrete time.

Mealy:𝑂! = 𝐺(𝐼!, 𝑆!),𝑆!"# = 𝐹(𝐼! , 𝑆!).

Definition of the state transition function F

Tl

STATE

...

...

STATEi1

STATEiM

Ti1

TiM

To1

ToN

STATEoN

STATEo1

The state transition function is the logical sum of conditions on all incoming arcs to the state including Tl.

where: + is logical OR, dot is logical AND, 𝑆𝑇𝐴𝑇𝐸!" - Boolean variables indicating activity of ”predecessor” states.STATE’ – state variable in the next scan,M – the number of transitions to STATE. N - the number of transitions from STATE. 𝑇!" - transition condition from a predecessor state 𝑆𝑇𝐴𝑇𝐸!" to STATE. 𝑇#$ - transition condition from STATE to the successor state 𝑆𝑇𝐴𝑇𝐸#$

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𝑆𝑇𝐴𝑇𝐸′ = 𝑆𝑇𝐴𝑇𝐸 ' 𝑇! +)"#$

%

𝑆𝑇𝐴𝑇𝐸"& ' 𝑇"&

𝑇!=*'#(

)

𝑇'*

Structured Text representation

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// InitialisationIF FirstScan THENS1 := 1; S2 := 0; S3 := 0;S1x := 1; S2x := 0; S3x := 0;MOVEF := 0; LED := 1;FirstScan := 0;

END_IF;// State transition function S2x := S2 AND NOT END

OR S1 AND START;S3x := S3 AND NOT HOME

OR S2 AND END; S1x := S1 AND NOT START

OR S3 AND HOME;// OutputsLED := S1x;MOVEF := S2x;// Next state variablesS1 := S1x; S2 := S2x; S3 := S3x;

RetractMove

END

S1

S3

LeftLED:=1

START HOME

MOVEF:=1LED:=0

MOVEF:=0

𝑆𝑇𝐴𝑇𝐸′ = 𝑆𝑇𝐴𝑇𝐸 - 𝑇! +/"#$

%

𝑆𝑇𝐴𝑇𝐸"& - 𝑇"&

S2

Ladder logic representation

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The same in Structured text:

S2x := S2 AND NOT ENDOR S1 AND START;

S3x := S3 AND NOT HOMEOR S2 AND END;

S1x := S1 AND NOT STARTOR S3 AND HOME;

LED := S1x;MOVEF := S2x;

S1 := S1x;S2 := S2x;S3 := S3x;

Table implementation of FSM

Inputs StatesSTART HOME END S1 S2 S3

1 0 0 0 X ... ...

2 0 0 1 X

3 0 1 0 S1

4 0 1 1 X

5 1 0 0 S2

6 1 0 1 S2

7 1 1 0 S2

8 1 1 1 x

Output LED=1 MOVEF=1

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State transition function F for the Cylinder2n

for n

bin

ary

inpu

ts

Fill the table and then update states and outputs according to it

Counters

There are three counter instructions in IEC 61131-3:

CTU - Count Up CounterCTD - Count Down CounterCTUD - Count Up/Down Counter

CTU

200

Load_Cnt

PV CV 178

QCU

R

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Counter Operation

Parameters:- IN/CU/CD = Count up/Down- Q/QU/QD = Comparison Output- R = Reset to Zero- LD = Load CV with PV- PV = Preset Value- CV = Count Value

...

...

CVPV|0

CUQUCDQD

LDR

Count Up/Down (CTUD) Counter

...INQ

CVPV|0

LD

...Count Down (CTD) Counter

...INQ

CVPV|0

R

Count Up (CTU) Counter...

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ExampleRequirement: Once the START button is pressed, the cylinder will need to shuttle back and forth 3 times.

To count the number of passes we need an integer variable which will be incremented every time cylinder reaches the “end” position. The variable will be compared with the desired number of passes (3) to decide whether to repeat or stop.

We use a counter object called CNT. CTU

3

CNT

PV CV

QCU

RESET

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Notation:• CNT.Q – is true if CNT.CV = 3 • CNT.CV is an integer variable• CNT.RESET – CNT.CV:=0

(and CNV.Q:=false)• CNT.CU – increment CV if it is

less than PV

Example

Notation for state diagrams: ®Op : do the operation Op once on entry to the state.

Rule for converting to Boolean equations: 1. For each counter add one invocation line before the

state transition section.

CNT(CU:= <C1>, RESET:= <C2 >; PV:= preset value); where: • C1 – logical sum of all states in which there is

®CNT.CU• C2 - logical sum of all states in which there is

®CNT.RESET

In ladder logic diagrams use the function block instead.

2. Use CNT.Q in state equations transition conditions 15

CTU

3

CNT

PV CV

QCU

RESET

Simplified Structured TextVARCNT: CTU; // Up counter with

// detection of// input rising edges

FirstScan: BOOL := 1;END_VAR

// InitialisationIF FirstScan THENS1 := 1; S2 := 0; S3 := 0;S1x := 1; S2x := 0; S3x := 0;MOVEF := 0; LED := 1FirstScan := 0;

END_IF;

// State transitions function S2x := S1 AND START OR S2 AND NOT ENDOR S3 AND HOME AND NOT CNT.Q;

S3x := S2 AND END OR S3 AND NOT HOME; S1x := S3 AND HOME AND CNT.QOR S1 AND NOT START;

// Invoking the counter object;CNT(CU:=S3, RESET:=S1; PV:=3);

// OutputsLED := S1;MOVEF := S2;S1 := S1x; S2 := S2x; S3 := S3x;

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Ladder Diagram

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// State transitions function S2x := S1·START + S2·¬ END+ S3·HOME·¬CNT.Q;

S3x := S2·END + S3·¬HOME;

S1x := S3·HOME·CNT.Q+ S1·¬ START;

// Invoking the counter// objectCNT(CU:=S3x,

RESET:=S1x;PV:=3);

Timer

PLC program

Configure and activate

Timer instance

Activation condition fulfilled, starts ticking

... ...

t

Time expired, stopped ticking, program can take action

Timer is an object, an instance of a function block

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Pulse Timer TP

As can be seen from Figure timers of type TP are not "retriggerable". If the intervals between the input pulses at IN are shorter than the pre-set time period, the pulse duration still remains constant (see period [t2; t2+PT]). Timing therefore does not begin again with every rising edge at IN.

TP

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TON/ TOFThe on-delay timer TON supplies the input value IN at Q with a time delay when a rising edge is detected at IN. If input IN is "1" only for a short pulse (shorter than PT), the timer is not started for this edge.The elapsed time can be read off at output ET.

The off-delay timer TOF performs the inverse function to TON i.e. it delays a falling edge in the same way as TON delays a rising one.The behaviour of the timer TOF if PT is modified during timer operation is implementation-dependent.

TON TOF

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Cylinder delay in the extended position

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// State transitions

S2’ :=S1·START + S2· ¬ END;S4’ :=S2·END + S4 · ¬ T1.Q; S1’ :=S3·HOME + S1 · ¬ START;S3’ :=S4·T1.Q + S3 ·¬HOME;

// Timer activation in S4

T1(IN: S4’, PT: #5s);

Rule for converting to Boolean equations: 1. Declare TON timer instance for each delay. 2. For each timer TIMER add one invocation line

before or after the state transition section.

TIMER(IN:= <C1>; PT:= preset time); where: C1 – logical sum of all states in which there is ®TIMER.IN(preset time)

In ladder logic diagram use the function block instead with the rung connected to input IN implementing the C1 condition.

3. Use TIMER.Q in state equations transition conditions as a condition of timer expiration.

LD implementation

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// State transitions

S2’ :=S1·START + S2· ¬END;S4’ :=S2·END + S4· ¬T1.Q; S1’ :=S3·HOME + S1· ¬START;S3’ :=S4·T1.Q + S3· ¬HOME;

// Timer activation in S4

T1(IN: S4’, PT: #5s);

Example: blinking lampRequirement: Make the LED of the START button blinking while the cylinder is in the leftmost state. Implement controller in LLD.To implement the blinking, we need to introduce a “sister” state to S1, where the LED will be reset for some time, say 200 ms.

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RetractMove

END

S1

S3

Left

START HOME

MOVEF:=1LED:=0 MOVEF:=0

OffS2 S4T1.Q

®T2.IN(200ms)LED:=0

T2.Q

®T1.IN(200ms)LED:=1

Example: heating ovenVerbal specification: The oven is started with a Start button that seals in the Auto mode. This can be stopped if the Stop button is pushed. (Remember: Stopbuttons are normally closed.)When the Auto goes on, the horn is used to sound for the first 10 seconds to warn that the oven will start, and after that the horn stops and the heating coils start. When the oven is turned off the fancontinues to blow for 300s, or 5 minutes, after.

START STOP

HORN

FANCOIL

TON

PT ET

QIN

TOF

T2

PT ET

QIN

T1

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Timing Diagram

START STOP

HORN

FANCOIL

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Timing diagram vs. Specification

The oven is started with a Start buttonthat seals in the Auto mode. This can be stopped if the Stop button is pushed.(Remember: Stop buttons are normally closed.)When the Auto goes on, the horn is used to sound for the first 10 seconds to warn that the oven will start, and after that the horn stops and the heating coils start. When the oven is turned off the fan continues to blow for 300s or 5 minutes after.

Note: 1) What will happen if Start is pressed here?

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Let us follow the diagram … (naive engineering)PROGRAM OvenSTVAR

HeatTimer: TP;CoolTimer: TOF;RE: R_TRIG;FE: F_TRIG;Edge: BOOL;

END_VARRE(CLK:=Start); // rising edge of Start is detectedIF RE.Q THEN

HeatTimer(IN:=Start, PT:=T#10S); Horn := 1;

END_IF;IF HeatTimer.Q THEN

Horn := 0; HeatingCoils := 1; Fan := 1;

END_IF;FE(CLK := Stop); // falling edge of Stop is detectedIF FE.Q THEN

HeatingCoils := 0; CoolTimer(IN:=NOT Stop, PT:=T#5M);

END_IF;IF NOT CoolTimer.Q THEN

Fan := 0; END_IF;

Notes1. Why do we use TP timer?2. Detecting rising/falling edge

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State Machine

Timer T1 starts on the rising edge of the state activity flag

Transition occurswhen timer expires

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From State Machine to Ladder Diagram

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Complete the Boolean functions implementation:

Limitations of State-based Design Approach

• Concurrent processes – need to decompose to smaller subsystems– how to handle their interaction and

coordination?• Hard to define stable states

– e.g., the Oven example

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Initialization – First scan

VARFirstScan: BOOL := 1;

END_VAR

// InitializationIF FirstScan THEN

// Put here setting of the first // state in state machine, etc.

FirstScan:=0;END_IF;

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1) Declare FirstScan Boolean variable and initialise it to TRUE.

2) Add POU INIT and put its call first in the MainTask.

3) Add initialisation code to INIT as follows:

Initialization in Application Design

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A new initial state Startup is introduced.

Problem: The machine may require positioning to the intial state before starting the operation

// InitialisationIF FirstScan THENS0 := 1; S1 := 0;S2 := 0; S3 := 0;S0x := 1; S1x := 0;S2x := 0; S3x := 0;MOVEF:=0; LED:=1;FirstScan :=0;

END_IF;// State transition function S2x := S2 AND NOT END OR S1 AND START;S3x := S3 AND NOT HOME OR S2 AND END; S1x := S1 AND NOT START OR S3 AND HOME

OR S0 AND HOME; S0x := S0 AND not HOME;// OutputsLED := S1x;MOVEF := S2x;// Next state variablesS0 := s0x; S1 := S1x;S2 := S2x; S3 := S3x;

OTHER SOLUTIONS?

Warning: do not overcomplicate things!

• State-based design is used to simplify things, not to complicate!

• It is reasonable to use Boolean variables to encode states only if this is really needed

• Otherwise, using integers/enumerations to encode states is more comprehensible and less error-prone– IF-ELSIF-ELSE (“switch” in C-like languages) pattern

from the previous lecture– In general purpose languages, maybe you’d like to

use the State design pattern in similar situations

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Summary

• State-based design implementation via Boolean logic– Reasons– Methods

• Use of standard functional elements in state-based design (implemented via Boolean logic)

• Limitations of state-based design and some workarounds

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