static characteristics - 4luiz.santos/ine5442/slides/aulas23-24.pdf · static characteristics - 4...
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EEL7312 – INE5442Digital Integrated Circuits
1Source: Rabaey
Static characteristics - 4
Vin Vout
VDD-VGSp
+-
VDSp
+
IDp
IDn
IDn
Vout
Vin= 2.5
2
1.5
Vin= 0
0.5
1
NMOS
Vin= 0Vin= 0.5
Vin= 1Vin= 1.5
Vin= 2Vin= 2.5
11.5
PMOS
VTC
Vout
0 .5
11.
52
2.5
NMOS resPMOS off
NMOS satPMOS sat
NMOS offPMOS res
NMOS satPMOS res
NMOS resPMOS sat
in0.5 1 1.5 2 2.5 V
EEL7312 – INE5442Digital Integrated Circuits
2Source: Rabaey
Static characteristics - 5
Vin Vout
VDD-VGSp
+-
VDSp
+
IDp
IDn
IDn
Vout
Vin= 2.5
2
1.5
Vin= 0
0.5
1
NMOS
Vin= 0Vin= 0.5
Vin= 1Vin= 1.5
Vin= 2Vin= 2.5
11.5
PMOS
Short-circuit current
IDD
V in0.5 1 1.5 2 2.5
0.5
11.
52
2.5
EEL7312 – INE5442Digital Integrated Circuits
3Source: Weste & Harris
Static characteristics - 6
Vin Vout
VDD-VGSp
+-
VDSp
+
IDp
IDn
Switching threshold - 1
EEL7312 – INE5442Digital Integrated Circuits
4Source: Weste & Harris
Static characteristics - 7
1DSVλ <<
;1 1M
Tn Tp DDDn Dp
r rVr r
V V VI I+
= → = ++ +
Vin Vout
VDD-VGSp
+-
VDSp
+
IDp
IDn
Switching threshold - 2
Experimental determination of VM: short-circuit between input and output
Vin
Vout
VM
( ) ( ) ( )
( ) ( ) ( )
2 2
22
12 2
12 2
n nn DSn
n n
p pp DSp DD
p p
Dn Tn M TnGSn
Dp Tp M TpGSp
k W k WVL L
k kW WVL L
I V V V V
I V V V V V
λ
λ
⎞ ⎞⎛ ⎛= + ≅⎜ ⎟ ⎜ ⎟⎝ ⎝⎠ ⎠
⎞ ⎞⎛ ⎛= + ≅ −⎜ ⎟ ⎜ ⎟⎝ ⎝⎠ ⎠
− −
− −
Usually
( )( )
/
/p p
n n
W Lkr
k W L=
Example: VDD=2.5 V, VTp=-0.4 V, VTn=0.43 V. What is VM for r= 0.5, 1.0, and 1.5? Answer: VM=0.98, 1.26, and 1.43 V, respectively.
EEL7312 – INE5442Digital Integrated Circuits
5Source: Weste & Harris
Static characteristics - 8 Noise margins - 1
Vin Vout
VDD-VGSp
+-
VDSp
+
IDp
IDn
EEL7312 – INE5442Digital Integrated Circuits
6Source: Rabaey
Static characteristics - 9 Noise margins - 2
Vin Vout
VDD-VGSp
+-
VDSp
+
IDp
IDn
Approximate calculation of VIL and VIH
VOH
VOL
Vin
Vout
VM
VIL VIH
For regeneration -g>1, g is the gain in transition region
EEL7312 – INE5442Digital Integrated Circuits
7Source: Rabaey
Static characteristics - 10 Scaling the supply voltage
Vin Vout
VDD-
VGSp
+-
VDSp
+
IDp
IDn
0 0.05 0.1 0.15 0.20
0.05
0.1
0.15
0.2
Vin (V)
Vo
ut (
V)
0 0.5 1 1.5 2 2.50
0.5
1
1.5
2
2.5
Vin (V)
Vo
ut(V
)
Effects of supply voltage reduction: • Energy dissipation decreases but gate delay increases• dc characteristic becomes more sensitive to variations in device parameters• Signal swing reduces making the design more sensitive to external noise sources that do not scale
EEL7312 – INE5442Digital Integrated Circuits
8
Impact of Process Variations
0 0.5 1 1.5 2 2.50
0.5
1
1.5
2
2.5
Vin (V)
V out(
V)
“Good” PMOS“Bad” NMOS
Good NMOSBad PMOS
Nominal
Source: Rabaey
Static characteristics -11
WkL
β ′=Notes: 1. k’n≈ 2 to 3 k’p2. For βn=βp and VTp=-VTn, VM=VDD/2
Source: Uyemura
EEL7312 – INE5442Digital Integrated Circuits
9
Dynamic operation - 1
M N
v I v
O
M P
C
V = 5 VDD
(a)
M N
v = 5 VI v (0+) = 5V
O
C
(b)
0 V
+ 5V
0t
vI
0 V
+ 5V
0t
vO
High-to-low output transition in a CMOS inverter
C: load capacitance + interconnect capacitance + capacitances associated with the inverter transistors
Source: Jaeger
EEL7312 – INE5442Digital Integrated Circuits
10Source: Jaeger
Dynamic operation - 2
C: load capacitance + interconnect capacitance + capacitances associated with the inverter transistors
M N
v I v
O
M P
C
V = 5 VDD
(a) (b)
V = 0 V I
M P
v (0+) = 0VO
C
V = 5 VDD
0 V
+ 5V
0t
vI
0 V
+ 5V
0t
vO
Low-to- high output transition in a CMOS inverter
EEL7312 – INE5442Digital Integrated Circuits
11Source: Uyemura
Dynamic operation - 3
tPHL tPLH
EEL7312 – INE5442Digital Integrated Circuits
12
Dynamic operation - 4
0/ 2
out DD
PHL out DD
t V Vt t V V= → == → =
Propagation delay - 1
0 VDS(V)I D
(A) VGS= VDD
VDDVDD/2
VGSn=VDD Vout
VDD
+VDSn
__
ID IC
outD C
dVCdt
I I= = −
( )
/ 2
0
/ 2
/ 2
1/ 2
PHL DD
DD
DD
DD
t Vout DD
PHLDavV
V
Dav D DS DSDD V
D
dV CVdt C tI
I I V dVV
I= − → =
=
∫ ∫
∫
EEL7312 – INE5442Digital Integrated Circuits
13
Dynamic operation - 5
( )
( )
2
2
for 2
/ 2 for
nDS
n
n DS DS DSn
D Tn TnGS GS
D Tn TnGS GS
k W VL
Wk V V VL
I V V V V
I V V V V
⎞⎛≅ >⎜ ⎟⎝ ⎠
⎞⎛ ⎡ ⎤≅ − ≤⎜ ⎟ ⎣ ⎦⎝ ⎠
− −
− −
Propagation delay - 2
( )2
/ 2 / 2 ;
2
DD DDPHL
nDav
n
PHL
nn
D DDD Tn
C CtW
V CVtk WI
LLkV VV
≈⎞⎛
⎜ ⎟
= ≈⎞⎛
⎜ ⎟⎝ ⎠ ⎝ ⎠
−
0 VDS(V)I D
(A) VGS= VDD
VDDVDD/2
Let us assume that ( )2 and that 2n
Dsat DDn
Dav DD Tn Tnk WI V
LI V V V⎞⎛≅ = >>⎜ ⎟
⎝ ⎠−
In this case we have
( )/ 2
/ 2
1/ 2
DD
DD
DDPHL
DavV
Dav D DS DSDD V
CVtI
I I V dVV
=
= ∫
VDD
Vout
Vin= VDD
CIav
Source: Rabaey
Approach 1Approach 1
EEL7312 – INE5442Digital Integrated Circuits
14
Dynamic operation - 6
( )2and
2that p
Dsat DDp
Dav DD Tp Tpk WI V
LI V V V⎞⎛≅ = >> −⎜ ⎟
⎝ ⎠+
Propagation delay - 3
( )2
/ 2 / 2 ;
2
DD DDPLH
pDav
n
PLH
pp
D DDD Tp
C CtW
V CVt k WILL
kV VV≈
⎞⎛⎜ ⎟
= ≈⎞⎛
⎜ ⎟⎝ ⎠ ⎝ ⎠
+
Comments: • kn≈2-3 kp, kn,p=μn,p ·Cox• Increasing VDD reduces tp but power goes up• tPLH can be ≈ tPHL by making (W/L)p≈2-3(W/L)n BUT C is dependent on transistor dimensions• C includes load (fan-out), wire, inverter “self-capacitance”• C is non linear
VDD
Vout
Vin= VDD
C
Iav
Source: Rabaey
2PLH PHL
Pt tt +
=
PHL
nn
DD
CtWkL
V≈
⎞⎛⎜ ⎟⎝ ⎠
Approach 1Approach 1
EEL7312 – INE5442Digital Integrated Circuits
15
Dynamic operation - 7 Propagation delay - 4
Source: Rabaey
EEL7312 – INE5442Digital Integrated Circuits
16
Dynamic operation - 8
( )1
0DS
Don n DD Tn
nDS V
dI WR k V VdV L
−
=
⎞⎛= = −⎜ ⎟⎝ ⎠
Propagation delay - 5
Modeling capacitor discharge as in an RC circuit!
Source: RabaeyPHL
nn
DD
CtWkL
V≈
⎞⎛⎜ ⎟⎝ ⎠
Approach 2Approach 2
VDD
Vout
Vin = VDD
Ron
CL
tpHL = f(Ron.CL)= 0.69 RonCL
t
Vout
VDD
RonCL
1
0.5
ln(0.5)
0.36
What’s Ron?
0 VDS(V)
I D(A
) VGS= VDD
VDDVDD/2
Approach by Approach by UyemuraUyemura
( )012on midR R R≡ +
1oR−
Approach by Approach by RabaeyRabaey
1midR−
EEL7312 – INE5442Digital Integrated Circuits
17
Dynamic operation - 9
( )1, ( ) ( ) ( )
( )0
( )
DS
Don n p n p DD Tn p
n pDS V
dI WR k V VdV L
−
=
+⎞⎛= = −⎜ ⎟
⎝ ⎠
Propagation delay - 6
Source: Uyemura
VDD
Vout
Vin = VDD
Ron
CL
tpHL = 0.69 Ron,nCLtpLH = 0.69 Ron,pCL
Approach by Approach by UyemuraUyemura
( ) ( )0.69 1 1
2 2PHL PLH L
P
n DD Tn p DD Tpn p
t t CtW Wk V V k V VL L
+
⎡ ⎤⎢ ⎥+ ⋅ ⎢ ⎥= = +
⎞ ⎞⎛ ⎛⎢ ⎥−⎜ ⎟ ⎜ ⎟⎢ ⎥⎝ ⎝⎠ ⎠⎣ ⎦
0.69 1 1[ ]2
LP
DDn p
n p
CtW WV k kL L
⋅≈ +
⎞ ⎞⎛ ⎛⎜ ⎟ ⎜ ⎟⎝ ⎝⎠ ⎠
EEL7312 – INE5442Digital Integrated Circuits
18
Experimental setupDynamic operation - 10
S
G B
+
-
VPULSE
D
2
3
1
1
+
VDD = 5.0 V
-
S
G BCL
0
0
EEL7312 – INE5442Digital Integrated Circuits
19
Dynamic operation - 11
Inverter Propagation Delay * this is the Propagationdelay.cir file* PMOS transistor description MP 3 2 1 1 modelp W=2u L=1u.model modelp pmos (level=1 VT0=-0.65 TOX=7.5n KP=60u lambda=0.0)* NMOS transistor descriptionMN 3 2 0 0 modeln W=2u L=1u.model modeln nmos (level=1 VT0=0.5 TOX=7.5n KP=150u lambda=0.0)* dc sourcevDD 1 0 dc 5.0*load capacitanceCL 3 0 0.01p*signal source v0 2 0 dc 0 pulse 0 5 0 1ps 1ps 200ps 400ps.end
EEL7312 – INE5442Digital Integrated Circuits
20
Dynamic operation - 12
SpiceOpus (c) 6 -> source Propagationdelay1.cir SpiceOpus (c) 7 -> tran 1ps 500ps SpiceOpus (c) 8 -> setplot
new New plot Current tran2 Inverter Propagation Delay (Transient Analysis)
tran1 Inverter Propagation Delay (Transient Analysis) const Constant values (constants)
SpiceOpus (c) 9 -> setplot tran2 SpiceOpus (c) 10 -> plot v(2) v(3) xlabel t[s] ylabel 'Input, Output [V]'
EEL7312 – INE5442Digital Integrated Circuits
21
Dynamic operation - 12
Why?tPHL≈2.5·tPLH Why?
EEL7312 – INE5442Digital Integrated Circuits
22
Dynamic operation - 14
Simulate the transient response of the inverter of the previous exercise for fan-outs of one and two inverters
Exercise
EEL7312 – INE5442Digital Integrated Circuits
23
Dynamic operation - 15
Design for PerformanceKeep capacitances smallIncrease transistor sizes (W)
watch out for self-loading!Increase VDD (????)
EEL7312 – INE5442Digital Integrated Circuits
24
Dynamic operation - 16
Design for PerformanceIncrease VDD (????)
0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.41
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VDD
(V)
t p(n
orm
aliz
ed
)
* Velocity saturated devices
Source: Rabaey
EEL7312 – INE5442Digital Integrated Circuits
25
Dynamic operation - 17
Increase transistor sizes (W)watch out for self-loading
Design for Performance
tPLH
tPHLtPLH0
tPHL0
Propagation delays vs. load capacitance 2 4 6 8 10 12 142
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8x 10
-11
S
t p(s
ec)
(for fixed load)
Self-loading effect:Intrinsic capacitancesdominate
Source: Uyemura Source: Rabaey
min
min
WL
min
min
SWL
EEL7312 – INE5442Digital Integrated Circuits
26
Dynamic operation - 18Design for Performance
Source: Rabaey
Propagation delays vs. PMOS-to-NMOS transistor ratio β=Wp/Wn
1 1.5 2 2.5 3 3.5 4 4.5 53
3.5
4
4.5
5x 10
-11
β
t p(s
ec)
tpLHtpHL
tp
EEL7312 – INE5442Digital Integrated Circuits
27
Dynamic operation - 19
Source: Rabaey
t pH
L(ns
ec)
0.35
0.3
0.25
0.2
0.15
trise (nsec)10.80.60.40.20
Impact of Rise Time on DelayImpact of Rise Time on Delay