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Statistical Metrology - Quantifying,Modeling, and Assessing the Impact ofSpatial Variation in SemiconductorManufacturing

PersonnelD. Ouma, T. Park, V. Mehrotra, T. Tugbawa, C. Oji,J. Yoon, B. Lee, B. Stine, and R. Divecha(D. Boning and J. Chung)

SponsorshipDARPA, AASERT, and ARO

As device and interconnect dimensions continue to scalebelow quarter-micron dimensions, maintaining processand structure uniformity at each processing step isincreasing in importance and difficulty. Yield loss due tosystematic sources of variation will begin to supersedeloss due to particle defects and random sources ofvariation. Circuit performance will also become increas-ingly limited by device and interconnect variation.

Statistical metrology is a new methodology we aredeveloping to quantify, model, and understand theimpact of spatial variation in semiconductor processesand device/interconnect structures. Key elements of themethodology include test structures, experimentaldesigns, and measurement methods to gather the largevolumes of data needed for statistical analysis; thedevelopment of algorithms and tools to decompose andidentify variation sources; modeling methods to capturethe systematic elements of device or interconnect varia-tion (particularly as a function of layout parameters); andCAD tools and methods to understand the impact ofsuch variation on circuit performance and yield.

The application of these methods have been in twoprimary areas: pattern dependencies in Chemical-Mechanical Polishing (CMP), and variation in polysiliconand metal linewidths. The following abstracts summa-rize work on methods for rapid characterization andmodeling of CMP in several process application areas,including metal dielectric (oxide) polishing, ShallowTrench Isolation (STI) formation, and in copper dama-scene polishing. Finally, development and application ofCAD tools which utilize variation models (such as thosegenerated in the above experiments) to study the impactof variation on circuit performance is summarized.These studies are deeply collaborative with partners atTexas Instruments, Sandia National Laboratories,Applied Materials, Hewlett-Packard, PDF Solutions,Digital Semiconductor, Lucent Technologies, and LSILogic. ❏

The CMP Characterization Mask Set

PersonnelD. Ouma, B. Stine, and T. Park(D. Boning and J. Chung)

SponsorshipDARPA, ARO, Intel, Sandia National Laboratories,Hewlett Packard, and SEMATECH

In order to enable the characterization and modeling ofpattern dependencies in oxide CMP (as well as otherCMP processes), we have designed the CMP Character-ization Mask Set (Figure 1). The masks are intended tofacilitate rapid CMP consumable, process, and toolcharacterization and evaluation. Each mask is targetedtoward an individual source of pattern dependentvariation. To this end, four separate single-layer maskshave been designed to probe structure area, patterndensity, line pitch, and structure aspect ratio effects,respectively. The masks support simplified metrologytools and techniques including optical film thickness andprofilometry measurements. Each mask is designed toproduce a 1.2 cm x 1.2 cm die; larger versions(2.0 cm x 2.0 cm) of the density, pitch and area maskshave also been made available.

Fig. 1: CMP Characterization Mask Set.

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The first mask, the area mask, has patterned structureswith areas ranging from 10 x 10 micrometers to 3 x 3millimeters across a variety of pattern densities achievedby altering the fill pattern inside each structure. Inaddition to the area structures, there are also structuresto test the role of geometric orientation (horizontal linesversus vertical lines).

The pitch mask is the second mask. The density of eachstructure is fixed at 50% (equal linewidth and linespace),and the pitch is varied from 2 to 1000 micrometers for atotal of 36 structures per die. With the exception of thestructures with a pitch less than 20 micrometers, eachstructure is 2 x 2 millimeters in size. Features with apitch of 20 micrometers or less are lumped into a single2 mm x 2 mm structure. There are also spatial replicatesfor many of the structures so that pitch effects can beseparated from purely spatial effects.

In the density mask, the third mask, the pattern density(the ratio of raised metal area in each structure to thetotal area of each structure) was varied systematicallyfrom 4% to 100% from lowest in the lower left corner togreatest in the upper right corner while the pitch of eachstructure was fixed at 250 mm. A total of 25 structureseach 2 mm x 2 mm are arranged in a 5 x 5 grid, inaddition to a border region which extends 1 mm fromthe edge of the 25 structures to act as a buffer. Withoutthe border, structures with the lowest density wouldcontact structures with the highest density (on neighbor-ing die) and interact strongly.

The fourth mask is designed to explore the role of theratio of perimeter to area. A total of 8 structures repli-cated twice are designed. In addition, each set of 16structures is replicated six times across the die but withdifferent spacings between structures ranging linearlyfrom 10 to 60 micrometers for a total of 96 structures.

Figure 2 shows the results of oxide thickness variationmeasured and extracted for each mask usingprofilometry in process experiments using two differentpolishing pads – a key consumable in CMP: the IC-1400and IC-2000. Several striking results are readily seen. Wefind that pitch and perimeter/area ratio have almost noimpact on polishing performance, while density has alarge linear effect on the final oxide thickness. Finally,structure area size has no clear impact once the densityvariations have been accounted for. The mask set thusenables simple empirical modeling, and is being used toextract key empirical parameters (such as planarizationlength) needed in analytical/physical modeling of theprocess. Through on-going work with the SEMI CMPstandards committee, we hope to establish the character-ization mask set and analysis procedures as a standardvehicle for evaluating CMP consumables, processes, andtools. ❏

Fig. 2: Empirical results from CMP characterization mask set.

189

An Integrated Characterization and Modeling Methodology forCMP Dielectric Planarization

PersonnelD. Ouma, B. Lee, C. Oji, and B. Stine(D. Boning and J. Chung)

SponsorshipDARPA, Texas Instruments, and PDF Solutions

Efficient chip-level CMP models are required to predictdielectric planarization performance for arbitrary layoutsprior to CMP. We are developing an integrated calibra-tion and modeling methodology for oxide planarizationwhich extends previous work in several important ways.First, we have developed improved characterizationmethods for model calibration, including new short flowtest masks and simplified planarization model parameterextraction. Second, we have developed an efficientphysically motivated density calculation and integrationwith a planarization model for prediction of oxidethickness above and between metal structures across theentire die. Predictions based on the model show excel-lent agreement when applied to layouts not used inmodel calibration.

In previous work, we have developed an analytic modelfor oxide CMP based on an effective layout densitycalculation. The critical parameter in this model thenbecomes the “planarization length” or method fordetermining the effective density. As shown in Figure 3,a new variant of mask sets have been designed whichenable this planarization extraction using abrupt “stepdensity” changes in the layout. Using experimentalmeasurements from wafers fabricated and polished with

Fig. 3: Characterization masks showing lines along which optical measurements were taken for model calibration (L1 and L2)and verification (L3-L6). Mask 1 was used for calibration and Mask 2 for verification of the modeling methodology.

Fig. 4: 1-D cross-section of an elliptic weighting filter. The charac-teristic length is defined as the section length when the relative weighthas dropped to 2/π. The filter shape corresponds to the deformationprofile of an elastic material under distributed load in a circle ofradius L/2.

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these masks, we are able to extract a “planarizationresponse function” as shown in Figure 4. Using thisweighting function, we are able to calculate an effectivepattern density for a given layout, such as the densitypattern shown in Figure 5 for Mask 1.

Using the improved extraction and planarization re-sponse function, excellent predictions of oxide polishingperformance are possible, as shown in Figure 6 (for theoxide thickness along cut lines shown in Figure 3). ❏

Fig. 6: Model prediction for ‘‘up’’ areas polished under process a fordifferent times. The elliptic weighting filter length is 3.80 mm.

Fig. 5: Effective pattern density optainedwith an elliptic weighting filter.

Layout Pattern Dependencies inChemical Mechanical Polishing forShallow Trench Isolation (STI)

PersonnelD. Ouma, T. Park, and J. Yoon(D. Boning and J. Chung)

SponsorshipDARPA, Applied Materials, andSandia National Laboratories

Shallow Trench Isolation (STI) is emerging as theisolation methodology of choice as the drive for devicedensity intensifies. However, solution of layout patterneffects at the CMP planarization phase is critical to cost-effective single-mask STI processes. Pattern effects inSTI are particularly severe and complex; it is firstmanifest at the overburden oxide polish phase resultingin a nonuniform time-to-reach the nitride capping layeracross the die. This necessitates over polishing tocompletely remove the oxide and ensure completenitride stripping. The over-polishing together withhigher oxide polish rate results in substantial dishing ofthe trench oxide in dense trench regions and rounding ofsilicon nitride around the trenches. In order to controland account for the pattern dependencies, understand-ing of the polish mechanism in both phases is needed.

The goal of this project is to study and model the patterndependencies exhibited at the two polish stages. Usinga dedicated mask to delineate the specific patterndependencies, the study will explore a range of polish-ing process conditions and consumables such as padsand slurries. Different oxide deposition techniques willalso be examined; in particular, the oxide topographygenerated by HDP plasma versus TEOS deposition isimportant. Model development will begin with exten-sions to existing oxide polish models to incorporatefinite pad bending and explicit quantification of thechemical effect of the slurry. Greater attention will alsobe paid to hydrodynamic erosion which may play agreater role once the overburden oxide is polished. Theend goal is to generate die and wafer-level modelsapplicable to this composite material structure. ❏

191

Modeling the Effect of Interconnect Variation on Circuit Performance

PersonnelB. Stine and V. Mehrotra(D. Boning and J. Chung)

SponsorshipDARPA, ARO, PDF Solutions, Intel, and IBM

In order to study the impact of spatial and pattern-depen-dent variation on circuit performance, CAD tools must beextended and integrated in innovative ways. In this work,we are developing the CAD infrastructure to study deviceand interconnect variation (both within-wafer and within-die variation) impact on circuit performance. The method-ology is also being applied to understand the circuit impactfor specific important circuit families such as high speedmicroprocessors, ASICs, etc.

One such case study is a study of the impact of oxidethickness variation resulting from CMP on circuit perfor-mance. A hypothetical chip floorplan is shown in Figure 7(top), where the goal is to carry the clock signal generatedat the center of the chip along the four different paths insuch a way that no clock skew results. Unfortunately, themetal clock paths lie over regions of different underlyingcircuit or metal density. For example, path 1 runs overrandom logic (with perhaps a 30% density), and then overembedded memory with a higher density of perhaps 50%.Path 3, on the other hand, lies entirely over 30% localdensity.

This layout density difference will result in non-idealpolishing of the interlevel dielectric between the clock linemetal layer and the circuit metal layers, as shown in thelower part of Figure 7. As a result, the ILD thickness alongthe clock paths, as well as the layer to layer capacitancethose paths experience, will be substantially different, asshown in Figure 8 (top). This disparity can be expected tohave an impact on the resulting clock skews; as shown inthe lower part of Figure 8, for example, the differencebetween the desired and actual timing for path 3 is about17% in this example.

In addition to methods for modeling and understandingspatial variation impact on circuit performance, methodsare also being explored to reduce that variation. In particu-lar, “dummy fill” methods which insert non-active metallines or structures in a metal layer have been analyzed, sothat the density can be made more uniform at the sametime as the capacitance impact is minimized. ❏

Fig. 7: Hypothetical balanced H-bar clock tree floor plan (above);corresponding predicted ILD thickness map (bottom).

Fig. 8: Resulting ILD thickness and capacitance alongclock paths (top); resulting clock skews (below).

192

Novel Methods for Run by Run ProcessControl

PersonnelT. Smith and E. Stuckey(D. Boning)

SponsorshipSEMATECH, NSF, and SRC

Novel methods are being explored for the run by runcontrol of semiconductor fabrication processes. In suchapproaches, periodic recipe modifications from one runto the next are made in order to maintain specifiedquality, throughput, environmental, and other objectives.Implementation and comparison of an ExponentiallyWeighted Moving Average (EWMA) controller, aPredictor-Corrector Controller (PCC), and ArtificialNeural Network (ANN) controllers have been accom-plished. These methods are explored with respect to theirstability, responsiveness (optimal or otherwise), ability toincorporate practical issues and their applicability to theCMP, plasma etch, sputter deposition, silicon epitaxy,and other processes. These characteristics have beenevaluated through both simulation and control experi-ments performed on various CMP and etch tools.

Key contributions to run by run control methods havebeen made in two areas. First, extensions to the run byrun controller have been made to address practical issuesin dealing with real data in a manufacturing environ-ment. In particular, data that is non-periodic (that is,appears at a random time interval), has missing orintermittent values, and which suffers recurring events(e.g. kit changes) are problematic for many controlapproaches. These have been addressed in an extensionof the EWMA and PCC, and demonstrated for thecontrol of metal sputter deposition.

The second key contribution is the development of aframework for benchmarking of run by run controlalgorithms and implementations. A network-basedinterface has been developed that consists of(a) a number of process “simulators” that deal withsuccessively challenging control problems and scenarios(e.g. plasma etch, CMP); (b) a standard message-basedinterface for candidate external controllers to use tocommunicate with the benchmark system; and(c) example implementations and interfaces for both Cand Java-based run by run controllers. ❏

Run to Run Model Based ProcessControl on a Dual Coil TransformerCoupled Plasma Etcher

PersonnelM. Le, B. Goodlin, and T. Smith(D. Boning and H. Sawin)

SponsorshipSRC and NSF

A novel technique for improving the etching uniformityin a high density polysilicon process has been imple-mented. Blanket polysilicon on 6 inch wafers are etchedin a high density plasma etcher that has been modified toprovide a means to control the etching uniformity. Theetching is monitored with an in-situ Full Wafer Interfer-ometry (FWI) system that provides etching rate informa-tion at multiple locations across the wafers. The plasmais also monitored with a multi-fiber optical emissionspectrometer. This information is reduced and used by amodel based run to run controller to provide recipeadvice for the next wafer as to ensure that the polysiliconis etching uniformly across the wafer.

Etching uniformity is adjusted by controlling the powerdelivered to a dual coil TCP system. Instead of a singleinductive coil in a Transformer Coupled Plasma (TCP)etcher, we have installed two concentric independentantennae on a modified Lam TCP. With this geometry,the macroscopic etching uniformity of the wafer can betailored. By increasing the power delivered to the outerspiral coil in the dual coil system, the etching rate atlarger radii is increased, likewise, by increasing thepower delivered to the inner coil, the etching rate atsmaller radii is increased. Holding other variables suchas pressure and gas flow constant, it is possible to find apower setting that will maximize the wafer level etchinguniformity. The dual coil TCP provides a means tochange the macroscopic etching uniformity. In order tocontrol the etching uniformity in a shifting or a driftingetch process, a means to measure disturbances is needed.

FWI is an in-situ diagnostic that provides that capability.The etching rate at many locations across the wafersurface is obtained from the FWI system. A three-levelthree-variable full factorial experiment allows a responsesurface mapping of the etch rate at 81 different locationson the wafer to the process variables. A neural networkis trained to this data to provide a smooth model thatrelates the process inputs to the etch rate at variouslocations across a wafer.

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The neural network model is integrated into an ArtificialNeural Network Exponentially Updated MovingAverage (EWMA) controller. The EWMA update of thebias layer in the neural network allows for the controllerto adapt to process disturbances. Experiments with thisconfiguration shows that the controller can stabilize theetching uniformity and bring the non-uniformity downto less than one percent one sigma STD. To further thiswork we integrated spatial OES data into the controller.The OES data provides information about the plasmastate. This data is reduced by means of Partial LeastSquares analysis. A response surface model is built thatrelates that reduced PLS data to the process parameters.This OES model is then used by the ANN EWMAcontroller to ensure that the plasma state is similar on arun to run basis, and if it is not, the OES model providesguidance as to which process parameters should beadjusted.

FWI provides information about the wafer state whilethe spatial OES system provides information about theplasma state. These two diagnostics coupled to theANN EWMA controller is shown to stabilize distur-bances introduced in the etching system. We etchblanket polysilicon wafers and introduce an etchinguniformity disrupting shift in the process. The control-ler is able to respond to the disturbance, and within 3wafer runs, the product is back within specifications.The ANN EWMA controller with the FWI and spatialOES diagnostics on the dual coil TCP is found to be ableto control etching uniformity. Further work is under-way to develop and extend the approach for patternedwafer etch uniformity control. ❏

continued CMP Sensors and Process Control forReduced Consumption

PersonnelT. Smith, A. Nishimoto, E. Stuckey, and D. Ouma(D. Boning)

SponsorshipNSF/SRC ERC for Environmentally BenignSemiconductor Manufacturing and Texas Instruments

Chemical-mechanical polishing is a process that is still inearly adolescence. Despite poor understanding and poorcontrol in the process, it is being widely pressed intoservice because it is the only process able to deliver theglobal planarity required in present and future ICtechnology. The use of CMP is expanding beyond oxideplanarization; it is widely used in metal polishing forplug formation, polysilicon polishing for DRAM cellformation, is crucial to device isolation using shallowtrenches (STI), and will be essential for future damasceneprocesses. These expanding applications place stress onwater and slurry consumption, pad consumption,monitor and look-ahead wafer usage, and generation ofwaste and potentially hazardous materials. Most CMPprocess development is currently conducted withoutconsideration of environmental issues. It is the objectiveof this project to reduce the consumption of slurry,water, and excess wafers. More broadly, the intent is todevelop process control and optimization methods thatincorporate environmental objectives as a key concern.For example, there is considerable research and develop-ment effort in copper damascene metallization ap-proaches; very little attention has been paid to date tothe environment issues in copper waste production orother environmental issues in the copper slurries beingconsidered.

The approach being developed in this research is thepractical run by run control of the CMP process, throughwhich the process can be optimized for minimal con-sumption, and the use of monitor and look-ahead waferseliminated.

One key barrier is the lack of in-situ sensors for themeasurement of polishing uniformity across the wafer.We are developing an approach to indirectly sense andmonitor the uniformity of a wafer being polished in-situ.The system incorporates an infrared (IR) sensor which isused to monitor the temperature of the polish padimmediately after it has been in contact with the wafer.

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An IR temperature profile can be obtained by monitoringa series of points corresponding to varying radii alongthe pad surface. This profile is then analyzed spatially todetermine the non-uniformity of the polishing condi-tions. By understanding the correlation between the padtemperature and the spatial wafer temperature profileduring polishing we can predict the nonuniformity of thewafer that has been polished in-situ eliminating the needfor look- ahead wafers.

Slurry usage during polishing can also be minimizedthrough the usage of this system. The minimum flowrate can be determined by observing the temperatureprofile during polishing. Initial results using multiplesingle point measurements show a clear relationshipbetween slurry flow rate and temperature (as well aswafer) uniformity. Work is underway to extend this tosimultaneous real-time measurements using an IRcamera. In this case, the temperature profile can be fedinto a control system to alter the slurry flow during thepolish based upon the analysis of this profile. The IRcamera provides an exciting opportunity for monitoringof CMP uniformity in-situ, which provides the ability tomake process adjustments during polishing which canminimize the consumption of slurry and reduce monitorand look-ahead wafer and processing consumption, aswell as improve process quality.

In order to overcome other practical barriers to adoptionof run by run control for CMP, additional key issues arebeing examined. First, integration with an in-line filmthickness measurement tool (the Nova sensor) is needed.Second, methods for addressing film thickness differ-ences among different products are required. Finally,stable and robust control methods are being applied toachieve reduced wafer consumption, while also address-ing practical issues such as missing sample data.

Finally, semi-physical models of the CMP process arebeing developed. These models can be used to deter-mine the minimal and optimal oxide film depositionthickness needed, together with the minimal polish time,in order to achieve the best within-die planarity results.In addition, these models offer the hope of rapid controladjustments for a large variety of product layouts. ❏

195

Remote Monitoring and Diagnosis

PersonnelA. Gower, H. Chen, D. White, and S. Sadashivappa(D. Boning)

SponsorshipDARPA, MIT Leaders for Manufacturing, and Ford(in collaboration with Stanford University)

In billion dollar factories, the penalty for down time forany individual piece of manufacturing equipment is veryhigh, not only in lost production, but also in potentiallyundetected problems in in-process inventory. Earlydetection of problems, preferably before they becomeserious, and rapid response to repair or compensate are ahigh priority for all manufacturing facilities. The prob-lem is made more complex because the number ofmachines at any location is typically small and there islittle sharing of information between locations, evenwithin the same company. The trend towards increasedequipment instrumentation and data collection is perva-sive, and applies across a large spectrum of manufactur-ing domains, including semiconductor, automotive, andother industries. As the amount of information that isgathered during normal operation increases with im-proved instrumentation, the difficulty of assimilating thatinformation also increases making the problem of detec-tion and diagnosis more difficult.

In this project, we have teamed with Stanford Universityto examine two key aspects of the problem. First, soft-ware and network architectural issues to support andenable remote access and monitoring of advancedequipment and manufacturing lines are being explored.For example, an interesting trend is toward the embed-ding of ubiquitous network interfaces and real timeoperating systems (e.g. via variants of Java) on individualpieces of equipment and sensors. Led by Stanford, theteam is further exploring the impact of such interfaces ondiagnostic system architectures.

One application for monitoring and diagnosis beingexplored is the detection of pick and place failures inprinted circuit board fabrication. Working with Ford, wehave been able to identify key opportunities for reducingthe volume of scrap chips and the improvement inequipment down time through improved electronicmonitoring and diagnosis.

Second, we are developing the algorithmic basis fordealing with the large volumes of manufacturing datathat will become available via such interfaces. In particu-lar, “data rich” situations in which hundreds or thou-sands of time-sampled data streams are available poseinteresting challenges and opportunities for monitoring,detection, and diagnosis. We have been exploringvariants of multivariate modeling approaches to incorpo-rate the issue of time, including Principal ComponentAnalysis (PCA), Partial Least Squares (PLS), multiwayPCA, and other variants.

One particularly exciting application is in the detectionof different stages of a complex manufacturing processthrough multivariate “signature” analysis of the process.In this novel approach, we have applied PCA, butexamine both the “loadings” and “scores”. That is, weare interested not only in the projection of the data on theeigenvectors of the data, but also on the orientation anddirectionality of those eigenvectors. The application tolow-open area oxide etch endpoint detection in semicon-ductor manufacturing is being explored. ❏

196

Architecture for Distributed Designand Fabrication

PersonnelM. McIlrath, D. Boning, and D. Troxel

SponsorshipDARPA

The design and fabrication of state-of-the-art semicon-ductor devices and integrated circuits requires anincreasingly diverse and expensive set of resources,including manufacturing equipment, people, andcomputational tools. Advanced semiconductor researchactivities can be even more demanding, frequentlyrequiring unique equipment and processing capabilities.

We are developing a flexible, distributed system archi-tecture capable of supporting collaborative design andfabrication of semiconductor devices and integratedcircuits. Such capabilities are of particular importance inthe development of new technologies, where bothequipment and expertise are limited. Distributedfabrication enables direct, remote, physical experimenta-tion in the development of leading edge technology,where the necessary manufacturing resources are new,expensive, and scarce. Computational resources, soft-ware, processing equipment, and people may all bewidely distributed; their effective integration is essentialin order to achieve the realization of new technologiesfor specific product requirements. Our architectureleverages current vendor and consortia developments todefine software interfaces and infrastructure based onexisting and emerging networking, CIM, and CADstandards. Process engineers and product designersaccess processing and simulation results through acommon interface and collaborate across the distributedmanufacturing environment. ❏

Exploring Semiconductor DeviceParameter Space using RapidAnalytical Modeling

PersonnelB. Lee(M. B. McIlrath, D. S. Boning, D. E. Troxel, andA. Chandrakasan)

SponsorshipDARPA

The creation and implementation of a semiconductordevice parameter space exploration tool has been accom-plished which can assist circuit and device designers.Such a tool allows the designer to analyze trade-offsbetween parameter variations (after defining electricalconstraints at the circuit level of abstraction) as well asreceive information about feasible device structures. Inaddition, it is also be possible to compare device param-eter variations within a technology family, as well asacross different technology families.

The technique of exploring parameter space utilizes amethod of rapid analytical modeling to allow for faster,but less accurate, evaluations than one might get throughestablished methods of numerical simulation tools suchas MEDICI or PISCES, offering an alternative to suchsimulators for circuit designers who wish to have roughestimates of parameter variation information, or devicestructure feasibility. The tool can be a valuable additionto any circuit or device designer’s CAD environment. ❏

197

Modeling of Interconnect Reliability

PersonnelY. Chery(C. V. Thompson and D. E. Troxel)

SponsorshipDARPA

Recent research has demonstrated interconnect failuredue to electromigration effect to be strongly dependentnot only on current density but also on metal film crystalgrain size distribution and geometries of interconnectpatterns. This type of failure is manifest as a depletionof interconnect metal forming a “void” (open-circuit) oran accumulation possibly forming a “short” to neighbor-ing interconnect.

Our research work focuses on:

i) developing abstract, physically-based, micro-structural interconnect failure models to moreaccurately predict electromigration induced failure.

ii) ERNI (Electromigration Reliability for NetworkInterconnect) our prototype computer-aided designtool based on these abstracted micro-structurallybased models.

A release of ERNI 2.0 is expected during Spring 1998with extensions supporting hierarchical designs andutilizing higher-performance circuit simulation engines.This release will incorporate client and server programsimplemented in Java. With this, multiple designers atdifferent locations will be able to cooperatively designintegrated circuitry which incorporates electromigrationreliability models. ❏

Distributed Process ControlArchitecture

PersonnelA. Gower(D. S. Boning and M. McIlrath)

SponsorshipDARPA and Stanford University

Semiconductor fabrication requires an increasinglyexpensive and integrated set of tightly controlledprocesses, driving the need for a fabrication facility withfully computerized, networked processing equipment.We have designed an integrated, open system architec-ture enabling distributed experimentation and processcontrol for plasma etching. The system was developedat MIT’s Microsystems Technology Laboratories andemploys in-situ CCD interferometry based analysis inthe sensor-feedback control of an Applied MaterialsPrecision 5000 Plasma Etcher (AME5000). Our systemsupports accelerated, advanced research involvingfeedback control algorithms, and includes a distributedinterface that utilizes the internet to make these fabrica-tion capabilities available to remote users.

The system architecture is both distributed and modu-lar: specific implementation of any one task does notrestrict the implementation of another. The low levelarchitectural components include a host controller thatcommunicates with the AME5000 equipment via SECS-II, and a host controller for the acquisition and analysisof the CCD sensor images. A Cell Controller (CC)manages communications between these equipment andsensor controllers. The CC is also responsible forprocess control decisions; algorithmic controllers may beintegrated locally or via remote communications.Finally, a System Server manages connections frominternet/intranet (web) based clients and uses a directlink with the CC to access the system. Each componentcommunicates via a predefined set of TCP/IP socketbased messages. This flexible architecture makesintegration easier and more robust, and enables separatesoftware components to run on the same or differentcomputers independent of hardware or software plat-form. ❏

198

Remote Microscope for Collaborative Inspection of Integrated Circuits

PersonnelM. Perez and B. Lee(D. E. Troxel)

SponsorshipDARPA

The internet remote microscope was developed to enableusers to inspect a microscope specimen remotely byusing an ordinary workstation computer connected tothe internet. The remote microscope is a distributedsystem that consists of one or more graphical clientinterfaces that communicate over the internet with amicroscope server unit consisting of hardware andsoftware needed to automatically control an inspectionmicroscope. The client interface presents the user with agraphical microscope control panel and two imagepanels that show static images of the microscope speci-men that can be updated upon request. Because it is notimportant to have live video when examining manytypes of specimens, especially in the context of inertsemiconductor wafers, this approach gives acceptableperformance while requiring only limited bandwidth.From the control or instrumentation panel, the user mayselect a new magnification, pan position, and focussetting (manual or automatic), and can then instruct thesystem to capture a new image at the specified coordi-nates. The new image can be placed in one of the twoarbitrary display windows, allowing the user to keep aprevious image for reference. Typically, one wouldactually use one window to show a global or panoramicview of the specimen at low magnification, while usingthe other window to show a more detailed region ofinterest at high magnification. The server system con-sists of a Zeiss microscope, an automated stage accurateto 0.4 µm for X-Y translation and 0.1 µm for Z direction, avideo camera, and an ordinary personal computerrunning OS/2 that services requests over the internetfrom clients. The PC contains a framegrabber board thatcan capture an ordinary NTSC video signal from a CCDcamera that is mounted on top of the microscope, andthe PC is also responsible for controlling the stage, turret,and focus settings for an automated Zeiss microscope.Except for the initial placement of a wafer on the stage,this system is fully automated and controllable from theclient control panel. Essentially, the remote microscopeallows distant users to access and view a specimen

remotely as if they were controlling the microscopethemselves. An additional capability of the internetremote microscope is that multiple clients can view themicroscope simultaneously during a conference inspec-tion mode. This enables any number of experts any-where on the internet to simultaneously view the micro-scope images collaboratively, although only one personat a time is in control and allowed to change the systemsettings.

Users use the remote microscope by retrieving the clientapplet from a web server, residing on the same system asthe remote microscope server application. This designhas made the client program platform independent,allowing the use of the client on any machine whichsupports Java applets. The Java client currently includesall the functionality of the original client, as well as manyof the new manual focusing options currently beingdesigned.

New features added include a text chat tool, online helpfiles, a mini tools window, and a layout based navigationtool. The text based chat tool allows users to send smalltext messages to one another, while inspecting a wafer.The online help contains a complete users guide, troubleshooting tips, and other remote microscope relatedmaterial. These help files will be directly availablethrough the web server. The mini tools window allowsfor quick zoom, move, and grab commands, as well asincluding some measurement functions. A Java basedMAGIC file viewer in our group serves as the basis foran easy and quick navigation tool. ❏

199

Semiconductor Process Repository

PersonnelM. Verminski and W. Moyne,(M. McIlrath and D. E. Troxel)

SponsorshipDARPA

The goal of this research task is to create a system tofacilitate distributed process research and design. Such asystem will allow users to retrieve and examine processflows from multiple process libraries across the network.

Work has proceeded on the design and development of adistributed process repository interface. The repositoryApplication Programming Interface (API) is encapsu-lated by an OMG CORBA distributed object model anddefined by an Interface Description Language (IDL)specification. The process object model used to encapsu-late the process repository API is based on the Semicon-ductor Process Representation (SPR) Information Model.The IDL specification is programming language-neutral;application clients and repository services may beimplemented in any language supported by a CORBA-compliant Object Request Broker (ORB) and interoperateacross a local or wide-area network. Process repositoriesmay be distributed; process objects and services may belocated at various sites transparently to applicationclients. Applications and services may interoperateusing entirely distinct ORB implementations if a com-mon protocol such as the Internet InterORB Protocol(IIOP) or appropriate bridges are available.

The present SPR IDL development includes the BaseInformation Model. This standard process representa-tion interface provides a common facility to communi-cate fabrication processes. The fabrication processinformation organizes processes into smaller subpro-cesses. At each level, the process can be described fromdifferent views. These include the ‘effect’ of a process onthe wafer, the ‘environment’ around the wafer duringthe process, and the ‘equipment’ settings during theprocess. Each view contains parameters that describesome aspect of the wafer, environment, or equipmentduring some interval of time. Dynamic attributes(property lists) are also supported for maximum extensi-bility. The base SPR IDL has been extended to includespecific effects and parameters with statistical informa-tion.

Two SPR-based repository implementations are inprogress. One uses the Xerox InterLanguage Unification(ILU) ORB to provide an SPR wrapper to processes in theMIT CAFE CIM system used by the MicrosystemsTechnology Laboratories. Repository object implementa-tions are built directly on the CAFE GESTALT objectoriented programming layer. This repository implemen-tation now integrates IIOP directly, supporting operationwith clients using heterogeneous ORBs without the needfor the request-level bridging employed earlier.

A distributed software architecture for semiconductorprocess design has been defined and implemented inJava with the OrbixWeb Object Request Broker (ORB).The implementation communicates with any ORBadhering to the Internet Inter-ORB Protocol (IIOP). Apersistent storage mechanism has been implementedusing Object Design ObjectStore PSE (Persistent StorageEngine) for Java.

Other services to manage, query and find distributedobjects are being developed. Their interfaces are basedupon the Object Management Group’s (OMG) CORBAservices specifications. A Life Cycle service for creating,deleting, copying, and moving distributed objects hasbeen developed. Work has begun on implementing aQuery service and a Trader service. Together, theservices will be essential for the development of distrib-uted and shared applications for semiconductor processresearch and design.

We have also been collaborating with the Sematech CIMFramework project in the areas of Specification Manage-ment and CIM Architecture. This work is also CORBAIDL-based and we are investigating the possibilities forinteroperation of these environments. ❏

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Labnet Software

PersonnelT. Lohman(D. Boning, M. McIlrath, and D. Troxel)

SponsorshipDARPA

University microfabrication laboratories are facing manynew challenges and opportunities: facilities are becom-ing more expensive and difficult to manage; resourcesand expertise need to be shared and made available to awider community; education and research are becomingmore dependent on multi-institutional collaboration.Given the above challenges, there is a growing desire fora new distributed information infrastructure, that willallow remote collaboration, access to remote sites’ dataand sharing of end-user software applications, in the faceof differences between remote sites in computer plat-forms, operating systems, and technical resources. Pastresearch has been done within this application domainbut most working systems are too tightly coupled totheir local facilities, suffer from portability problems andhave never addressed the issue of data distribution andremote site interaction.

The Labnet Software Project was initiated in recognitionof a need for universities to share the development andsupport effort needed to develop and maintain newdistributed laboratory information systems. Jointdevelopment work was initiated between MIT, StanfordUniversity and the University of California at Berkeleyto:

• Assess the applicability of emerging tech-nologies such as the Object ManagementGroup’s (OMG) Common Object RequestBroker Architecture (CORBA), OMG’sInterface Definition Language (IDL), SunMicrosystem’s Java language, and objectdatabases.

• Explore infrastructure to enable collabora-tive distributed design and fabrication(including object-oriented distributedprogramming interfaces and web-based userinterface capability).

• Develop abstract specifications of program-ming interfaces to both data and services.

• Explore standards to achieve softwarecompatibility such as the Sematech CIMApplication Framework.

In the last year, substantial progress has been made indeveloping a prototype distributed reservation system.The system utilizes a Java user interface which enablesthe reservation module to run on standard web browserclients anywhere on the network. On the back end,information is managed through JDBC database connec-tivity. The system is now being used to gain userfeedback, as well as to evaluate implementation optionsand architecture decisions. ❏