status and roadmap of hybridization technologies technologies … · 2018-11-21 · - precisive but...
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1T-Micro / Motoyoshi
T-Micro
Status and roadmap of hybridization
technologies technologies technologies
relevant to future pixel detectors
Makoto Motoyoshi
Tohoku-MicroTec
Dec. 13, 2017 SPIPIX2017
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2T-Micro / Motoyoshi
T-Micro
LSI Technology
- Predictable- Precisive but inflexible
- unpredictableApplication driven technology
- Need flexibility System technologyMany integration methods
3D-IC Technology
Dec. 13, 2017 SPIPIX2017
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3T-Micro / Motoyoshi
T-Micro 3DIC Supply chain
Base devices
4 inch Si wafer
6 inch Si wafer
8 inch Si wafer
12 inch Si wafer
Shuttle service (LSI Chip)
Compound Semiconductor (Chip/Wafer) 3D
integration
Dec. 13, 2017 SPIPIX2017
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4T-Micro / Motoyoshi
T-MicroUnique Points of 3D-LSI
Conventional SoC3D-SoC
Long Global interconnect
large RC delay, large CP
Length of TSV:1-50mm
-Short global interconnectsmall RC delay, small CP
-High band width-Small form factor
1. Increase of electrical performances
2. Increase of circuit density
3. New Architecture (Hyper-parallel processing, Multifunction, etc)
4. Heterogeneous integration
5. Better yield
Sync.
clock Repartitioning Die
Compound semiconductor
TSV:Through Silicon Via
Dec. 13, 2017 SPIPIX2017
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5T-Micro / Motoyoshi
T-Micro
5
WSTS: World Semiconductor Trade Statistic Inc. (2017)
Semiconductor Market Forecast
‘11 ‘12 ‘13 ‘14 ‘15 ‘16
3000
2000
1000
2500
1500
500
0
3500
M$
‘17 ‘18 ‘19 ‘20 ‘21
4000
4500
3D-IC
WSTS data
‘22 ‘23 ‘24 ‘25
DRAM, Flash
MEMS device
Sensor /Detector
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6T-Micro / Motoyoshi
T-Micro
Source: Cliff Hou (TSMC), ISSCC 2017 (Plenary)
Chip & System Integration Trends for better PPA & System Performance
Dec. 13, 2017 SPIPIX2017
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7T-Micro / Motoyoshi
T-Micro
Key technologies of 3D-IC Integration
Chip Alignment
Micro bump TSV (Through Silicon Via)
Wafer thinning
N+ N+
N+ N+
N+ N+
P+ P+
P+P+
P+P+
SiO2
SiO2 SiO2 SiO2
SiO2
SiO2SiO2
Pch-MOSFETNch-MOSFET
Pch-MOSFET
Nch-MOSFET
Si Substrate
NWell
PWell PWell
NWell
Over coat
metal metal
metal
metal
Top tier
Middle tier
Bottom tier
775μm 50~10μm
satisfy LSI reliability test
Dec. 13, 2017 SPIPIX2017
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8T-Micro / Motoyoshi
T-Micro
Via Last
Aft
er
BE
OL
Front Via
450~350ºC >
Handle
Wafer
Back Via
Via Middle
Aft
er
MO
S
Aft
er
1st
Inte
rlayer
600ºC >
Befo
re M
OS
Allowable max. process
temperature1000ºC >
Via First
TSV process classification
TSV
step
Well
IsolationMOS Interlayer
FEOL BEOL
MOS
process
SOI
Handle
Wafer
Stacking
Handle
Wafer
Handle
glass
Thinning
Dec. 13, 2017 SPIPIX2017
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9T-Micro / Motoyoshi
T-Micro
Si
Multi-levelmetallization
Organic film (Adhesive) Oxide Metal Microbump
Adhesive Bonding Oxide Fusion Bonding Metal (Cu) Fusion Bonding
Wafer Bonding Methods -1
Si
Multi-levelmetallization
Si
Multi-levelmetallization
Metal (Cu/SnAg) Eutetic Bonding
Dec. 13, 2017 SPIPIX2017
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10T-Micro / Motoyoshi
T-Micro
Microbump
Adhesive/ Metal Bonding
Oxide
Oxide/ Metal Bonding
(Hybrid bonding)
Si
Multi-levelmetallization
Si
Multi-levelmetallization
Organicfilm
Microbump
Wafer Bonding Methods -2
Dec. 13, 2017 SPIPIX2017
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11T-Micro / Motoyoshi
T-Micro
Dec. 13, 2017 SPIPIX2017
T-Micro
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12T-Micro / Motoyoshi
T-MicroHBM (High Band Width Memory)
Commercialized 3D DRAM
Source: Kyomin Sohn (Samsung), ISSCC2016
Dec. 13, 2017 SPIPIX2017
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13T-Micro / Motoyoshi
T-MicroCross-sectional View and Chip Photo of HBM
Source: Kyomin Sohn (Samsung), ISSCC2016
Dec. 13, 2017 SPIPIX2017
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14T-Micro / Motoyoshi
T-Micro
Source: Kyomin Sohn (Samsung), ISSCC2016
Dec. 13, 2017 SPIPIX2017
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15T-Micro / Motoyoshi
T-Micro
Top part
BI-CIS
Middle part
DRAM
Bottom part
Logic
Sony / 3D-Stacked Image Sensor
Cu-Cu Via
3um wide
14um pitch
Cu-Cu Via
3um wide
6um pitch
Source: T. Haruta (Sony) ISSCC2017Source: Chipworks, April, 2016
Sony’s first CIS module(IMX260) product
with Cu-Cu Hybrid bonding
Dec. 13, 2017 SPIPIX2017
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16T-Micro / Motoyoshi
T-Micro
High Density Memory Systens using Si Interposer
Dec. 13, 2017 SPIPIX2017
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17T-Micro / Motoyoshi
T-Micro
Fury graphics card : $649, June, 2015
Si Interposer
HBM (1GB, 1GbX4 Tier)
Memory Interface ; 4096bit
Memory Bandwidth ; 512GB/s
9900mm2
<4900mm2
AMD reveals HBM-powered Radeon Fury graphics
cards,
new R300-series GPUs
Dec. 13, 2017 SPIPIX2017
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18T-Micro / Motoyoshi
T-Micro
MEMS chipSensor chipCMOS RF-ICMMICPower ICControl ICLogic LSIFlash memoryDRAMSRAMMicroprocessor
Metal microbumpThrough-Si via (TSV)
3D Super Chip
New chip stacking
technologies are
required
Different
chip size
Different devices
Different materials
Highly Integrated Heterogeneous 3D Integrated System1.3
mm
38-layer chip stack
Dec. 13, 2017 SPIPIX2017
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19T-Micro / Motoyoshi
T-Micro
Dec. 13, 2017 SPIPIX2017
Fine Pitch TSV
By Plating
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20T-Micro / Motoyoshi
T-Micro
Dec. 13, 2017 SPIPIX2017
Novel Hybrid Bonding Features
for Ultra-High Density 3D/2.5D Integration
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21T-Micro / Motoyoshi
T-Micro
Dec. 13, 2017 SPIPIX2017
Novel Hybrid Bonding Features
for Ultra-High Density 3D/2.5D Integration
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22T-Micro / Motoyoshi
T-Micro
Dec. 13, 2017 SPIPIX2017
Inorganic Anisotropic Conductive Film
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23T-Micro / Motoyoshi
T-Micro
Dec. 13, 2017 SPIPIX2017
Hybrid Bonding using Cu Nano-Pillar
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24T-Micro / Motoyoshi
T-Micro
Dec. 13, 2017 SPIPIX2017
Hybrid Bonding using Cu Nano-Pillar
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25T-Micro / Motoyoshi
T-Micro
Dec. 13, 2017 SPIPIX2017
Multi-Chip FPGA TEG Modules
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26T-Micro / Motoyoshi
T-Micro
Dec. 13, 2017 SPIPIX2017
300mm FPGA TEG modules Fabricated by
Multichip-to-Wafer 3D Stacking
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27T-Micro / Motoyoshi
T-Micro
Dec. 13, 2017 SPIPIX2017
Chip-to-chip,Chip-to-Wafer bonding
using Au cone bump
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28T-Micro / Motoyoshi
T-MicroX-ray CT Image
M5
M4
M3
M2
M1
M1
M2
M3
M4
M5
W plug
AlCu
AlCu
Au Cone bump connection
28
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29T-Micro / Motoyoshi
T-MicroAu Cone bump formation
29
Bump litho.
NpDSi-sub
Photoresi
st
Hole pattern
Top view after deposition
Close bump hole
Au/barrier
metal/SiO2
Si
After resist lift-off
HeHe He He
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30T-Micro / Motoyoshi
T-MicroMaterial cost of Au bump
2.5μm
2.5μmφ
106 micro bumps
30μmφ
Au wire
0.57cm
Reuse the deposited Au on photoresist
Dec. 13, 2017 SPIPIX2017
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31T-Micro / Motoyoshi
T-Micro
Cylinder Bump for fragile material
Dec. 13, 2017 SPIPIX2017
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32T-Micro / Motoyoshi
T-Micro
CdTe
CdTe surface after CdTe/Si-ROIC bonding with Au bump
Dec. 13, 2017 SPIPIX2017
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33T-Micro / Motoyoshi
T-MicroBump bonding with cylinder Au bumps
Thin
(easy to deform)
Cylinder bump
Si-sub
Fragile material
Si-sub
Dec. 13, 2017 SPIPIX2017
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34T-Micro / Motoyoshi
T-Micro
Cylinder bump
3.5μm
photoresist
Au Sputter Au
Short Throw(SL)Au spatter SiO2
AuAu electrode
after photoresist lift-off
Bump hole patterning
SiO2
Bump bonding with cylinder Au bumps
Dec. 13, 2017 SPIPIX2017
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35T-Micro / Motoyoshi
T-Micro
Si ROIC
CdTe
SEM cross sectional view
Dec. 13, 2017 SPIPIX2017
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36T-Micro / Motoyoshi
T-Micro
Process cost reduction
for the Heterogeneous Integration
Dec. 13, 2017 SPIPIX2017
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37T-Micro / Motoyoshi
T-Micro
Need a high speed COW technique with the high alignment
accuracy and the practical process cost
3D stack approaches
CtC
(chip to chip)
CtW
(chip to wafer)
WtW
(wafer to wafer)
stack dicing dicing
Process cost High LowHigh ~ Middle
Stack chips with
different chip size possible possible Impossible
Chip alignment
accuracy
<0.5μm (3σ)
Difficult from economical stand point possible ?
MiscellaneousNeed high yield wafers
Ytotal=YW#1 x・・・・・x YW#n
Need same size wafers
Dec. 13, 2017 SPIPIX2017
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38T-Micro / Motoyoshi
T-Micro
(a)Current 3D Production
Economy of 3D LSI manufacturingT
hro
ug
h p
ut
3D LSI chip
LSI Wafer process 3D integration
~10k chips/hour100 chips/hour
pro
cess 1
pro
cess 2
pro
ce
ss
3
pro
cess n
-1
pro
ce
ss
n
12”φ
wafer
8”φ
wafer
6”φ
wafer
2”φ
wafer
Stack one-by-one
IP11IP12
IP1n
IP21
IP22
IP2n
IP
IPIP
IPm2 IPm1
IPmn
IPm3
IP
IPIP・・・・・・・・・・・・・・・・・・・・・・・
・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・
・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・
Dec. 13, 2017 SPIPIX2017
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39T-Micro / Motoyoshi
T-Micro
(b)Our Target
Economy of 3D LSI manufacturing
Th
rou
gh
pu
t
3D-IC chip
LSI Wafer process 3D integration
10k chips/hour 100 chips/hour
(a)Current 3D ProductionT
hro
ug
h p
ut
3D-IC chip
10k chips/hour 10k chips/hour
pro
ce
ss
1
pro
ce
ss
2
pro
ce
ss
3
pro
ce
ss
n-1
pro
ce
ss
n
pro
ce
ss
1
pro
ce
ss
2
pro
ce
ss
3
pro
ce
ss
n-1
pro
cess n
Dec. 13, 2017 SPIPIX2017
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40T-Micro / Motoyoshi
T-Micro
Self-assembly Technique
“Super Chip”
Dec. 13, 2017 SPIPIX2017
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41T-Micro / Motoyoshi
T-MicroSelf-assembly technique
hydrophilic areahydrophobic area
5mm
droplet
Dec. 13, 2017 SPIPIX2017
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42T-Micro / Motoyoshi
T-Micro
Targetinterposer
wafer
New Reconfigured Wafer-to-Wafer 3D IntegrationReconfigured waferKnown good die (KGD)
3D super chipCarrier waferLSI wafer with/without TSV
1st layer chip
2nd layer chip
3rd layer chip
Failure die
Dec. 13, 2017 SPIPIX2017
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43T-Micro / Motoyoshi
T-Micro
2. Self-assembly
DC supply
+ ‐
DC supply
00
SAE carrier
KGD
SAE carrier
Bipolar electrode
Top view
Water
SAE carrier
Hydro-philic
3. Electrostatic bondingComb-type
bipolar electrode
5. Electrostatic debonding
Dielectric layer
Cross-sectional view
CA: < 30°
Self-Assembly & Electrostatic (SAE) Bonding
CA: > 110°
Assembly area(hydrophilic)
Surrounding area(hydrophobic)
4. Inverse-voltage apply
Top view
Cross-sectional view
SAE carrier
Hydro-phobic
Hydro-phobic
KGD
1. Face-up KGD release
Self-assembled KGDs
KGD
Dec. 13, 2017 SPIPIX2017
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44T-Micro / Motoyoshi
T-Micro
Dec. 13, 2017 SPIPIX2017
Thank you for your kind attention.
If there’s anything you are unclear on, please feel free to contact me. [email protected]