Stellaris ® ARM® Cortex™ -M4F Training

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Peripheral Overview

Agenda

• Stellaris LM4F General Specifications

• Features of ARM® Cortex™-M4F

• Other System Features– Low Power Features– Watchdog Timers

• Timers and GPIOs

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• Timers and GPIOs

• Analog Peripherals

• Connectivity

• Motion Control Peripherals

Stellaris ® LM4F Devices

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Stellaris ® ARM® Cortex™ -M4F

Connectivity features:• CAN, USB H/D/OTG, SPI, I2C, UARTs

High-performance analog integration• Two 1 MSPS 12-bit ADCs• Three analog comparators

Best-in-class power consumption• As low as 370 uA/MHz

Stellaris ® LM4Fx MCU

Serial Interfaces Motion Control

ARM®

Cortex™-M4F

SWD/T

NVIC

JTAG

FPU

ETM

MPU

80 MHz

256 KBFlash

Analog

Temp Sensor

3 AnalogComparators

32 KBSRAM

ROM

2KB EEPROM

LDO VoltageRegulator

2 x 12-bit ADCUp to 24 channel

1 MSPS

System• As low as 370 uA/MHz• 500µs wakeup from low-power modes • RTC currents as low as 1.7uA

Solid roadmap • Higher speeds• Larger memory• Ultra-low power

6 I2C

2 CAN

8 UARTs

USB Full Speed Host / Device / OTG

4 SSI/SPI

2 QuadratureEncoder Inputs

16 PWM Outputs

Comparators

PWMGenerator

Timer

Dead-BandGenerator

PWMGenerator

System

Systick Timer

Precision Oscillator

Clocks, ResetSystem Control

12 Timer/PWM/CCP6 each 32-bit or 2x16-bit6 each 64-bit or 2x32-bit

2 Watchdog Timers

GPIOs

32ch DMA

Battery-BackedHibernate

RTC

Internal Memory

• 256 KB single-cycle Flash memory up to 40 MHz; a prefetch buffer improves performance above 40 MHz

• 32 KB single-cycle SRAM with bit-banding

• Internal ROM loaded with StellarisWare software:– Stellaris Peripheral Driver Library– Stellaris Boot Loader– Stellaris Boot Loader– Advanced Encryption Standard (AES) cryptography tables– Cyclic Redundancy Check (CRC) error detection functionality

• 2KB EEPROM

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Stellaris ® LM4F System Features

Watchdog Timer, Hibernate Module

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Watchdog Timer, Hibernate Module

Watchdog Timers

• Two 32-bit countdown timers, capable of generating maskable or non-maskable interrupts on roll-over.

• One Watchdog timer is clocked by the system clock. The other runs from the PIOSC

• Configuration may be locked to prevent inadvertent changes to the watchdog settings.watchdog settings.

• User-enabled stalling for software debugging.

• May be used to generate a system reset when the processor fails to clear the interrupt

• Possible uses:– Recovering from software errors– Recover from external devices failing or not behaving as expected.– Reset and continue operation if the main crystal is damaged or removed. 7

Hibernation and Low Power States

Stellaris family devices offer the following three low power states:

• Sleep Mode

• Deep-Sleep Mode

• Hibernation

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Sleep Mode and Deep Sleep Mode

Sleep Mode

• Turns off the clock for the main processor

• Will “wake up” when a high enough priority interrupt is received

Deep SleepDeep Sleep

• Turns off the system clock, PLL, and flash memory

• Enables a Wake-up Interrupt Controller (WIC), which will bring the processor out of deep sleep if an interrupt is received

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Normal Run Operation

Processor HibernationModule

Peripherals

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ProcessorModule

WIC

Processor and peripherals are powered; sleep, deep sleep, and hibernate-related features are turned off.

Run Mode

– This mode provides normal operation of the processor and currently enabled peripherals (i.e. the ones that are enabled in RCGC registers).

– The microcontroller actively executes code with maximum performance.

– The system clock can be any of the available clock sources including the PLL.

IDD_RUN=32mA

1111

Sleep Mode

Processor HibernationModule

Peripherals

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ProcessorModule

WIC

The processor enters a low-power state, and stops executing instructions until a sufficiently important interrupt is received.

Sleep Mode

• Sleep mode is used to lower the overall power consumption by turning off the clock to the processor and memory (Flash & SRAM).

• The active peripherals (i.e. the ones that are enabled in SCGC/ RCGC registers) are clocked at the same frequency as the system clock.

• The system clock has the same clock source & frequency as that during run mode.

• Application: This mode is used in applications where processor needn’t be running code, but peripherals are still required to function at system clock speed.

IDD_SLEEP=10mA

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Processor executes a Wait for Interrupt (WFI), or Wait for Event (WFE) or Sleep-on-Exit (upon completing execution of exception handler if SLEEPEXIT bit in SYSCTRL register is set)

Processor (NVIC) detects an interrupt, or depending upon the mechanism that caused it to enter the sleep mode i.e.

WFI/WFE/Sleep-on-Exit.

Code execution begins

Entering into Sleep Mode and waking up from Sleep M ode

SLEEP MODE2 sys clks. (when PPL is not used)

Deep Sleep Mode

Processor HibernationModule

Peripherals

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ProcessorModule

WIC

Processor enters a very low-power state, and some features (such as Systick) are shut off completely. The Wakeup Interrupt Controller (WIC) intercepts important interrupts, and wakes the processor if necessary.

Deep Sleep Mode

• Deep Sleep mode is used to further reduce the overall power consumption by turning off the clock to the processor and memory (Flash & SRAM) along with the following:

– Main osc. (MOSC, 4 to 25MHz) can be powered off.– PLL is powered off (if active in Run Mode).– The active peripherals (enabled in DCGC register) can be clocked using internal oscillator

(IOSC, 30kHz).

• Application: This mode is used in applications where processor needn’t be running code, and peripherals are required to function at a speed lower than run-mode system speed.

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If SLEEPDEEP bit in SYSCTRL & processor executes a Wait for Interrupt (WFI)/ Wait for Event (WFE) or Sleep-on-Exit (upon completing execution of exception handler if SLEEPEXIT bit in SYSCTRL register is set)

Wake-Up Interrupt Controller (WIC) wakes up the processor upon

detecting an interrupt if DEEPSLEEPbit SCR register is set.

Code execution begins

Entering into Deep Sleep Mode and waking up from De ep Sleep Mode

DEEP SLEEP MODE1.25 to 350 µs

Hibernate

Processor HibernationModule

Peripherals

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ProcessorModule

WIC

Power to the majority of the chip, including the processor and all peripherals, is shut off. The Hibernation module continues to operate using its own power source and clock until the wakeup condition is met.

Hibernation Mode

• Hibernation mode provides the lowest power configuration available on Stellaris microcontrollers.

• This mode allows users to completely power down the core and peripherals while only maintaining power to the Hibernation module.

• Hibernation module is a dedicated hardware that:– Allows managing removal and restoration of power to the

processor.– Can be independently powered by an external battery or an aux.

IHIB=1.6 µA

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– Can be independently powered by an external battery or an aux. power supply.

– Allows power to be restored upon assertion of an external signal, or at a certain time (using RTC).

• Application: Used in battery-powered/ hand-held applications where the system can be put into a lowest-power state while saving some state information.

Hibernation Module Key Features

• 32 bit real time seconds counter (Real time clock) with 15-bit sub seconds & add-in trim capability

• Dedicated pin for waking using an external signal

• RTC operational and hibernation

• Low-battery detection, signaling, and interrupt generation, with optional wake on low battery

• Clock source from a 32.768-kHzexternal crystal or external oscillator

• 16 32-bit words of battery-backed memory to save state during hibernation

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• RTC operational and hibernation memory valid as long as VBAT is valid

• GPIO pins state retention (VDD3ON Mode)

• Two mechanisms for power control

• System Power Control

• On-chip Power Control

memory to save state during hibernation

• Programmable interrupts for RTC match, external wake, and low battery events.

Hibernation Module Block Diagram & Signal Description

32.768 kHz crystal, or a

single ended clock source

External input that brings the processor out

of hibernation

Buffered version of 32.768 kHz clock

Battery Backed Memory

16 Words

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of hibernation mode

Power source for

Hibernation module, can

be an external

power supply or a battery

Output that indicates processor is in hibernation mode

Functional Block Diagram of Hibernation Module

• The device enters hibernation mode in following cases:– When HIBREQ bit in HIBCTL register is set, or– When VDD is removed with a valid VBAT (if properly configured).

• When the device is in hibernation mode, HIB signal is asserted.

• The device wakes-up from hibernation in following cases:– When WAKE pin is asserted, or – When RTC match occurs, or– When low battery is detected.

Hibernation Module Functional Description

– When low battery is detected.

• Upon wake up, HIB signal is de-asserted and an internal POR signal is issued.

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HIBREQ=1, or VDD removal

RTC match/ WAKE assertion/ Low battery detection

Code execution begins

tWAKE_TO_HIB TTPOR

Entering into hibernation and waking up from hibern ation

HIBERNATION

~500 µs

HIB signal isde-asserted

tLDO_RAMP

• Dynamic power source determination– Supply voltage of Hibernation module is the higher of VDD or VBAT.

• 2 mechanisms for power control (based on VDD3ON bit in HIBCTL register)

Power Control

Controls the power to the MCU with a control signal, HIB is connected to EN signal of an external LDO

VDD3ON Mode : Uses internal switches to control power to MCU while retaining power to I/O pins

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Power control* using an External LDO Power Control* using VDD3ON Mode

GNDX GNDX

32.768 kHz 32.768 kHz

*simplified diagram to explain the concept. See datasheet for more details.

• Hibernation module requires an external clock source that is independent from the main system clock.

• An independent clock source is required to maintain RTC/ preserve the contents of battery-backed memory when the main system clock is powered down due to removal of VDD.

• A 32.768-kHz crystal or an external clock source can be used to provide clock to the Hibernation module.

• If the application does not require hibernation, XOSC1 pin can remain unconnected, XOSC0 can be connected to ground, and VBAT pin should be connected to VDD.

Hibernation Clock Source

22Hibernation Clock Source: External Crystal Hibernati on Clock Source: External Oscillator

Clock Source

(fEXT_OSC) 32.768

kHz NC

32.768 kHz

GNDX

• Low Battery Detection– Optionally, hibernation can be prevented during low battery condition i.e.

the module can be configured so that it does not go into hibernation mode if the battery voltage drops below this threshold.

– The module can monitor the voltage level of the external battery and detect when the voltage drops below VLOWBAT (1.9V, 2.1V, 2.3V or 2.5V).

– VLOWBAT threshold is configured using VBATSEL bit in HIBCTL register.

– Battery voltage is monitored while in hibernation, and the microcontroller

Battery Management

– Battery voltage is monitored while in hibernation, and the microcontroller can also be configured to wake from hibernation if the battery voltage goes below the threshold using the BATWKEN bit in the HIBCTL register.

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• The Hibernation module draws power from whichever source, VBAT or VDD, has the higher voltage.

Stellaris ® LM4F Analog Features

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Analog -to-Digital Converter

• Stellaris LM4F MCUs feature 2 ADC modules (ADC0 and ADC1) that can be used to convert continuous analog voltages to discrete digital values

• Each ADC module has 12-bit resolution

• Each ADC module operates independently and can therefore:

– Execute different sample sequences

ADCVIN VOUT

VIN

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– Execute different sample sequences– Sample any of the 24 analog input channels– Generate different interrupts & triggers

25Analog-to-Digital converterADC Implementation in Stellaris LM4F MCUs

ADC0

ADC1

Input Channels

Triggers

Interrupts/ Triggers

Interrupts/ Triggers

24

VO

UT

000

001

011

010

100

101

t

t

ADC Key Features

• 12-bit precision ADC

• 24 shared analog input channels

• Single ended & differential input configurations

• On-chip internal temperature sensor

• Flexible trigger control– Controller/ software– Timers– Analog comparators– PWM– GPIO

• Hardware averaging of up to 64 samples

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• Maximum sample rate of one million samples/second (1MSPS).

• Selectable reference signals (VDDA, GNDA or two external voltages*)

• 4 programmable sample conversion sequencers

• Hardware averaging of up to 64 samples for improved accuracy

• 8 Digital comparators/ per ADC

• Efficient transfers using µDMA

• Optional phase shift in sample time, programmable from 22.5 ° to 337.5°

*except on 64 pin packages

ADC Block Diagram

Digital readingsADC

Trigger

Analog in

Ref. voltage

Analog

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Analog Comparator

The analog comparators may also be used as ADC trigger sources: • Allows the user to monitor a sensor value after it passes some

threshold voltage. • Conversions will only be triggered when the voltage is inside the

range of interest

Block Diagram & Signal Description

Reference voltages to specify the voltages at which ADC converts to a min/max

value

Analog Inputsto ADC

28Functional Block Diagram of an ADC Module

Sample Sequencers

• ADCs on Stellaris LM4F devices collect and sample data using a programmable sequence-based approach.

• Each sample sequence is a fully programmable series of consecutive (back-to-back) samples that allows the ADC module to collect data from multiple input sources without having to be re-configured.

• Each ADC module has 4 sample sequencers that control sampling and data capture.

• All sample sequencers are identical except for the number of samples they can capture

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and the depth of the FIFO.

• To configure a sample sequencer, the following information is required:– Input source– Mode (single-ended, or differential)– Interrupt generation on sample completion– Indicator for the last sample in the sequence

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ADC Sample Sequencers

SequencerNumber of

Samples

Depth of

FIFO

SS 3 1 1

SS 2 4 4

SS 1 4 4

SS 0 8 8

• µDMA Operation: There is a dedicated µDMA channel for each ADC sample sequencer. Each sample sequencer can transfer data independently.

ADC Voltage Reference

• ADC uses ADCVREFA+ and ADCVREFA- reference voltages to produce a conversion value.

• Internal/ external reference voltages for ADC can be selected using VREF bit in ADCCTL register.

VDDA

GNDA

VREFA+

VREFA-

ADCVREFA+

ADCVREFA-

Inte

rnal

Ext

erna

l

• Resolution (in single-ended mode): CREF

• ADC saturates in under-voltage and over-voltage cases ( shaded region).

3030ADC Voltage Reference & Conversion Range

Con

vers

ion

Res

ult

VIN0x000

ADCVREFA- ADCVREFA+ [ADCVREFA- + ADCVREFA+ ]2

0xFFF

0xC00

0x800

0x400 Sat

urat

ion

Reg

ion• Range:

Differential Sampling

• ADC also allows differential sampling of two analog input channels.– Differential input pair can be configured in ADCSSMUXn register.– Differential sampling can be enabled by setting Dn bit in ADCSSCTL0.

• Differential input pair ‘n’ samples the voltage difference (∆VIN) between consecutive even and odd analog inputs channels.

0xFFF

Sat

urat

ion

Reg

ion

3131ADC Conversion Range in Differential Mode

Con

vers

ion

Res

ult

∆VIN0x000

0

0xC00

0x800

0x400 Sat

urat

ion

Reg

ion

-∆VADCVREF ∆VADCVREF

Where,

∆VADCVREF = ADCVREFA+ - ADCVREFA-

• For conversion accuracy:

• Resolution:

• ADC conversions saturate in under-voltage and over-voltage cases (shaded region).

Sample Phase Control

• ADC Sample Phases shifts– ADC0 and ADC1 can be

operated from the same trigger source.

– If they are sampling data at the same frequency, then start of conversion can be delayed in 15 discrete increments of 22.5° from 0° up to 337.5°.

t

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19ADC Sample Clock

PH 0x0(0º)

PH 0x1(22.5º)

PH 0x1F(337.5º)

3232

Ana

log

Inpu

t

t

S1 S2 S3 S4 S5 S6 S7 S8

S1 S2 S3 S4 S5 S6 S7 S8

ADC1

ADC0

Skewed Sampling

• Skewed Sampling– ADC0 & ADC1 can be used

out of phase of each other.– The sampled data can be

combined in the software.– This effectively doubles the

conversion bandwidth upto2MSPS.

t(337.5º)

ADC Sample Phases

Hardware Sample Averaging Circuit

• Hardware sample averaging circuit can be used to generate higher precision results.

• Up to 64 samples can be accumulated and averaged to form a single data entry in the sequencer FIFO.

• By default, hardware sample averaging circuit is off.– All the data from the converter passes through

the sequencer FIFO.– Averaging is controlled by ADCSAC register.

Sam

ples

t

A+B+C+D

A

B

CD

A’

B’

C’D’

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• All channels are averaged equally irrespective of their configuration (single ended or differential).

• Example: if AVG value in ADCSAC register is0x02, then 4x averaging will be done. If IE bit in ADCSSCTL0 register is set, then an interrupt will be generated when FIFO gets second data entry.

• Tradeoff: Throughput is decreased proportionally to the number of samples in the averaging calculation.

33Sample Averaging Example

A+B+C+D4

A’+B’+C’+D’4

FIFO

INT

Internal Temperature Sensor

Ref

eren

ce V

olta

ge (

V)

Temperature(°C)

2.7

1.633

0.3

• Internal temperature sensor module consists of:– Band gap reference circuit that provides

reference voltage to various analog peripherals.

– On-chip internal temperature sensor.

3434Internal Temperature Sensor Characteristics

12525-55

Tem

pera

ture

(°C

)

ADC Output

147.5

91.2

-77

0xFFF0x8000x0 0xC000x400

34.9

-21.3

• Internal temperature sensor serves following key purposes:

– Senses die temperature for reliable system operation.

– Provides temperature measurements in order to calibrate hibernation module’s RTC trim value.

• The temperature can be sampled by setting TSn bit in ADCSSCTLn register.

Digital Comparator Unit

• A digital comparator compares the ADC module’s output with user programmable limits. Depending on the result of the comparison, a processor interrupt or a trigger to the PWM module can be generated.

• Each ADC module contains 8 digital comparators .

• Operational Modes:– Always Mode– Once Mode– Hysteresis Mode

Mid

Ban

d

COMP1

Hig

h B

and

VIN

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– Hysteresis Always Mode

• Modes can be selected using CIM or CTM bit in ADCCTLnregister.

• Functional Ranges:– Low Band– Mid Band– High Band

• Functional Ranges can be selected using COMP0 and COMP1 bits in ADCDCCMPn register.

• Always, COMP1 ≥ COMP0.35Digital Comparator Functional Ranges

Mid

Ban

d

COMP0

tLo

w B

and

Analog Comparator Key Features

• Analog comparator compares two analog voltages and provides a logical output depending upon the result of the comparison.

• 3 analog comparators integrated in Stellaris MCUs can be independently used to:

– Compare two analog signals and replace an external/discrete analog comparator to save board space and system cost. VIN-

VIN- (external)

VIN+ (internalref. or external)

VOUT

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– Drive an external pin– Trigger an ADC– Signal an application using interrupts

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VIN+

VOUT

1 1

0 0 0

Using Analog Comparators Independently

Generate an interruptTrigger an ADC

Any Signal

Analog Comparator: Inputs & Output

t

t

Block Diagram & Signal Description

Analog Comparator N’s positive input

Analog Comparator N’s negative input

C1o

C2o

Analog Comparator N’s output

C1o

Output to trigger an ADC

37Functional Block Diagram of Analog Comparator Modul e

C0o