stick diagram

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  • 1. Design Rules Interface between designer and processengineer Guidelines for constructing process masks Unit dimension: Minimum line width scalable design rules: lambda parameter absolute dimensions (micron rules)

2. 5 3. 6 4. Stick Diagram A stick diagram is a graphical view of a layout. Does show all components/vias (exceptpossibly tub ties), relative placement. Does not show exact placement, transistorsizes, wire lengths, wire widths, tubboundaries. 5. Stick Diagram Represents relative positions of transistors Stick diagrams help plan layout quickly Need not be to scale Draw with color pencils or dry-erase markersInOutVDDGNDInverterAOutVDDGNDBNAND2 6. Stick DiagramMetal (BLUE)Polysilicion (RED )N-Diffusion (Green)P-Diffusion (Brown)Contact / ViaLayers 7. Jhon P. UStick Diagrams Cartoon of a layout. Shows all components. Does not show exact placement, transistor sizes,wire lengths, wire widths, boundaries, or anyother form of compliance with layout or design rules. Useful for interconnect visualization, preliminary layoutlayout compaction, power/ground routing, etc. 8. Jhon P. U5 VDepVoutEnh0V5 v0 VVin5 v 9. Parallel Connected MOS PatterningJhon P. UxyA BxA BX X Xy 10. Alternate Layout StrategyA BJhon P. UxyxX XA BX Xy 11. Designing MOS ArraysA B Cx yJhon P. UyxA B C 12. The CMOS NOT GateJhon P. UXXXXVpGndxGndn-wellVpx xxContactCut 13. Alternate Layout of NOT GateJhon P. UVpGndxxXxVpGndXxXX 14. NAND2 LayoutJhon P. UVpGndb a.a bXVpGndX XX Xa bb a. 15. NOR2 LayoutJhon P. UVpGndb a a bX XXVpGndX Xa bb a 16. NAND2-NOR2 ComparisonJhon P. UXVpGndX XXXXXXXXVpGndMOS Layout Wiring 17. Activity 2 Sketch a stick diagram for a 4-input NOR gateAVDDGNDB C2: MIPS Processor Example Slide 20YD 18. A OutCJhon P. UStick Diagram - Example IIPowerGroundB


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