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    Ravikiran

    STICK DIAGRAMS

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    VLSI DESIGN FLOW

    D.Ravikiran babu

    Assoc.ProfessorDept of ECE.,

    JITS, [email protected]

    2

    D.R.K.Babu

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    VLSI DESIGN FLOW

    3

    D.R.K.Babu

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    4

    D.R.K.Babu

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    D.R.K.Babu

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    Stick Diagrams

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    Stick Diagrams

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    Stick Diagrams

    Objectives:

    To know what is meant by stick diagram.

    To understand the capabilities and limitations of stick

    diagram. To learn how to draw stick diagrams for a given MOS

    circuit.

    Outcome: At the end of this module the students will be able

    draw the stick diagram for simple MOS circuits.

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    Stick Diagrams

    D.R.K.Babu

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    Stick Diagrams

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    N+ N+

    Stick Diagrams

    D.R.K.Babu

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    Stick Diagrams

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    Gnd

    VDD

    xx

    X

    X

    X

    X

    VDD

    x x

    Gnd

    Stick

    Diagram

    Stick Diagrams

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    Stick Diagrams

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    Gnd

    VDD

    xx

    X

    X

    X

    X

    VDD

    x x

    Gnd

    Stick Diagrams

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    Stick Diagrams

    VLSI design aims to translate circuit conceptsonto silicon.

    stick diagrams are a means of capturingtopography and layer information using simplediagrams.

    Stick diagrams convey layer informationthrough colour codes (or monochrome

    encoding). Acts as an interface between symbolic circuit

    and the actual layout.

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    Stick Diagrams

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    Stick Diagrams

    Does show all components/vias.

    It shows relative placement of components.

    Goes one step closer to the layout

    Helps plan the layout and routing

    A stick diagram is a cartoon of a layout.

    Stick Diagrams

    D.R.K.Babu

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    Stick Diagrams

    Does notshow

    Exact placement of components

    Transistor sizes Wire lengths, wire widths, tub boundaries.

    Any other low level details such as parasitics..

    Stick Diagrams

    D.R.K.Babu

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    Stick encoding(n-mos & p-mos)

    N-diffusion

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    P-diffusion

    Metal 1

    Contact Cut

    Implant

    Polysilicon

    N-diffusion

    P-diffusion

    Metal 1

    Contact Cut

    Implant

    :::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::

    Poly Silicon

    Buried contact

    Color Coding Monochrome Coding

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    Stick diagram:

    green,,yellow n-diffusion, p-difffusion

    Red Polysilicon

    Blue Metal

    Yellow Implant

    Black Contact areas

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    Contact cuts

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    Electrical connections

    Rule 1.

    When two or more sticks of the same type

    cross or touch each other that represents

    electrical contact.

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    Contact cuts

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    Contact cutBuried contact

    Rule 2.When two or more sticks of different type cross or

    touch each other there is no electrical contact.

    (If electrical contact is needed we have to show the connection

    explicitly).

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    Contd.

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    Butting Contact

    Via

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    N-diffusion

    Ploy silicon

    Nmos enhancement transistor:

    Rule 3.When a poly crosses diffusion it represents a transistor.

    Note: If a contact is shown then it is nota transistor.

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    N-diffusion

    Ploy silicon

    Implant

    Nmos depletion transistor:

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    pmos enhancement transistor:

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    p-diffusion

    Ploy silicon

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    pmos DEPLETION MODE transistor:

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    P-diffusion

    Ploy silicon

    Implant

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    Stick diagram for nmos inverter:

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    vin

    gnd

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    Step1:

    Draw metal(blue) VDDand GND rails in parallel

    with enough separation

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    VDD

    GND

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    vin

    Step2:

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    Forming transistors

    gnd

    VDD

    GND

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    Step2-1:

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    vin

    gndVin

    VDD

    GND

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    Step3:

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    vin

    gnd

    Vout

    Vin

    VDD

    GND

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    Step4:

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    vin

    gnd

    VDD

    GND

    Vout

    Vin

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    Vdd

    Vss

    N mos NAND GATE

    A

    Ploy(G)

    Ploy(G)

    s

    s

    D

    D

    B

    Ploy(G)

    Vout(A nand B)

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    Vout(A nor B)

    N mos NOR GATE

    3333

    Vdd

    Vss

    A

    Ploy(G)

    Ploy(G)s s

    DD

    B

    CMOS ENCODING

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    CMOS ENCODING

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    Cmos inverter:

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    Demarcation line

    VDD

    GND

    input output

    Vdd contact

    Vss contact

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    Demarcation

    Line

    Vdd contact

    Vss contact

    Vdd

    Vss

    Vout(A nand B

    A

    Ploy(G)

    Ploy(G)

    Ploy(G)

    Ploy(G)

    B

    s s

    s

    s

    D

    D D

    D

    Cmos NAND GATE

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    Vdd contact

    Vss contact

    Vdd

    Vss

    DemarcationLine

    Vout(A nor B)A

    Ploy(G)

    Ploy(G)

    Ploy(G)

    Ploy(G)

    s

    s

    s s

    D

    D

    D

    D

    B

    Cmos Nor GATE

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    Vss contact

    Vdd

    Vss

    Demarcation

    Line

    Vout

    Vdd contactBiCmos inverter

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    Vdd

    Vout

    Vdd contactBiCmos inverter