stp-uoai spacewire in russiaspacewire.esa.int/wg/spacewire/spw-snp-wg-mtg6...spacewire in russia...
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SpaceWire in RussiaProf. Yuriy Sheynin
St. Petersburg State University of Aerospace InstrumentationInstitute of High-Performance Computer and Network Technologies
190 000 St. PetersburgBolshaya Morskaya str., No 67
Fax: +7 812 3157778E-mail: [email protected]
Tatyana Solokhina,ELVEES company,
R&D Director Moscow Phone: 913-31-88
[email protected]. ELVEES.RU
SpaceWire implementation: IP-cores, chips, boards
2006, Q1PCI104 SpaceWire Kit
DSP module with SpaceWire linksBoards
2006, Q4 samples,2007
MCK-0116-channel SpaceWire routing switch
2006, Q4 samples,2007
MCB-01SpaceWire multichannel communication controller bridge (ASIC implementation)
2006, Q2 samples,2007
МСТ- 01MultiCore Terminal Controller with SpaceWire links
Chips
2005MCB-SpW-F SpaceWire multichannel communication controller bridge (FPGA implementation)
2005SWIC2SpaceWire Network Interface Controller with AMBA AHB interface
2005SpWCore2SpaceWire Network Interface Controller IP-core
2004 SpWCodec2SpaceWire Codec IP-block
IP-cores
TimescaleCodeTypeClass
MiT
Hierarchy of IP-blocks for SpaceWire
SpaceWire Network Interface Controller with AMBA AHB interface SWIC2
SpaceWire Network Interface Controller SpWCore2
SpaceWire
Codec
SpWCodec2
TX_Data
TX_Code
RX_Data
RX_Code
D_IN
TC_IN
TC_OUT
D_OUT
AHB MASTER
AHB SLAVE
S
D
S
D
State
Machine
FCT Generator
Control Unit
FIFOs
DMA
D_IN
D_OUT
MiT
SpWCodec2IP-block SpaceWire Codec
CLK
CLK_TX
LB_EN
RX_EN
TX_DATA(7:0)
TX_EN
TX_TYPE(3:0)
RX_CON
RX_DATA(7:0)
RX_ERR(2:0)
RX_SPD(7:0)
RX_TYPE(6:0)
TX_READY
TxD
TxS
RxD
RxS
IP-block complexity:• ASIC – 500 logic gates, • FPGA – 250 LUT
• High-speed duplex link:5 Mbit/s to 400 Mbit/s in each direction (@ 0,25 µm )
• Completely synchronous interface (interface signals are fixed on ascending front)
• RX clock computation scheme (detection up to 800Mbit/s)
• LoopBack included
• The ratio of local and reception frequencies is 1:6
• Small number of triggers working on TX and RX clock
MiT
IP-core SpWCore2
• High-speed duplex link:5 Mbit/s to 400 Mbit/s in each direction (@ 0,25 µm )
• Transmits/receives data packets, time codes and distributed interrupts signals
• Simple parallel interfaces with typical FIFO
• 2 levels of LoopBack
• Programmable crediting scheme depending on the sizes of the reception buffer (16, 32, 64 and 128 words)
• Completely synchronous interface (interface signals are fixed on ascending front)
• RX clock computation scheme (up to 800Mbit/s)
MiT
RSTn
CLK
FIFO_DEPTH(1:0)
TC_THREADING(1:0)
RxD
RxS
D_IN(7:0)
TC_IN(7:0)
TxD
TxS
D_OUT(7:0)
TC_OUT(7:0)
D_OUT_W E
D_OUT_CTRL(1:0)
D_IN_RE
TC_IN_RE
TC_OUT_W E
TxCLK
TC_IN_READYn
D_IN_READYn
LINKENABLE
LINKSTART
AUTOSTART
D_IN_CTRL(1:0)
STATUS(2:0)
EXT_LOOPBACK
INT_LOOPBACK
STATE(2:0)
D_OUT_FIFO_EMPTY
D_OUT_FIFO_HEMPTY
Compexity:ASIC – 1100 gates, FPGA – 550 LUTs
SpaceWire Network Controller SWIC2• 5 Mbit/s to 400 Mbit/s in each direction
(@ 0,25 µm )
• Transmits/receives data packets, time codes and distributed interrupts signals
• 32-bit AMBA AHB bus interface (master/slave), 100MHz
• Parameterized internal FIFOs in both directions (8, 16, 32, 64, 128 words).
• DMA component, multi-channel (32-bit AMBA AHB master)
• 3 interrupts on the AMBA AHB(error in link, packet reception, time labels or distributed interrupts).
• 3 levels of LoopBack included (DS-codec, SpWCore2, Controller SWIC2)
• RX clock computation scheme
LCLK
RxD
RxS
SCLKAHB_MASTER
AHB_SLAVE
HRST
IRQ
IRQF(3:0)
TxD
TxS
HCLK
Compexity:ASIC – 6300 gates, FPGA – 3000 LUTs
MCB-01SpaceWire multi-channel communication controller bridge
SWIC_1master
slave
SWIC_2master
slave
SWIC_3master
slave
SWIC_4master
slave
master
SRAMslave
IRQ registerslave
AHB
MPORT slave interface IRQ interface
master0Master 1
Master 2
Master 3
Master 4
Slave 0
Slave 1,2
Slave 3,4
Slave 5,6
Slave 7,8
Slave 9
AHB_clk
RAM communication system
PCI master/slave
MCB-SpW-FSpaceWire multichannel communication controller bridge
(FPGA implementation)
Xilinx Spartan-3 1500FPGA type
16 KbytesInternal buffer RAM
32-bit, 40 ns, SRAM-likeExternal interface
From 2 Mb/s up to 400 Mb/s SpaceWire channel speed
4 SpaceWire channels
WWW. ELVEES.RU
2007200520042004Production
HSBGA, > 600HSBGA416HSBGA292PQFP240Package
5760025600
9600
86403840
1440
36001600
600
1800800
300
Performance:8b, Int , MOPs16b Int, MOPs32b, float, (IEEE754), Mflops
400 (6.5/3.3)
120 (1.8)
100 (1.4)
100 (1.2)
CLK, MHz /Power (W)
RISCore32 (MIPS32) + 4xDSP(ELcore-28)(MIMD)
RISCore32 (MIPS32) + 2xDSP(ELcore-26)(MIMD)
RISCore32 (MIPS32)+ 1xDSP (2SIMD) (ELcore-14)
RISCore32 (MIPS32)+ 1xDSP (ELcore-14)
Multi-core chip,MIMD
(RISC+nxDSP cores)
65~8
~263
~192
~182
Transistors, mln. /on-chip RAM (Mbit)
0,18/0.130,250,250,25Implementation technology, µm
MCF- 0428,(Test chip – МС-0128)
1892ВМ4Я/1892ВМ5Я
1892ВМ2Т((MC-24)
1892ВМ3Т(МС-12)
Multi-core chip(RISC+DSP cores)
Multi-core DSP chips “ MULTICORE”
Development Kit and Software Tools for “MULTICORE” DSP chips
MCStudio
ГУПГУП НПЦНПЦ ««ЭЛВИСЭЛВИС»» ©©, , 20020066 10
МСТ- 01MultiCore Terminal Controller with SpaceWire links
CPU JTAG
Flash SRAM
SDRAM IO
SpaceWire interface
AMBA AHB
AXI Switch
UART TIMERS Interrupt controller
On chip debugger (OnCD)
SWIC
MPORT DMA
Dual-port RAM
4 channel ADC
4 channel ADC
4 channel DAC
On chip debugger (OnCD)
RISCorE
On chip debugger (OnCD)
FPU
GPIO
PLL
Engineering samples2Q 2006.
9.5x9.5 мм2
CMOS, 0.25 µm3.3В
PCI104 SpaceWire Kit
Microprocessor MC24
SDRAM 32МB Flash
16МB
SpW controller Xilinx Spartan-3
XC3S1500FG320
FPGA configuration
PROM
Microprocessor Bus
6x SpaceWire connectors
RS-232 connector
The one-board high performance DSP module: - a ready-made building block
• for SpaceWire-compatible EGSE systems• for on-board distributed & parallel space data systems prototypes with high-speed SpaceWire communication technologies.
PCI104 form-factor
PCI104 SpaceWire Kit
MCStudio Tools for MultiCore-24programming
LinuxSpW links driver
Software
10 W max.Power consumption
5 V Power supply
RS-232EJTAGOther interfaces
32 (8 for ROM)CPU bus width
FlashType
16-64 MBytesCapacityROM
SDRAMType
32 MBytesCapacityRAM
up to 600 MflopPerformance
Double core (RISC+DSP) On-chip RAM (3 blocks)RISC core – MIPS32 arch.
Features
1892ВМ2Т(“MultiCore-24”)Type
Processor
2 to 400 Mb/s,duplexRates
4 - 6Number of linksSpaceWire
links
Microprocessor MC24
SDRAM 32МBFlash
16МB
SpW controller Xilinx Spartan-3
XC3S1500FG320
FPGA configuration
PROM
Microprocessor Bus
6x SpaceWire connectors
RS-232 connector
MCK-0116–channel SpaceWire routing switch
• Supports signal, symbol, exchange, packet, network protocol stack levels• Advanced non-blocking internal switching fabric• Supports adaptive routing• Supports multicast routing• Provides time-codes distribution in compliance with the ECSS-E-50-12A
SpaceWire standard• Provides interrupt codes and poll codes distribution in compliance with the
project of the second part of the ECSS-E-50-12A SpaceWire standard• Includes the internal RISC core for configuration, monitoring and network
administration purposes
Interfaces:
– 16 full-duplex SpaceWire interfaces– Transmission rate of each interface from 5 Mb/s to 400 Mb/s;
can be set independently for every of 16 links– Parallel interface to external static memory– Parallel SRAM-like interface to external RISC processor
(includes masked interrupt signal)
MCK-01SpaceWire routing switch
SpaceWire Switch (MCK-01)
SpWPort1
SpWPort8
SpWPort9
SpWPort16
Configuration port
Time-code processing engine
Interrupt&poll code processing engine
Switching fabric Routingtable
RISC core Registers RAM
MBAMemoryport
Processor busMemory bus(SDRAM, RAM, ROM)
Packet buffer
… …
MCK-01 applications(without external processor)
SpaceWire Switch (MCK-01)
RISC core
ROM
SpaceWire Switch (MCK-01)
RISC core
ROMROM
RAM
Memory bus Memory bus
MCK-01 applications(with an external processor)
SpaceWire Switch (MCK-01)
RISC core
ROM ROMRAM
External RISC processor
ROMROMRAM
SpaceWire Switch (MCK-01)
External RISC processor
ROMROMRAM
Processor bus
Processor bus
Memory bus
SpaceWire implementation: IP-cores, chips, boards
2006, Q1PCI104 SpaceWire Kit
DSP module with SpaceWire linksBoards
2006, Q4 samples,2007
MCK-0116-channel SpaceWire routing switch
2006, Q4 samples,2007
MCB-01SpaceWire multichannel communication controller bridge (ASIC implementation)
2006, Q2 samples,2007
МСТ- 01MultiCore Terminal Controller with SpaceWire links
Chips
2005MCB-SpW-F SpaceWire multichannel communication controller bridge (FPGA implementation)
2005SWIC2SpaceWire Network Interface Controller with AMBA AHB interface
2005SpWCore2SpaceWire Network Interface Controller IP-core
2004 SpWCodec2SpaceWire Codec IP-block
IP-cores
TimescaleCodeTypeClass
MiT
Latest news:
• The Federal Space Agency of Russian Federationis to apply officially in support of the SpaceWire
technology
Thank you!SpaceWire