structured analog cmos design - gbv

STRUCTURED ANALOG CMOS DESIGN

DANICA STEFANOVIC

and

MÄHER KAYAL Ecole Polytechnique Federale de Lausanne, Switzerland

Springer

Table of Contents

1 Introduction

1.1 The objectives of this work 2

1.2 Structured analog design 3

1.3 Transistor-level design based on the device inversion level 4

1.4 CAD tools for analog design assistance 5

1.5 Practical design example 5

1.6 Book organization 5

2 Transistor level design

2.1 MOS transistor model 7

2.1.1 Overview of MOS models 8

2.1.2 MOS model oriented towards transistor-level design 10

2.2 Transistor design parameters 10

2.2.1 Transistor symmetry and voltage definitions 11

2.2.2 Operating regions 12

2.2.3 Strong inversion, pinch-off voltage and slope factor 13

2.2.4 Weak inversion 15

2.2.5 Drain current and specific current 16

2.2.6 Saturation drain current and saturation voltage 18

2.2.7 Inversion factor as a measure of the device inversion

level 20

2.2.8 Transconductances 20

2.2.9 Normalized transconductance 22

2.2.10 Capacitances 24

2.2.11 Intrinsic gain 26

2.2.12 Transition frequency 27

2.2.13 Intrinsic noise 27

2.3 Design approach 28

2.3.1 Design parameters and design variables 28

2.3.2 Table of design parameters as functions of

the design variables 30

2.3.3 Analyses of design parameters as functions of

the design variables 32

2.3.4 Design steps 40

2.3.5 Design recipes 41

2.4 Conclusion 46

Bibliography 48

3 BSIM to EKV conversion

3.1 Motivation and purpose 51

3.2 Conversion concept 52

3.3 BSIM versus EKV, the fundamental differences and

the conversion algorithm guidelines 53

3.4 Conversion algorithm 55

3.4.1 Initialization 57

3.4.2 Specific current calculation 59

3.4.3 Extraction of parameters VTO, GAMMA and PHI 60

3.4.4 Extraction of parameters LETA, WETA, and LK, QO 60

3.4.5 Extraction of parameters KP, E0 61

3.4.6 Extraction of parameters RSH, DL 62

3.4.7 Extraction of parameters UCRIT, LAMBDA 62

3.4.8 Extraction of parameters IBA, IBB, IBN 64

3.4.9 Extraction of parameters TCV, BEX, and UCEX 64

3.4.10 Extraction of parameters KF, AF 64

3.5 Conversion results 64

3.5.1 The 0.18 |xm CMOS technology conversion example 68

3.5.2 Results interpretation for analog design 72

viii

3.6 Conclusion 73

3.7 Download 73

Bibliography 74

4 Basic analog structures

4.1 Introduction 77

4.2 Basic analog structures library 77

4.2.1 Transistor in a design environment 80

4.3 Structured design approach 81

4.3.1 Circuit partitioning 82

4.3.2 Derivation of the specifications 83

4.4 Transconductance structures 87

4.4.1 Common source 87

4.4.2 Common drain 89

4.4.3 Common gate 92

4.4.4 Cascode and folded cascode 95

4.4.5 Differential pair 98

4.5 Load structures 107

4.5.1 Simple current mirror 107

4.5.2 Cascode current mirror 109

4.6 Bias structures 110

4.6.1 Voltage bias 110

4.6.2 Current bias 112

4.7 Conclusion 114

Bibliography 115

5 Procedural design scenarios

5.1 Introduction 117

5.1.1 Procedural design sequence for an analog amplifier 117

5.1.2 Definitions of the circuit-level design parameters 120

5.2 Procedural design scenario for a folded-cascode OTA 127

5.2.1 Circuit-level design parameters 127

5.2.2 Frequency analysis 130



5.2.5 Procedural design sequence 136

5.3 Procedural design scenario for a fully-differential folded

cascodeOTA 141






5.4 Procedural design scenario for a Miller operational amplifier 156






5.5 Conclusion 166

Bibliography 167

6 PAD tool

6.1 Introduction 169

6.1.1 Overview of analog CAD tools 170

6.1.2 Procedural Analog Design (PAD) tool 171

6.2 PAD structure 173

6.2.1 Chart-based graphical interface 174

6.3 Basic analog structures library 174

6.4 Procedural design scenarios 177

6.4.1 Example of the procedural design for

a folded cascode OTA 178

6.4.2 Example of the procedural design for

a Miller operational amplifier 178

6.5 BSIM and EKV model library file input 183

6.6 Conclusion 184

6.7 Download 184

Bibliography 185

7 Topology variants

7.1 Basic concept 189

7.1.1 Design example: fully-differential folded cascode OTA

and its CMFB amplifier 189

7.2 Gain enhancement - two stages 192

7.2.1 Miller compensation 193

7.2.2 Cascode Miller compensation 196

7.3 Gain enhancement - gain boosting 200

7.4 Input common-mode range enhancement - complementary

differential pair 206

7.5 Differential input range enhancement - linearized differential

pair 210

7.6 Rejection of the differential signal in a common-mode signal

- cascoded current bias sources 214

7.7 CMFB stability improvement- split bias sources 216

7.8 Conclusion 219

Bibliography 220

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8 Practical example: the design of analog amplifiers in the Delta-Sigma modulator system

8.1 Delta-Sigma modulator system 221

8.1.1 Design flow 223

8.1.2 Verification of the performance 225

8.2 Derivation of the testbench 227

8.2.1 Fully-differential difference amplifier 227

8.2.2 Fully-differential amplifier in the first integrator 229

8.2.3 Fully-differential amplifier in the second integrator 230

8.3 Topology selection 233

8.3.1 Analysis of technology limits 234

8.3.2 Topology variants to fulfill the additional design

requirements 237

8.4 Design of the fully-differential high-gain amplifier 238

8.4.1 Equivalent output load 240


8.4.3 Simulation results 248

8.5 Design of the fully-differential difference amplifier 251



8.6 Design of the fully-differential two-stage amplifier 267

8.6.1 Equivalent output load 267

8.6.2 Additional design requirements for

the continuous-time integrator 270



8.7 Conclusion 279

Bibliography 280

Index 281

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structured analog cmos design - gbv

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