5/24/2001

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Study of Gate Line Edge Roughness Effects in Short Channel MOSFET

SFR WorkshopMay 24, 2001

Shiying Xiong, J. Bokor

UC Berkeley

Qi Xiang, Philip Fisher at al.

STG of AMD

2001 GOAL: Simulations for AMD device designs at 100nm, 70 nm, and 50 nm gate length, including effect of

isolation roughness by 9/30/2001.

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Motivation• This aims to quantify poly gate LER of the most advanced

devices, and to model and investigate its effects.

• Several possible LER effects has been simulated:

•Increase on leakage and driving current

•Variation of Vt

•Effect on lateral diffusion and doping profile

• An efficient description of LER from direct measurement of poly lines in advanced MOSFET has not been established

• Substantial experimental data of devices with different LER must to be obtained to make a meaningful comparison with simulation results.

•

•

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SEM Poly LER Measurement

SEM current scan over line

One scan

Multi-box measurement on each poly line and 64 Scans in each box

x

y

Max resolution:

x:~0.8nm

y:~3nm

LER Measurement and Characterization

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x

y

LER Measurement and Characterization

Line edges are extracted by processing SEM current data

-10 0 100

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-10 0 100

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-10 0 100

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-10 0 100

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Unit: nm

Typical poly line edges: (List from left to right)

1.Top left edge

2.Top right edge

3.Bottom left edge

4.Bottom Right edge

1

3

2

4

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LER Characterization

yi

y

Lix Rix

Scan #i

Lix Left edge position

Rix Right edge position

64:1,

iRRiLLi xxxxMaxMED

•Width Variation Range

MinWMaxWWVR

•Average Line width

•Maximum Edge Deviation from the Mean

•Edge RMS

64

1

22

2

1

64

1

iRRiLLix xxxxRMS

•Width RMS:

64

1

2

64

1

iiW WWRMS

LER Measurement and Characterization

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•Distribution of line width (MOSFET gate length ) subtracted the mean

-10 -8 -6 -4 -2 0 2 4 6 8 100.00

0.02

0.04

0.06

0.08

0.10

Pro

bab

ility

W - Wmean (nm)

Fit function Cut 3-tail Gaussian

2

32

32

2

2

Erf

LLUeLP

LL

RMS U:Unit step function

LER Measurement and Characterization

•LER Frequency properties

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.080

2

4

6

8

10

12Pxx - X Power Spectral Density

Frequency

Lc*2

1

Power spectral density

FFT of edge waveform Power Spectral Density

Correlation Function

*Observed line RMS value was reduced ~ 10% if filtering off LER period small than Lc

Correlation length

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LER Experiments with AMD• Characterize LER on AMD wafer and develop ways to vary LER

• Simulate LER effect on AMD device using our method

• AMD fabricates devices with different LER values

• Comparison experimental data with simulation results

We have developed methods to measure and characterize LER

AMD Results so far has not given reliable increase of LER

Need to work harder to increase LER for the study purpose

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Simulation of LER Effect on AMD 50nm Technology

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qkTVdf e

Doff eCLI

/)(2,LCCLI Don /)( 212,

1.Fit leakage and driving current of 2D devices with different gate length

Estimation of 3D long period LER device current from 2D Simulation

max

min23

L

LdDD LLPLIWI

2. Get the current from the following equation

700 750 800 850 900 950 1000 1050 1100 1150

10

100

1000

Nominal device

NMOS:Red: RMS_W=0Green: RMS_W=2nmBlue: RMS_W=4nmBlack: RMS_W=6nm

Ioff

(Log

Sca

le)

Ion (Linear Scale)

3. Comparison on devices with different LER from simulation

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Conclusion• Line width RMS:1.5nm~4.5nm, Line Edge RMS: 1nm~3.5nm RMS does

not scale with line width, Maximum edge deviation ~3.

• Lc is generally greater than 25nm, the power of high frequency (wavelength <Lc) line edge variation is small, so HF LER is insignificant.

• The prospective 50nm technology is insensitive the typical LER (Lc> 25nm, RMS_W 1.5~4.5nm) produced in process.

• We need to produce LER with 4-6nm RMS to test our model

MilestonesWafers processed at AMD finished with varying, and well-characterized LER by 9/30/2002 (This will likely be completed by 12/31/2001).

Device characterization on AMD wafers completed and data analyzed by 9/30/2003 (This will also be significantly accelerated)