subject: 8086 maximum mode sbc

Subject: 8086 maximum mode SBCPosted by lynchaj on Sun, 30 Apr 2017 18:03:00 GMTView Forum Message <> Reply to Message

HiI've been mulling over an 8086 maximum mode SBC based on the Intel datasheet. It is simplecomputer with just CPU, RAM, ROM, & DUART. No PIC, PIT, DMA, and no wait state generator. Take a look at the schematic and tell me what you think.

The PCB is fairly small & 2 layer 5.525" x 4.700" which I am guessing would be fairly inexpensiveto build. All the parts a PTH so easy construction.

Note1: I noticed there was a problem with the memory decoder so I fixed it and updated theschematic. Also included the memory decode truth table and the PCB layout file.

Note2:Argh! I thought about the IO decoder some more and realized if I made some minorchanges I could use left over gates and eliminate the second 74LS688 so I updated the schematicand PCB layout (again).

Subject: Re: 8086 maximum mode SBCPosted by lynchaj on Mon, 01 May 2017 11:42:56 GMTView Forum Message <> Reply to Message

Hi

The 8086 maximum mode SBC is in no way intended to be IBM PC compatible. In fact, just theopposite. I'd like it to be a clean sheet design without any of the limitations of the IBM PC heritagedesign.

So far, it is an 8086 CPU with 1MB SRAM, 256KB Flash ROM, a DUART which provides twoUARTs and a parallel printer port. Also added a general purpose output latch (used to swap the256KB Flash ROM in/out of memory after booting) and an IDE port (which is practically free on 16bit x86 computers).

Is anyone interested in collaborating on said project? I am considering building this one myselfsince I never seem to get to do that anymore.

Subject: Re: 8086 maximum mode SBCPosted by jcoffman on Mon, 01 May 2017 15:07:02 GMTView Forum Message <> Reply to Message

Andrew,

Before the NS32202 was put on the MF/PIC board, I did a series of experiments with the NEC8289A. Perhaps it is easy to interface it to 80x86 systems, but I was unable to get it to work with

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a Z80. Part of the problem was the 8289 data sheet -- clear as mud.

Note that the 8086, in taking an interrupt, must read the 8289 twice. This seems to me to be avery odd requirement, and may have been part of the reason I could not use the 8289 on a Z80.

I was looking at the 8289 because I felt it was easier to source than the NS32202 chip, and thelatter worked fine on Z80, NS32000, and later on Motorola 68000's. By buying the '202 in bulkand providing it with the board, the chip sourcing problem was solved.

===============================================

BTW: if we can get the VGA3 board to work satisfactorily, I've considered a re-spin of theSBC-188, mainly to add full memory (2 x 512K chips). The board is known to run as it is at25mhz, but needs to be slowed to 16mhz to access off-board 4MEM. A re-spin needs to addressthe wait-state problem with off-board accesses.

===============================================

RE: pure 8086 & software

The SBC-188 was intended to be a non-MSDOS computer entirely. However, the lesson learnedis that one wants to run available s/w, and MSDOS is the most available. The earliest revision ofthe SBC-188 (timer fix), made it a little more like a PC. There are several other things to be doneto make it even more like a PC, and these would be incorporated into any re-spin. However, the'188 will NEVER be a total PC-clone. An 8086 could be. Plan on running MSDOS.

============================================================ ===

For running Linux on a home-built PC, have you looked at Mark Williams' COHERENT. It will runon a 386, with relatively little memory. It is more a clone of System V, since it pre-dates Linux'wide acceptance. It is now open source.

--John


Hi John, did you mean 8259A (programmable interrupt controller) instead of 8289A? The 8289Ais a bus arbiter for Multibus although it looks like an interesting addition to the SBC. For instance,it provides AEN# which is useful for an expansion bus. The current 8086 SBC does not supportexpansion bus of any kind. Everything is CPU local bus for now.






Frankly, I would like to get away from the IBM PC standard for how it implemented itson-the-mainboard peripherals. Its practically a war-crime. I think the PIC and PIT could be usedto much greater potential. For instance, I think the PIC could support a *lot* more interrupts with aslightly different configuration and an adjusted interrupt service routine (see the other thread on8259A PIC in General Discussion). Similarly with the PIT, however the PIC has to be workingbefore the PIT can be used so the CPU can utilize the PIT interrupts.


Hi JohnWould you be interested in a re-design of the SBC-188 to incorporate an 8086, PIC, PIT, andDMA? It is probably too big to put on a 160x100mm Euro board but it might fit on a double stackboard (like the uPD7220). If we were to go down that road though, I would like to implement thePIC (and the PIT) differently than the IBM PC did. I think the PIC could support 256 differentinterrupts with level detection vs. edge detection along with a different interrupt service routine. Also the PIT could have three separate interrupts (one for each timer channel). With 256interrupts we could assign them with abandon rather than hoard them like you have to do with thecurrent IBM PC/ISA architecture. Every device could have its own unique interrupt or even morethan one if needed for separate modes, etc.

I am thinking the PIC would receive multiple interrupts at once, read them as levels, update itsinternal registers, and call the CPU via the INTR line. Then the CPU passes the INTA line back tothe PIC and reads the internal PIC registers to assess which interrupt was called (status of IRR)then clears the PIC. The CPU would handle the rest via its interrupt service routine. Does thatmake sense? It's a theory I've held for a long time but never had a chance to experiment with.

Thanks, Andrew Lynch

PS, the 8259A datasheet says the PIC supports level detection and multiple interrupt requests. From the datasheet:

The events occur as follows in an 8086 system:1. One or more of the INTERRUPT REQUEST lines (IR7±0) are raised high, setting thecorresponding IRR bit(s).2. The 8259A evaluates these requests, and sends an INT to the CPU, if appropriate. 3. The CPU acknowledges the INT and responds with an INTA pulse.4. Upon receiving an INTA from the CPU group, the highest priority ISR bit is set and thecorresponding IRR bit is reset. The 8259A does not drive the Data Bus during this cycle.5. The 8086 will initiate a second INTA pulse. During this pulse, the 8259A releases an 8-bitpointer onto the Data Bus where it is read by the CPU.6. This completes the interrupt cycle. In the AEOI mode the ISR bit is reset at the end of thesecond INTA pulse. Otherwise, the ISR bit remains set until an appropriate EOI command isissued at the end of the interrupt subroutine.







Yes, I totally mean the Interrupt Controller, 8259A (not 8289).

You can argue that the IBM-PC architecture has its flaws, but there is too much s/w written for it toignore. I found the Intel PIC architecture to be a bit odd. I think it was meant to work originallywith the 8085, and was never updated to a newer version for the 8086.

--John


jcoffman wrote on Mon, 01 May 2017 12:01Yes, I totally mean the Interrupt Controller, 8259A (not8289).

You can argue that the IBM-PC architecture has its flaws, but there is too much s/w written for it toignore. I found the Intel PIC architecture to be a bit odd. I think it was meant to work originallywith the 8085, and was never updated to a newer version for the 8086.

--John

Hi John,According to the 8259A datasheet there is both an MCS-80/85 and an 8086 mode in the PIC. They are different but very similar. What IBM did with the PIC and PIT (and even more ghastlyMDA and CGA boards) are crimes against nature and it doesn't have to be that way. Unfortunately the software written for the IBM PC had to be written "on the metal" as to extract outevery last bit of performance. Why application software is dependent on ISR implementations ismind-boggling to me.


lynchaj wrote on Mon, 01 May 2017 09:10

<snip> ... Unfortunately the software written for the IBM PC had to be written "on the metal" as to extractout evs) areery last bit of performance. Why application software is dependent on ISRimplementations is mind-boggling to me.












I think IBM wanted the BIOS to insulate applications from the underlying h/w, but seeking speedon a 4.77mhz 8088, vendors had to talk directly to the h/w. This IBM-intentded BIOS insulationextended to the WAIT and POST calls in the early PC/AT's. These calls were intended to supportmulti-programming / multi-tasking operating systems. Later BIOS's did not support these calls,because the OS's (Windows 3.1, OS/2, e.g.) all wanted to do the multi-tasking on their own.

In my opinion, it was subtle incompatibilities that doomed the IBM PS/2. About the only goodthing to come out of it was the smaller keyboard and mouse connectors. :)

--John

Subject: Re: 8086 maximum mode SBCPosted by Sergey on Mon, 01 May 2017 22:43:54 GMTView Forum Message <> Reply to Message

A "properly designed" 8086 board is an interesting idea. Here are some of my wishes/additions:1. Integrate an 8087, and a couple of 8089's (otherwise what's the point of using the MaximumMode?). Use the latter ones for DMA purposes...2. Make it a multi-processor system (Multibus-style?!) using an 8289 bus arbiters?3. Integrate an 8259A PIC and an 8254 PIT. 4. Think about some non-DOS OS to run on it. Some kind of UNIX-like system? Xenix? Minix?


For your reference, some 8086/88 application notes:AP-51 and AP-67 are particularly interesting

File Attachments1) 000105_AppendixA_4.pdf, downloaded 318 times2) 000105_AppendixA_3.pdf, downloaded 275 times3) 000105_AppendixA_1.pdf, downloaded 265 times4) 000105_AppendixA_2.pdf, downloaded 504 times5) 000105_AppendixA_5.pdf, downloaded 232 times









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And one more file...

File Attachments1) 000105_AppendixA_6.pdf, downloaded 236 times

Subject: Re: 8086 maximum mode SBCPosted by lynchaj on Tue, 02 May 2017 10:10:05 GMTView Forum Message <> Reply to Message

skiselev wrote on Mon, 01 May 2017 18:43A "properly designed" 8086 board is an interestingidea. Here are some of my wishes/additions:1. Integrate an 8087, and a couple of 8089's (otherwise what's the point of using the MaximumMode?). Use the latter ones for DMA purposes...2. Make it a multi-processor system (Multibus-style?!) using an 8289 bus arbiters?3. Integrate an 8259A PIC and an 8254 PIT. 4. Think about some non-DOS OS to run on it. Some kind of UNIX-like system? Xenix? Minix?

Now that's a good idea! Check out the datasheet for the 8289, it is right along these lines. Includes Multibus signal for multiprocessor applications.

Agree 100% on the 8087 and especially the 8089(s). What a difference those would make tooffload the IO to its own processor.

Yes, not DOS although maybe FreeDOS would be a good intermediate point. Start with a monitorand work out all the issues with the hardware and then port an OS. Maybe Coherent? I don'tknow.

I looked over the 8086 maximum mode SBC design last night and added the 8259A PIC and 8254PIT. After reading the datasheets they were fairly easy to add since they require almost noadditional glue logic or anything other than a few pull-up/pull-down resistors. I'd like to build thecore 8086 maximum mode CPU first and make sure that's working. Then integrate in the moresophisticated 8087, 8089, 8289, etc. I have some more to do tonight and will update theschematic & PCB layout.


Wow, where did you get those application notes? Very interesting. Much better than thedatasheets alone. They answered a lot of questions.

I will add in the 8087, 8289, and 8089 chips tonight. It looks like those can be left as emptysockets and the chips added later as testing progresses.

It looks like with the 8289 and the 8089 installed it would support multiprocessing. A simple form










of that would be to export the "system bus" to some pin headers and make it "stackable" somultiple SBCs could work in parallel. Very interesting.

What's even more interesting is the concept extends to the PIC as well since they can be"chained" in a master/slave configuration. Need to make some adjustments to my schematicthough.


It looks like the initial 8086 maximum mode SBC can keep everything on one PCB for testingpurposes, however, to exploit the multiprocessor capabilities fully the board would have to breakup into separate CPU, IO, and memory boards. Then there could be multiple CPU boards sharingcommon IO and memory boards.


Thinking about this some more, I think what I'll do is move the PIT and PIC (master) and add aPIC (slave) to the CPU sheet. The CPU + IOP + numeric coprocessor + PIT use up at least sixinterrupts alone and are high priority. I think they warrant their own PIC (slave) connected to thePIC (master) IRQ0.

Then at a dedicated PIC (slave) just for IO peripherals. Start thinking about making that aseparate board. Same with memory. They are already sub-schematics so that should be prettyeasy.

Whatever future expansion bus would need to include the Multibus signals from the 8289 as wellas the IRQs from the PIC (master) and the CAS lines. The insight is the PIC (master) and PIT arereally part of the core CPU and not really peripherals in the usual sense.

This is a pretty big rework and it might take some time to get it all sorted out. I'll post an updatedschematic when its ready.

Subject: Re: 8086 maximum mode SBCPosted by lynchaj on Wed, 03 May 2017 10:14:34 GMTView Forum Message <> Reply to Message

Hi, did a bunch of rework on the design last night but never made it to the 8289 and 8089 chips. Of course those don't exist in the KiCAD libraries so first I'll need to make them and then addthem to the design. Also had some revelations after some rework. For instance, the SBC needsan RTC. Also provisions for FDC and the DMA chip. The memory decoder approach can be












further simplified to eliminate gate delays. So a bunch more rework tonight. Hopefully I can posta new set of schematics maybe today or tomorrow.

Subject: Re: 8086 maximum mode SBCPosted by Sergey on Wed, 03 May 2017 15:45:55 GMTView Forum Message <> Reply to Message

I am wondering if it can be designed in a modular way? Something like this:1. A backplane (it might contain an arbitration circuit to allow multiple 8086 boards)2. One or more 8086/8087/8089 processor modules, with some local memory, and perhaps aUART. These modules can be operated either as a standalone SBC, or plugged into thebackplane mentioned above... They might have a split memory and I/O address space, such thatpart of this address space is used for local to SBC devices, and the rest goes to the backplaneconnector.3. I/O boards (HDD, FDC, display).


Hi,

Yes, I agree. I am taking steps in that direction now by dividing the PCB into partitions. It will bea rectangle with 3 partitions, left to right 1. peripherals, 2. CPU, 3. memory.

Each partition is completely separate (no shared components) and would form its own board in abackplane. However, we don't have a backplane defined yet and I'd like to shake out the basicdesign before committing to multiple PCBs.

I've thought briefly about a backplane standard and I am leaning towards a hybrid approach. Ireally like the DIN connectors (like ECB) much better than card edge. However I like the AT ISAform factor. So I was thinking like an 8086 version of ECB using a DIN 41612 (4 row) connector. I like Multibus but its just huge (expensive) and requires Multibus card cages & its card edge.

Something like a 4"x13" rectangle with this connector similar to an AT ISA board

https://www.digikey.com/product-detail/en/hirose-electric-co-ltd/PCN10A-128P-2.54DS(72)/H124237-ND/2410699













If you want to go low cost, then we could use pin headers but we'd need a lot of them. At least100 by my counts. I think card edge connectors suck. DIN 41612 much better. Euroboard(160x100 mm) is too small for this technology.


Also regarding modular design, one thing I'd like to avoid is ROMs permanently in the memorymap and memory mapped peripherals (CGA, MDA, and their progeny). VGA is possible bydesigning a small 8086 SBC with a VGA chip and then placing it on the IO bus. Communicate bydisplay list. Similar for other peripherals.


I think AP-50, figure 1, page A-88 captures pretty well what a system bus would look like. Probably add in the 8289 signals too though.

File Attachments1) 8086 MM system bus.png, downloaded 1436 times

Subject: Re: 8086 maximum mode SBCPosted by jcoffman on Wed, 03 May 2017 19:39:44 GMTView Forum Message <> Reply to Message

lynchaj wrote on Wed, 03 May 2017 10:50If you want to go low cost, then we could use pinheaders but we'd need a lot of them. At least 100 by my counts. I think card edge connectorssuck. DIN 41612 much better. Euroboard (160x100 mm) is too small for this technology.

Consider the 160mm x 233.35mm Eurocard format used by VME.

With the 96-pin DIN 41612 on the right connector (landscape format), the ECB bus could besupported in the Siemens 6508 chassis.

Subject: Re: 8086 maximum mode SBCPosted by Sergey on Wed, 03 May 2017 22:06:16 GMT














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Here are a couple of 8086 User Manuals. It appears that they include all the application notes I'veattached in the thread above, and even more... http://bitsavers.trailing-edge.com/pdf/intel/8086/9800722-03_The_8086_Family_Users_Manual_Oct79.pdf ftp://bitsavers.informatik.uni-stuttgart.de/pdf/intel/_dataBooks/1981_iAPX_86_88_Users_Manual.pdf

The 8086/8087/8089 combination was apparently called iAPX 86/21. Unfortunately I can't find anyreference designs, schematic, or detailed documentation about iAPX 86/21...

Subject: Re: 8086 maximum mode SBCPosted by mikemac on Thu, 04 May 2017 01:33:31 GMTView Forum Message <> Reply to Message

lynchaj wrote on Wed, 03 May 2017 10:48Hi,




NuBus! The ones Apple used in their 68K Quadras et al are pretty much that.

Subject: Re: 8086 maximum mode SBCPosted by lynchaj on Thu, 04 May 2017 12:02:23 GMTView Forum Message <> Reply to Message

skiselev wrote on Wed, 03 May 2017 18:06Here are a couple of 8086 User Manuals. It appearsthat they include all the application notes I've attached in the thread above, and even more... http://bitsavers.trailing-edge.com/pdf/intel/8086/9800722-03_The_8086_Family_Users_Manual_Oct79.pdf ftp://bitsavers.informatik.uni-stuttgart.de/pdf/intel/_dataBooks/1981_iAPX_86_88_Users_Manual.pdf

The 8086/8087/8089 combination was apparently called iAPX 86/21. Unfortunately I can't find anyreference designs, schematic, or detailed documentation about iAPX 86/21...

A reference design would be extremely helpful as a cross-check against the 8086 MM SBC.











Thanks for the pointers to the information. What a treasure trove! Intel did good documentationthat's for sure.


mikemac wrote on Wed, 03 May 2017 21:33lynchaj wrote on Wed, 03 May 2017 10:48Hi,




NuBus! The ones Apple used in their 68K Quadras et al are pretty much that.

Yes, I am just tossing out ideas but the Mac II NuBus cards were well designed. it's a shameApple dropped that whole line. The boards I am talking about would only superficially resembleNuBus and would in no way be compatible with it.

DIN 41612 connectors are really good gas-tight reliable connectors. Card edge is cheap butcompared to DIN 41612 is terribly unreliable.

One thing I don't like about the AT ISA format is the connector is on the right hand side. I wouldbe better were it centrally located (like S-100) so as to balance trace lengths going in an out of theboard.


jcoffman wrote on Wed, 03 May 2017 15:39lynchaj wrote on Wed, 03 May 2017 10:50If you wantto go low cost, then we could use pin headers but we'd need a lot of them. At least 100 by mycounts. I think card edge connectors suck. DIN 41612 much better. Euroboard (160x100 mm) istoo small for this technology.

Consider the 160mm x 233.35mm Eurocard format used by VME.









With the 96-pin DIN 41612 on the right connector (landscape format), the ECB bus could besupported in the Siemens 6508 chassis.

Yes, VME is an excellent design and just about the right size too.

The thing is I think we'll need a lot of bus pins. Just the bare minimum, 6 VCC, 6 GND, 20address (+BHE#), 16 data, 12 interrupt related, 12 DMA related, plus at least a couple dozen busarbitration, controller, and CPU control signals. It fully loads a 96 pin connector and that'sassuming I accounted for everything.

Subject: Re: 8086 maximum mode SBCPosted by lynchaj on Fri, 05 May 2017 02:00:34 GMTView Forum Message <> Reply to Message

HiI was able to get this far tonight. Still have some work to do but please take a look at theschematic and PCB layout. Comments & questions welcome.


File Attachments1) 8086-SBC-PCB-ver_1-1.pdf, downloaded 232 times2) 8086-SBC-sch-ver_1-1.pdf, downloaded 409 times


HiThere are a couple of questions I have on the 8086 MM SBC design. Maybe someone can helpme out?

1. The 8289 bus arbiter requires a LOCK# signal from the processor to tell it when to not give upthe external bus. OK, that's fine. However both IOPs also have LOCK# signals. The 8086processor and the IOPs all output LOCK#. Obviously I can't tie all three outputs together so do Ijust connect the processor LOCK# to the 8289? What happens to the IOP's LOCK# signals? The8086 datasheet mentions LOCK# goes tristate when in "hold acknowledge". Does that mean itneeds a pull-up resistor? KiCAD eeschema choked on tying all three outputs together so Iinstalled option jumpers. The 8086, 8087, and both 8089s can be in control of the local bus at anygiven time not just the processor so this is confusing to me.

2. DMA on with the IOP is very different than the DMA on the IBM PC. The IBM PC has DRQ,DACK#, and TC on the ISA bus. ISA bus DMA peripherals generally expect all three and DRQ is











an output, DACK# is an input, and TC is an input. However on the IOP, DRQ is an input (good),there is no DACK# nor is there a TC. The IOP does have an EXT signal which sounds a lot like aTC except it also is an input. WTF? How is DMA supposed to work if the DMA controller and theDMA peripheral are both sitting around waiting for someone to tell them when the transfer iscomplete or acknowledge the DMA request? I presume to implement DACK# like a chip selectsignal and maybe use a latch pin tied to both peripheral TC and IOP EXT to tell the bothsimultaneously to stop transferring? Whichever processor is in control at the time (CPU or IOP)will have to manually control DACK# and EXT/TC because it won't be automatic. I am going toadd an FDC to the design just to see if we can possibly get DMA working. Frankly, it looks like along shot. The interfaces just don't match up.

Thanks for any insights.

PS, my *theories* for #1 and #2 above are:

#1. CPU is master processor and IOPs are both slaves so only the CPU LOCK# is connected tothe bus arbiter. If IOP is in control of the local bus it can't request a LOCK# on its own but mustrequest the CPU to do it. So if an IOP needs exclusive control of the local bus, the CPU hadbetter do it before turning over control to the IOP.

#2. The IOP executes its own little program using its instruction set to manually set up the wholeDMA transfer including DACK# and EXT/TC.


HiYesterday there was some discussion about a bus and/or expansion backplane for the 8086 MMSBC project. I was looking at AP-28, appendix A, and the signals on the Multibus P1 connectorsure look like a good first try at an expansion bus pins 1-86. I think it would require someadditional pins though like the DMA (DRQs, DACKs, TC, EXTs, etc.) and the cascading PICs(CASs). Plus there would be some utility pins like IO_CLK, ROM/RAM#, AEN, RESET#, GATEs,PCLK, CLK, etc. I don't feel its necessary to adopt the Multibus standard out-right especiallysince the form factor is large (12x6 = 72 square inches) per board and it uses a card edgeconnector for P1. I think we can do better with a standard DIN 41612 connector. My initial countfor pins is 111 so a 128 pin connector would give some breathing room but not enough for say full32 bit address and data busses.

Subject: Re: 8086 maximum mode SBCPosted by lynchaj on Sat, 06 May 2017 13:19:04 GMTView Forum Message <> Reply to Message

Hi









The current design has a system bus and should support multiprocessing, however, it is serialmultiprocessing. Only a single bus master CPU can be in control of the system bus at a time andsince all processors share common resources (memory and IO) it is capable of multi-tasking butnot parallel processing. At any given time only a single CPU is executing even if they are sharingthe system bus and doing different things. If the 8086 had any sort of L1 cache it would becapable of some parallel processing.

If we want to go to a true parallel processing multiprocessor system, then each processor willneed its own resident memory and IO so it can effectively detach from the system bus while theprocessor is executing its own task. Essentially the 8086 MM SBC as it is now would be modifiedto add an additional bus controller, address latches, and data buffers.

At this point though I think the best approach is to get the 8086 MM SBC working with its systembus and once all the problems resolved then think about converting the existing system bus into aresident bus and adding a separate system bus.

File Attachments1) 8289 in Resident bus mode.png, downloaded 269 times


HiI just checked on easyEDA.com and 5 prototype PCBs would cost $24 plus $7 shipping or about$31 total. That makes sense to me since these are relatively small boards and 2 layer only.

Is anyone willing to build and test this design? At least the PCB is relatively inexpensive (~$6each plus shipping). Also all the parts are cheap and available even the 8089 is commonlyavailable on ebay.

Subject: Re: 8086 maximum mode SBCPosted by davetypeguy on Sat, 06 May 2017 21:16:48 GMTView Forum Message <> Reply to Message

My time has been pretty tight lately, but I'd be willing to help build and test the design. I am notreally experienced with early development testing, but I am trying to learn. I'd be willing to build and test a board.

If the DIN 41612 96 position connector doesn't provide enough signal pins, the power and groundcould be moved to a separate power plug using the 4-pin molex connector used on old IDE hard drives. It could be run across the back edge opposite the DIN backplane, so you plug in the










card, then plug in the power cable. That might also allow higher current to the board.The 96 pin connectors have the advantage of being plentiful and much cheaper than the 128 pinconnectors. The pricing on the 128 connectors would probably be $20+ per pair, so it would get prohibitive quickly.

Another possibility would be to look at the pci-e x16 connector. It is an edge board connector, butis plentiful, can be found in the < $5 range, and has 164 positions in a narrow connector. If we went that way, we could leave pins available for future expansion to a 32-bit busdesign with support for existing peripheral boards.

Subject: Re: 8086 maximum mode SBCPosted by lynchaj on Sun, 07 May 2017 14:07:46 GMTView Forum Message <> Reply to Message

Hi Dave, Thanks! That's great! Really you don't have to be experienced as this is a hobby andyou can learn by doing. Assuming you know the basics of electronics it is really a matter ofdeducing what should be happening and seeing if it is. Having a logic analyzer is a big help too!

This weekend I've been reading the application notes (again) and trying to make theprocessor/memory/peripherals interface more "multibus-like". The downside is there were a fewsignals missing so I've added them. It had the unfortunate side effect of adding several 74xx logicchips.

Once we get the basic design down and working, I think this board is a candidate for a CPLD orsome GALs to clean up the miscellaneous logic chips on the memory and peripheral boards.



I was thinking that if the 128 pin DIN 41612 pairs are too expensive then there is a cheaper yetmethod. Use two of the 62 pin card slots (aka 8 bit ISA) which would give 124 pins. That shouldbe sufficient connections for at least Multibus I+. If expansion to 32 bits comes to pass, addanother connector.

Multibus P1 connector pins 1-86 + DMA (4 DRQ, 4 DACK#, 4 EXT, TC) + PIC (3 CAS) + IO_CLK+ AEN

~104 pins but there are probably more which will reveal themselves later. Full 32 bit requiresanother 16 data and 12 address










Subject: Re: 8086 maximum mode SBCPosted by davetypeguy on Sun, 07 May 2017 17:53:22 GMTView Forum Message <> Reply to Message

The 62 pin isa connector is the same width as the DIN41612 96 pin connector, so may as well gowith two of those to avoid the edge card gold finger issue. If you went with John Coffman'ssuggestion and used the VME card layout and the Siemens 6508 chassis, you could use a leftand right backplane design to support dual 96 pin DIN41612 connectors nicely. The cageincludes card guides as well, so it would be a ready made chassis.


Hi, here is the latest schematic of 8086 maximum mode SBC


Subject: Re: 8086 maximum mode SBCPosted by davetypeguy on Mon, 08 May 2017 14:55:00 GMTView Forum Message <> Reply to Message

Hi Andrew,

I was looking at the parts we would need to build the prototype board when it is ready, and I havea question about the 8089 IO processor. I can't seem to find information about the versionnumbers, but from the datasheets, it appears the 8089 is only rated for 5MHz. I see 8089-3 and8089A-3 parts available, but can't find anything which says they support 8MHz (or higher). Anyidea what part we would need to run at the 8MHz design speed?

Dave London


Hi Dave

















Not sure. I recommend starting out the initial build and test with 5MHz parts and working our wayup from there. I don't think anyone will even need the 8087 or 8089s to get the bare bonesworking at first. Really just enough to boot the ROM and then get the DUART working. Thenbuild out from there. For sure there are 5MHz and 6MHz 8089s available although I think youhave to use NEC, AMD, or Fujitsu 8089s to get 8MHz. Need to do some investigation on this. BTW the system clock speed is adjustable by changing the master oscillator. It is notionally 24MHz in the schematic but can be scaled down to lower speeds. A 5MHz CPU clock would requirea 15MHz master oscillator. I think it can go down as low as 2MHz (6MHz master oscillator). Atthe higher clock speeds its not unusual to find some logic chips need to be 74F or 74S type ratherthan 74LS or 74HCT.

Subject: Re: 8086 maximum mode SBCPosted by wsm on Mon, 08 May 2017 16:52:02 GMTView Forum Message <> Reply to Message

Hi Andrew,I did a QUICK calculation on your latest schematic and it appears that total max power is in therange of 3.8 Amps. That's based on 74LS* and 74F* or 74S* could add even more. Before youfabricate boards I think you'll need to look at this aspect and change the LM7805 regulator.

Subject: Re: 8086 maximum mode SBCPosted by davetypeguy on Mon, 08 May 2017 17:09:27 GMTView Forum Message <> Reply to Message

An external 5V power supply connectionwould probably be worth considering and just removingvoltage regulation on the board entirely. In fact, the ATX power supply connection circuit fromXagdin might be a good add on to the schematic. Long term, an ATX supply is a common andlow cost power source for high current 5V (and possibly 12V) supply.

Subject: Re: 8086 maximum mode SBCPosted by plasmo on Mon, 08 May 2017 18:03:24 GMTView Forum Message <> Reply to Message

While I have not had the opportunity to design with Intel processors, I do collect them over theyears. The discussion about 8086 reminds me of the MCS-86 University Kit I acquired manyyears ago. Still in the box, never did put it together. Since IBM PC was introduced in 1981 andthis kit was made in 1978, now I wonder what monitor software was resided in the PROM. Thepart number for the PROM is 2616 which is factory programmed PROM. The content may still bevalid 40 years later.

You can't read the part numbers at this resolution, but they are (from top to bottom):C8086-4D82842x P8282












2x P8286SAB8251A-DSAB8259AD4x C2142-32x B2616

File Attachments1) DSC_24670508.jpg, downloaded 1214 times2) DSC_24690508.jpg, downloaded 1222 times


wsm wrote on Mon, 08 May 2017 12:52Hi Andrew,I did a QUICK calculation on your latest schematic and it appears that total max power is in therange of 3.8 Amps. That's based on 74LS* and 74F* or 74S* could add even more. Before youfabricate boards I think you'll need to look at this aspect and change the LM7805 regulator.

Hi BillGood point. The 9V wall wart connector and LM7805 are artifacts left over from the original 8086maximum mode only in the 8086 datasheet. Since then the design has evolved considerably andrequired amperage has gone way up. I will convert to the AT/ATX PS drive connector like theJackalope uses. Possibly the ATX circuit if it fits on the current board.

Thanks for the input. Great catch! Andrew Lynch


plasmo wrote on Mon, 08 May 2017 14:03While I have not had the opportunity to design with Intelprocessors, I do collect them over the years. The discussion about 8086 reminds me of theMCS-86 University Kit I acquired many years ago. Still in the box, never did put it together. SinceIBM PC was introduced in 1981 and this kit was made in 1978, now I wonder what monitorsoftware was resided in the PROM. The part number for the PROM is 2616 which is factoryprogrammed PROM. The content may still be valid 40 years later.

You can't read the part numbers at this resolution, but they are (from top to bottom):C8086-4D82842x P8282











2x P8286SAB8251A-DSAB8259AD4x C2142-32x B2616

Nice kit. It may be 40 years old but I'll bet it still works just fine.


wsm wrote on Mon, 08 May 2017 12:52Hi Andrew,I did a QUICK calculation on your latest schematic and it appears that total max power is in therange of 3.8 Amps. That's based on 74LS* and 74F* or 74S* could add even more. Before youfabricate boards I think you'll need to look at this aspect and change the LM7805 regulator.

Hi Bill

I think generous use of 74HCTxxx and CMOS versions of the ICs would also reduce powerconsumption quite a bit. I am going to add a design note on the top level schematic to substituteCMOS versions whenever possible and minimize 74LS and HCMOS chips. I think at the initiallow speeds of build and test they should be fine with timing. They may actually be easier tosource than the old school HCMOS and 74LSxxx parts.

There are CMOS versions of 80C86, 82C84, 82C88, 82C89, 82C59, 82C54, TL16C552,DS12C885, WDC37C65, the flash and SRAM chips, and most if not all of the miscellaneous logicchips. Its not quite like the original design but at 5 to 8 MHz it should be OK.

I use 74LSxxx chips in KiCAD because that's what is best supported by the libraries.

https://electronicsclub.info/74series.htm#hchct


Subject: Re: 8086 maximum mode SBCPosted by wsm on Tue, 09 May 2017 13:33:16 GMTView Forum Message <> Reply to Message

Andrew,









Having been burnt before (no pun) on component creep / power, I was just curious what the worstcase might be.

From my old data sheets, the worst HMOS components appear to be: 8087 (475ma), 8086(360ma), 2 * 8089 (350ma each), 8288 (230ma), 8289 (165ma), 8284 (162ma) and 8254(140ma). Those kind of numbers make me remember why my S100 power supply looks like anarc welder.

I used some NOS 512Kx8 SRAMs that I had for a recent project and discovered that newer onescould use 1/5 the power (30ma vs. 150ma each). Something to keep in mind when creating aBOM.

74AHCTxxx should also work if you need to reduce propagation delays.

I'm sure you're well aware that given these kinds of possible power levels the PCB power traceswill need to be sized accordingly.


Good point. The design has serious power use creep and needs a rethink.

I think there are a couple of ways to tackle this issue. Either use the ATX power supply connectorand break out multiple VCC feed lines, one each for processor, peripheral, and memory partitions,OR use a 4 layer PCB with internal VCC and GND layers. I am rather leaning towards the 4 layerPCB at the moment. Maybe a combination of both.


Given the 3+ times price hit for 4 layers, I would think in terms of a significant +5V main rail or two(perhaps .125") with feeds coming off of it (perhaps .060"+) and ground pours top & bottom. Depending on the layout it might require actual ground rails. Likewise, perhaps a bit of distributedbulk capacitance. Hmmm ... sounds similar to some of the old S100 boards.


Yes, its an issue on all of these home brew projects using legacy, 40 year old parts. Definitelywas (and is) an issue on S-100 boards.












Were I laying this PCB out by hand setting up variable width traces for supply rails would be easy. With KiCAD, not so much. It would require a main supply rail trace class with feeders connectedby wire jumpers to sub-classes. Ugh. I think the people building it would rather just have the 4layers than go through all the contortions just to keep it 2 layer. With 4 layer PCB then VCC andGND are common across the whole board and supply trace length is really not an issue. It reallymakes a big difference with power hogs like DRAM which fortunately this design does not use.

Each chip has its own filter bypass capacitor but your idea of sprinkling a few bulk capacitors isgood too. I hadn't realized how much this design had grown since the original idea.

Anyway, let's toss the idea out there and see what the response is from the people building it. Ifthere is major heartburn either way then it will be clear what to do.

Everyone, if you are considering building the 8086 MM SBC, what say you regarding powerdistribution? Don't be shy, please speak up.

Thanks Bill, great suggestions as usual! Andrew Lynch


PS, I know the design guides for 74HCTxxx suggest grounding all the inputs for unusedcomponents which is a great idea for the final or near final board. However for the initial build andtest units it is probably better to leave those unconnected in case they are needed for fixes. Letthe person building it ground those inputs with wires if its a problem rather than disabling thespare components.

Subject: Re: 8086 maximum mode SBCPosted by davetypeguy on Tue, 09 May 2017 15:54:23 GMTView Forum Message <> Reply to Message

Since this is a prototype anyway, could we bring the power connections to the middle of the boardand fan out the supply lines from there? Longer term, each subsection will be on its own smallerboard anyway, so design it that way from a power standpoint in the prototype.


Quote:Were I laying this PCB out by hand setting up variable width traces for supply rails wouldbe easy. With KiCAD, not so much. It would require a main supply rail trace class with feedersconnected by wire jumpers to sub-classes. Ugh.OUCH! I hadn't realized this was such an issue with KiCAD since I use Eagle. Although I seldom












use the full autorouter, with Eagle its quite easy to first lay out some traces by hand either fully orpartially, like the power rails, and then let the autorouter complete all the other connections. Ihaven't tried using Eagle's autorouter with mixed trace widths but I imagine it would also requiresignificant effort.


davetypeguy wrote on Tue, 09 May 2017 11:54Since this is a prototype anyway, could we bringthe power connections to the middle of the board and fan out the supply lines from there? Longerterm, each subsection will be on its own smaller board anyway, so design it that way from a powerstandpoint in the prototype.

Yes, we can do that with the ATX connector since it has 4 separate 5V supply lines. Eachpartition (processor, memory, peripherals) and miscellaneous get their own supply line straightfrom the ATX connector. It precludes the use of the molex drive connector though (single point of5V).

Since I am going to add the ATX connector anyway, let me try setting this up and see how itworks. Probably boost the width of the supply traces too. Might be feasible to keep it 2 layer thatway.

The plan is for ground fill zones on top and bottom regardless so that's covered. Its the VCCsupply rails that need attention.

Subject: Re: 8086 maximum mode SBCPosted by rhkoolstar on Tue, 09 May 2017 17:06:16 GMTView Forum Message <> Reply to Message

Using different track sizes is not that difficult.

What you do is create a footprint with two (smd or through-hole) pads with numbers 1 and 2 whichpartially overlap.then connect one net to pads # 1 and the other net to pads # 2This will route correctly, but off course the design rules check will complain about clearanceerrors.

Rienk










Hi,OK last night I made some changes to the 8086 MM SBC to help with the power situation. First, Iadded the ATX power supply circuit. Then I split up the power supply rails into 4 groups(processor, memory, peripherals, & miscellaneous). One for each of the ATX power supply 5Vrails.

The major chips in processor partition have the big current draw so they got their own supply linedirect from the PS. According to the worst case load from Bill, I calculated just below 2 amps for8086, 8087, 2 8089s, 8284, 8288, 8289, 2 8259s, and an 8254 which requires a trace widthslightly less than .8 mm to carry the load using 1 oz. copper on a 2 layer board with a tiny bit ofmargin. That's convenient since a 0.8 mm trace width is the largest that will still trace route tointernal pads on PLCC chips.

Did the same for memory and peripheral partitions. All the other remaining 74LSxxx chips fell intothe miscellaneous category and got their own supply rail. Did a bit of experimental trace routingand the board still routes just fine. The only issue that came up is to the mélange of partlibraries in KiCAD it is important to ensure to not mix power input names because it willoccasionally merge networks depending on the name of the power input to a chip. For instance, ifyou have a 5V chip with a power input called "VDD" and connect 5V to it and a separate networkfor 3.3V called VDD, it will merge the 5V and 3.3V supply rails. Ugh. It is can be a very difficultbug to find but I knew it before hand and it wasn't an issue.

Also added a bunch of distributed bulk capacitors to help keep the supply rails well behaved. Each rail got 2 or 3 capacitors sprinkled around the board. Tonight I am going to add to the toplevel schematic a note for people building the board to use CMOS chips whenever and whereverpossible to keep power usage levels down. I think this is the most important part since it willprevent large current draws in the first place.

Unfortunately, due to the 4 separate supply rails, using the molex drive power supply connector isnot an option on the board. However if people really want to use one they can not install the ATXconnector and just manually hook up a molex drive power supply connector using wires. Then itmerge all the supply rails into one supplied by the PS. Since it is using wires rather than traces itwon't be limited by current draw (up to a point).

The board is still 2 layer PCB and it looks like the power distribution issue has been addressed. Are there any other design issues we need to deal with? I don't think this board will take long totrace route optimize. It seems to quickly settle at about 350 vias and trace routes cleanly.










Well one thing I can think of is now that we have an ATX power supply with +12V and -12V wecan replace the MAX238s with GD75232s and save a bit of room and have slightly more completeserial ports (include RI#).


With latest updates. Please post comments, questions, corrections. Thanks, Andrew Lynch

PS, especially the new GD75232s as those are new components.



Hi

While people are looking at the schematic and PCB layout, here is an idea for making aninexpensive passive backplane to connect Multibus-like boards. Taking cue from PC/104, Isuggest a standard PCB size for all the boards, say 6"x8" (48 square inches) using a pair of 64pin stackthrough connectors like these:

http://www.mouser.com/ProductDetail/Harwin/M20-6103245/?qs=sGAEpiMZZMud62t8luTOJtjReFLWWuxIslCjqrHIrtM%3d

Put the connectors in the middle of the short sides of the rectangular PCB, with input devices onthe bottom of the board and output connectors at the top like this:

+------------+| output ||| |||| ||| input |+------------+

The connectors are Harwin which is a top quality brand available from Mouser. I suspect withsome shopping around (ebay, alibaba, etc.) we could bring these prices down considerably.











The benefits of this approach is no passive backplane is needed and it uses off the shelf parts forthe Multibus-like expansion.

I recommend just using Multibus pins 1-86 as they are in the P1 specification and either leave therest as reserved or fill in with pins we know we are going to need like CASx, extended address &data, etc.

Ideas, comments, questions? Thanks, Andrew Lynch

PS, darn proportional pitch font, look at the diagram in edit mode with a fixed pitch font and itmakes more sense. How do you use fixed pitch font on RBC forums?

Subject: Re: 8086 maximum mode SBCPosted by mikemac on Thu, 11 May 2017 16:30:32 GMTView Forum Message <> Reply to Message

I personally like the idea of stackable connectors. As long as you can add the daughter cards toeither the top or the bottom of the stack, that is! It's a royal pain to debug a card if it can't be put atthe top of the stack. Sometimes you'll want the processor on top and other times you'll want theI/O board on top.

Making the stackable does limit the height of the components that you can have on the boards. Soprobably no heat sinks or 7805s. Probably shouldn't be a problem for what you intend though.

Doesn't the 'code' tag use a fixed width font?

Subject: Re: 8086 maximum mode SBCPosted by davetypeguy on Thu, 11 May 2017 19:00:03 GMTView Forum Message <> Reply to Message

I'm good either way, but the idea of using the Siemens 505-65xx chassis and the 96pin DIN41612connector(s) is worth considering. The 505-6508 prices are still a bit high from the buying rush forthe ECB systems, but the 505-6516 can be had for under $40 right now and has the same specs,except it is slotted for 16 cards rather than 8. The 8-port backplane designed for the 6508 willalso fit the 6516, and if you can get away with just the one 96pin connector on the left, you havethe other side of the chassis for an expansion backplane if the system were to warrant expansionto support 32 bit CPUs. Careful board size choice would let you use the card guides on bothsides of the chassis, and the 16-slot size allows a power supply to be mounted inside the chassiswith plenty of room to spare.

Subject: Re: 8086 maximum mode SBCPosted by lynchaj on Thu, 11 May 2017 19:06:38 GMT










View Forum Message <> Reply to Message

HiIs that the same board outline as the 6x0x-ATX?


mikemac wrote on Thu, 11 May 2017 12:30Doesn't the 'code' tag use a fixed width font?

Thanks, much better now.


Looking at that board, if it is not it would certainly be close. The URL for the 12-slot 6508backplane board is https://retrobrewcomputers.org/doku.php?id=boards:ecb:backplane-505-6508:start. It could be used as a starting point for the backplane design, although we'dhave to ensure that users didn't try to plug ECB cards into the Multibus backplane.


The dimension drawings of the various chassis from the Siemens 505-65xx line are available onpages 3-5 through 3-7 of the Siemens SIMATIC TI545/TI555 System Manual available from here:

https://cache.industry.siemens.com/dl/files/465/17518465/att _106091/v1/545-8101-2.pdf

Looks like the ECB boards fit nicely height wise, so a board somewhere around 160mm x 234mmshould be pretty close to perfect. The 6X0X-ATX board is 160 mm x 233.35 mm, so I would say itlikely was design for that footprint.

A two layer board that size in quantity 5 from easyeda would be $4.40 each plus shipping, soquite reasonable a size to get made. I have one of the chassis at home, so I could do somemeasuring on it if you're interested in exact measurements.














Subject: Re: 8086 maximum mode SBCPosted by jcoffman on Thu, 11 May 2017 22:24:26 GMTView Forum Message <> Reply to Message

Note: The 505-6516 would hold 20 RetroBrew ECB cards, not 16. The 505-6508 holds 8Siemens cards, or 12 RetroBrew ECB cards.

The 505-6508 backplane is out-of-stock; I would make the Gerber files available to anyoneinterested in producing some.

--John


Hi

Yes, I think that's the main concern I have with reusing chassis & backplane from an ECB project. Multibus is completely different and incompatible pin arrangement which would mean certaindeath for any board accidentally plugged into an ECB system and vice versa. The VME sizedboard is about right though at approximately 6"X9"

I think it would be safer to just make a new PC/104 like board stacking standard so there would beno chance of destroying boards by accident. What I am thinking is a 6"X8" board with these onthe ends:

http://www.ebay.com/itm/2pcs-100-2-54mm-Female-Header-80pin-2x40-Long-pin-stack-through-connector-/152529119129

They have enough pins for Multibus plus expansion, are plentiful, cheap, and available on ebay. Also they can be substituted with a pair of 40 pin stackthrough connectors making them evenmore available.

Subject: Re: 8086 maximum mode SBCPosted by davetypeguy on Fri, 12 May 2017 03:36:36 GMTView Forum Message <> Reply to Message

You can solve the safety issue by offsetting the DIN connector so it won't allow an ECB board toplug in while fitting into the slot. It was just an idea, though. Stacking headers should work fine.

Subject: Re: 8086 maximum mode SBC












Posted by lynchaj on Fri, 12 May 2017 10:12:35 GMTView Forum Message <> Reply to Message

HiWell, nothing is cast in concrete yet. I do like the idea of keying the bus connectors though. Irecall there were some problems with the ECB backplanes of some people installing the DIN41612 connectors backwards and destroying boards. It is so easy to do if you've got multipleprojects and aren't checking closely as you go.


Assuming the 8086 MM SBC gets past initial build and test, I think we need to consider anoperating system. I'd like to go to some sophisticated multiprocessor system like iRMX eventuallybut that's probably too ambitious right away. So I am thinking more of a "crawl, walk, run"approach makes more sense. Although iRMX is really cool I suspect it is closed source onlywhich would make its use in a home brew project almost impossible.

So for "crawl", I suggest a simple monitor and maybe a ROM BASIC type program and/orassembler/disassembler. Maybe a stretch goal of Flash ROM updater to reduce chip removals forreprogramming. Any suggestions? I suppose there are several to choose from or build one fromscratch.

For "walk", I was thinking FreeDOS or CP/M-86. Both are full blown operating systems withsource available. Either of these would help build the scaffolding for more advanced operatingsystems by facilitating more advanced programming and/or driver development.

Finally for "run", a Un*x like system such as Coherent, Minix, or something similar. uCLinuxwould be neat but I don't think it runs on 8086. Possibly QNX or Xenix but I don't think those areopen source which really limits the ability of porting and/or driver development.

Ideas, comments? Thanks, Andrew Lynch


Hi

I got an estimate from easyEDA.com to build 5 initial PCBs so now I'd like to know if anyone isinterested in build and test of these prototypes.

The 5 PCBs with shipping come out to $51 including shipping. So that would be $10 per personper board plus shipping which should be fairly low ($3 or so) in the US. Not sure what it would beinternationally but it tends to be more expensive. Obviously we can get more boards if warranted












but I think we'll be lucky to get the 5. I am in so that means we only need 4 others to make thiswork.

So who would be interested in building the 8086 MM SBC prototype boards? I think this would bea fun and useful project. Also I think Multibus provides a great platform for future expansion as itis well defined standard with excellent documentation. Better yet, there is no fragmentation ofMultibus that I am aware of which really helps build consistent projects.

Please contact me by PM or just post here if you'd like to participate. Thanks, Andrew Lynch

File Attachments1) 8086-SBC.png, downloaded 967 times


Hi, just a quick note of caution with KiCAD. I've had KiCAD installed on my PC for about 10 yearsand have a lot of legacy libraries, footprints, etc. So part of this project is to modernize my KiCADinstallation using the latest distribution, Github libraries & footprints, etc. Its been quite a trek,however, when reusing old libraries & footprints be *careful* about matching them up. Some partscan be replaced but others can't. For instance I reused the ATX connector from Sergey's ISAbackplane on several projects. However if you use the actual Molex Mini-Jr ATX power supplyconnector (new in KiCAD) it has a different pin numbering sequence resulting in a very differentand incompatible ATX power supply connector. Once I noticed this I switched back to the oldcustom part. Similar for the PLCC sockets which have the same pin out and but the pads aredifferent resulting in very different trace routing. Some things are nearly drop in replacements likethe CR2032 battery holders but others aren't

Another idea that's crossed my mind for RBC would be a library of proven components for peopleto reuse in designing their home brew computers. Like sub-schematics for ATX power supply,and the many custom part libraries and footprints we (collectively) have developed over the years. ECB board outlines, S-100 board outlines, WDC37C65 libraries, etc. It would really simplifythings for people building their own home brew projects.


Hi, I think a worthy goal for the 8086 maximum mode SBC is to get it running, build a monitor, andget CP/M-86 running. There are CP/M-86 sources here:

http://www.cpm.z80.de/source.html










Maybe FreeDOS but the project will not have IBM PC compatibility so I don't want to give peoplethe wrong impression


Also excellent reference material, courtesy of Bill Beech NJ7P Intel and Multibus historianextraordinaire, a Multibus design guide by Johnson

http://www.nj7p.org/Manuals/PDFs/Intel/Johnson_The_Multibus_ Design_Guidebook_1984.pdf

Its a great supplement to the datasheets and application notes explaining things in easy tounderstand language


John Monahan has great instructions on S100computers.com for how to bring up an 8086 monitorand CP/M-86 on his website:

http://www.s100computers.com/Software%20Folder/8086%20Monito r/8086%20Monitor.htm

http://www.s100computers.com/Software%20Folder/CPM86/CPM-86% 20Software.htm

Both should be very helpful in getting the 8086 MM SBC working with some software.


HiThere are still a couple of the prototype PCB available if anyone would like to build and testplease send me a PM or email. Thanks, Andrew Lynch


Hi, good news, I ordered the 8086 Maximum Mode SBC PCBs this morning. They should be here















in a couple of weeks or so. Thanks, Andrew Lynch


Subject: Re: 8086 maximum mode SBCPosted by lynchaj on Sun, 04 Jun 2017 18:50:16 GMTView Forum Message <> Reply to Message

HiThe 8086 Maximum Mode SBC PCBs arrived on Friday so if you are interested in build and test itshould be starting soon. Please send me a PM if you'd like to also build and test. Thanks,Andrew Lynch

Subject: Re: 8086 maximum mode SBCPosted by lynchaj on Sat, 10 Jun 2017 14:45:19 GMTView Forum Message <> Reply to Message

HiStill have an 8086 Max Mode PCB available if anyone wants one. They are $10 plus shipping. Please send me a PM. Thanks, Andrew Lynch











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