substrate noise analysis and simulation with substratestorm

© Copyright 2001 Simplex Solutions, Inc. 1

Substrate Noise Analysis andSimulation with SubstrateStorm

Philippe Duchene

[email protected]


Complete SoC Verification Suite

ReliabilityElectronStorm™

Power IntegrityVoltageStorm™ SoC

Signal IntegritySubstrateStorm™

SI Report™

Timing IntegrityFire & Ice® QXClockStorm™


Noise GenerationNumber devices - UPFrequency - UPRise / fall time - DOWN

The Substrate Crisis

Digital Noise Sensitive Section

Noise Sensitivity Signal resolution - UP Frequency - UP Power - DOWN

At 0.13 micronNoise generation increases by 50%Noise sensitivity increases by 100%


ADI Disaster Example:Trial & Error

• Video converterwith 27 MHz PLLfailed

• VCO locked tosubstrate clock

• Various solutiontechniquesattempted

• What worked?

www.imse.cnm.es/esd-msd/WORKSHOPS/ESSDERC2000


EmbeddedMemory

CPU core

I/O

I/O

A/D

Std cellblock

Std cell Logic

D/A

PLL

What designs needSubstrateStorm?

• Mixed-Signal SoCs– Digital Noise Generation + Noise

Transmission + Analog Sensitivity– 100 MHz or above

• RF designs– Wireless, Bluetooth, 3G, SiGe– GHz range

• Sensitive analog designs– A/D’s, D/A’s

• High-speed I/O’s– 1 GHz or above

• High-speed PLL’s– 500 MHz or above


• • •

Typical Substrate RelatedQuestions

• I have 5 isolation structures– which is optimal for this design?

• How wide should my guard ring be?• How will a technology port effect my design

performance?• What immunity do I gain by backside plating?• What benefit do I get by splitting my power supply?


SubstrateStorm Design Flow

IC Design

Netlist

LVS/LPELVS/LPE

SimulationSimulation

Layout

SubstrateStormSubstrate

Abstract View EditEdit

SubstrateSubstrateExtractionExtraction

Visual AnalysisVisual AnalysisCDS DFII or Standalone GUI

TechnologyDescription


3-D Model3-D Model

Technologydescription

Technologydescription

IN

Model Extraction Strategy

OUT

LayoutLayout

VisualanalysisVisual

analysisElectricalsimulationElectricalsimulation


• Substrate Abstract View Definition- Process regions (wells, buried layers, deep trenches, …)- Ports connecting the ideal circuit to the substrate- Equivalent ideal circuit model for interactive visual analysis

• RC Model Extraction

Noise Source Noise Victim

Bonding Wire

NwellN+ contact

P+ contacts

Modeling the Substrate


x

y

z

poly

p+

nwell

}LAYOUT

device

nwell

p-substrate

p+

PR

OC

ES

S(d

opin

g pr

ofile

s)

contact

interconnect

3D Modeling


p-substrate

nwell

n+p+ p+

poly

resistivesubstrate

resistivewell

well-substratejunction

capacitance

Modeling

Distributed RC Model


Self-Adjusting Grid

• Unlimited chip size

• Highest accuracy where

needed

• Non-manhattan shapes


SubstrateExtraction

Fabrication ProcessFabrication ProcessSubstrateStormSubstrateStorm

SubstrateStorm™ TCT

MeasurementTCAD

TechnologyTechnologyDescriptionDescription

TechnologyTechnologyCharacterizationCharacterization

DopingProfiles

Patents granted


Designer

SubstrateExtraction

Simplex Foundry Partners

Measurementor TCAD

Simulations

TechnologyDescription

TechnologyCharacterization

Tool

DopingProfiles

• Simplex teams up with foundrypartners to provide acuratesubstrate parameters


• Design Example– Effect of pad ring switching

noise on PLLs

• Exploration Questions– Noise frequency dependence

– Splitting ground lines

– Backside grounding

– Number of VSS pins (packageinductance)

– Guard rings

– etc.

Full-chip Analysis


PLL Affected By Output Ring

• Design– 1M gates, 0.18µ– 100MHz clock (PLL)

• PLL Noise Concerns:– Noise propagated from the output

buffer ring– Explore various solutions to

improve noise immunity


Buffer Creates Substrate Noise

abstraction

GDS

SubstrateAbstract

View

NoiseColorMap

analysis

SPICE substratesubnetlist

extractionnot shown

on customerrequest

simulation


Pad Ring Creates Substrate Noise

• SubstrateStorm– surface distribution of the

noise

• Conditions– 400ps rise/fall time– 30pF off-chip load– 2nH bond inductance– Plotted @ 350MHz


Noise Is Collected By PLL

PLL is well protected by itsguard rings

BUT

Guard rings also carry noise!!


Noise Increases with Frequency

350 MHz

Noise isolation typically degrades at higher frequencies

Isolation is 6dB @ DC, but -0.42dB @ 350MHz

DC


Splitting Power Reduces Noise

Effective way of improving isolation (-0.42dB to -9.5dB)Requires additional pins but no additional space

VSS1 VSS2VSS1


Backside Grounding Has LittleEffect

With backside connection through a 5nH bond wire:

FIsolation at PLL ring improved by only 0.03dB

FNot worth the cost !


Exploration Questions

• What if you:– added a N-well guard ring around your PLL?– used a triple-well process?– used a low-resistivity substrate?– introduced a grounded backside connection?– took the seal ring into account?– cut the VSS ring to avoid noise transportation– … Etc …

Each question only takes minutes to answerusing SubstrateStorm


Goal: locate the most sensitive parts of the analog cell and improveGoal: locate the most sensitive parts of the analog cell and improvethe noise immunity (lightly doped substrate)the noise immunity (lightly doped substrate)

Noise source (Noise source (substratesubstratepropagation propagation onlyonly))

Sensitive Sensitive analog cellanalog cell((opop--ampamp))

Detailed Cell-level Analysis


Non-Non-inverterinverter amplifier, gain = 1000 amplifier, gain = 1000

Noise sourceNoise source

Simulation Set-Up


Noise sourceNoise source

tr = 350 ps

220mV

Noise

OutputOutputNoiseNoise

impact

impact

Substrate Impact

Through the substrate


Differential Differential input pair?input pair?Input Input currentcurrent mirrormirror??

Active Active loadload??Compensation circuit?Compensation circuit?

Output driver?Output driver?

CombinationCombination of of themthem??

Output Output current mirrorcurrent mirror??

What Is the Most Sensitive Part?


Differential Input Pair

VSSA

Substrate

Substrate Substrate model extractionmodel extraction

SPICE simulationSPICE simulation

Circuit Circuit netlistnetlist back-annotation back-annotation

Output noise < 1% Total noiseOutput noise < 1% Total noise

No impact from this stage

VDDA


Output DriverOutput Driver

Active Active LoadLoad

Output Output Current MirrorCurrent Mirror

Input Input Current MirrorCurrent Mirror

Differential Differential Input PairInput Pair

Active Devices < 1% Total Noise


Feedback Circuitry

Substrate Substrate model extractionmodel extraction

SPICE simulationSPICE simulation

Circuit Circuit netlistnetlist back-annotation back-annotation

Output noise > 95% Total noiseOutput noise > 95% Total noise

Major noise collector isfeedback capacitor

VDDA VSSA

Substrate


1st Solution:1st Solution:extending the extending the n-n-well under thewell under thecompensation compensation devicesdevices

ResultResult::1: noise 1: noise immunityimmunity improvedimproved: 50%: 50%

2nd Solution:2nd Solution:p+ ring p+ ring around the cellaround the cell

ResultResult::2: noise immunity improved: 80%2: noise immunity improved: 80%

Design trade-off: What’s your choice?Design trade-off: What’s your choice?

Immunity Increase


Substrate Technology You Need

• Unique Solution– Technology Characterization + Accurate Modeling– Visual Analysis

• Flow Integration– Standalone: GDS to Spice– Diva, Calibre, Assura, Dracula– Seamless Integration in Cadence Virtuoso and Analog Artist

• 2 Use Models– Detailed Cell Analysis and Simulation– Chip-level Floorplan Analysis

• Foundry Program

– TSMC, ST, UMC

• Currently Used In Production Designs


New in SubstrateStorm V4.0

• Performance & Capacity– Upgraded extraction & analysis kernel

• speed 3-5x– RC Netlist reduction

• capacity 5x– Macro-modeling

• Ease-of-Use– Automation of common tasks– Multiple object edition

• Flow Integration– Cadence 4.4.5, 4.4.6– Calibre, Assura, Dracula


STV0399 - first single chip CMOS integration“Until now, two or more ICs have been required toimplement these functions, at a cost some 25 - 50%higher.”

• Zero IF tuner• multistandard demodulator (QPSK and 8-PSK)• Forward Error Correction (FEC)• 950-2200 MHz RF input

“We have already applied SubstrateStorm successfully to severaldesigns, one of which is a very advanced single-chip satellite RFreceiver for cable television. We have been impressed that the firstsilicon confirmed the predictions of SubstrateStorm in that the digitalblock interference with the RF blocks was sufficiently low as to makethe chip functional.” Philippe MagarshackPhilippe Magarshack

Central R&D Group Vice President for Design Automation and LibrariesCentral R&D Group Vice President for Design Automation and Libraries


SoC + Analog = Substrate Noise

Substrate noise killsanalog performance

. . .Don’t wait for it to kill

your design !

substrate noise analysis and simulation with substratestorm

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