summary notes on electrical engineering

7/28/2019 Summary Notes on Electrical Engineering

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I. CIRCUIT BASICS

• Electrical quantities

Current:dt

dq I = [Units: C/s = Amps (A)] Voltage:

dq

dwV = [Units: J/C = Volts (V)]

Power: VI P dt dq

dqdw

dt dw ===

[Units: J/s = Watts (W)]

avg power: ∫=T

T dt t V t I P

0

1 )()(

P = IV > 0: power deliveredP = IV < 0: power extracted

• Primitive circuit elements

Voltage Source Current Source

Resistor – follows Ohm’s Law: V IR= (note polarity)

R = resistance [Units: V/A = Ohms (Ω)]

G = 1/R = conductance [Units: Siemens (S)]

Resistor power dissipation: R

R I IV P === V 22

∑=

=n

k

k eq R R

1

• Circuit definitions Node – point where 2 or more circuit elements are connected Series elements – same current flows through all elements

Parallel elements – same voltage across all elements

II. CIRCUIT ANALYSIS BASICS

• KCL (Kirchhoff’s Current Law) Sum of all currents entering a node = 0

Sum of all currents leaving a node = 0

Σ(currents in) = Σ(currents out)

• KVL (Kirchhoff’s Voltage Law) Sum of voltage drops around a loop = 0

Sum of voltage rises around a loop = 0

Σ(voltage drops) = Σ(voltage rises)

• Series resistors: • Parallel resistors: ∑=

=n

k k eqR R

1

11

2 R+1 R Req = 21

2121 ||

R R

R R R R Req

+==

321

1111

R R R Req

++=



• Voltage divider • Current divider

S V R R

RV

2122 += S V R R R

RV

32133 ++= S I R R

R

I 21

12 += S I

R R R

R I

321

33 111

1

++=

• Source combinations (series voltage sources and parallel current sources)

III. CIRCUIT ANALYSIS METHODS

• Nodal Analysis – finds unknown node voltages in a circuit; once all node voltages are known,currents can be found through IV relationships of circuit elements (e.g., Ohm’s Law)

1. Choose a reference node (“ground”)

2. Define unknown voltages (those not fixed by voltage sources)3. Write KCL at each unknown node, expressing current in terms of node voltages

- use IV relationships of the circuit elements (e.g., I=V/R for resistors)

4. Solve the set of independent equations (N eqn’s for N unknown node voltages)

• Supernode – for a floating voltage source (where both terminals are unknown voltages), define

a supernode around the source, write KCL at supernode, and use the voltage source equation

x y F

y x

V V V

R

V

R

V

I I

−=+=+ 2121

• Superposition – In any linear circuit containing multiple independent sources, any I or V in the

circuit can be calculated as the sum of the individual contributions of each source acting alone

o Linear circuit – circuit with only independent sources and linear elements (linear RLC,linear dependent sources). Linear elements have linear IV characteristics.

1. Leave one source on and turn off all other sourcesÆ replace voltage source with short circuit (V=0)Æ replace current source with open circuit (I=0)

2. Find the contribution from the “on” source

3. Repeat for each independent source.4. Sum the individual contributions from each source to obtain the final result

Note: Superposition doesn’t work for power, since power is nonlinear (P=I2R=V

2/R)



• Thevenin/Norton Equivalent Circuit Models – Any linear 2-terminal network of independentsources and linear resistors can be replaced by an equivalent circuit consisting of 1 independent

voltage source in series with 1 resistor (Thevenin) or 1 independent current source in parallelwith 1 resistor (Norton). The circuit models have the same IV characteristics.

Three variables: Vth=Voc, R th=R N, I N=Isc. Thevenin/Norton relationship: Vth=I NR th Æ only 2 of the 3 variables are required

Vth = Voc: open-circuit voltage – Leave the port open (IL=0) and solve for Voc.

I N = Isc: short-circuit current – Short the port (VL=0) and solve for I N. R thc: Thevenin/Norton resistance – Turn off all independent sources (leave the dependent

sources alone). If there are no dependent sources, simplify the resistive network using

series and parallel reductions to find the equivalent resistance. If dependent sources are

present, attach Itest or Vtest and use KCL/KVL to find R th=Vtest/Itest.

test

test th

I

V R =note the direction of I test

and the polarity of V test

• Source Transformations – conversion between Thevenin and Norton equivalent circuits

• Maximum Power Transfer TheoremÆ power transferred to load resistor R L

is maximized when R L=R

th

• Load-line Analysis – graphical method solving circuits with 1 nonlinear circuit element Æ graph the IV curves for the nonlinear circuit element and the Thevenin/Norton equivalent of

the rest of the circuit on the same axes; the operating point is where the two curves intersect



IV. CAPACITORS AND INDUCTORS

• Capacitor – passive circuit element that stores electric energy

Capacitance: C = Q/V [Units: Coulombs/Volt = Farads (F)]

IV relationship: dt

dv

c

c

C i =

Energy stored: Ec = ½CV2

voltage across capacitor vc cannot change instantaneously: vc(0-)=vc(0

+)

note polarity!

in steady-state, capacitor is an open circuit (dvc/dt=0Æic=0)

low freq: open circuit; high freq: short-circuit

• Parallel capacitors: • Series capacitors:∑=

=n

k k eq C C

1∑=

=n

k k eq C C 1

11

• Capacitive voltage divider

S V C C

C V

21

12

+=

S V

C C C

C V

321

33 111

1

++=

• Inductor – passive circuit element that stores magnetic energy

Inductance: L = Φ/I [Units: Webers/Amps = Henrys (H)]

IV relationship: dt

di L

L Lv =

Energy stored: EL = ½LI2

current through inductor iL cannot change instantaneously: iL(0-

)=iL(0+

)

note polarity!

in steady-state, inductor is a short circuit (diL/dt=0ÆvL=0) low freq: short circuit; high freq: open-circuit

• Series inductors: • Parallel inductors:∑=

=n

k k eq L L

1∑=

=n

k k eq L L1

11

Capacitor and Inductor Summary :

Capacitor Inductor

IV relationshipdt

dvC i =

dt

di Lv =

Energy storage Ec = ½CV2 EL = ½LI2 Continuity Voltage: vc(0

-)=vc(0

+) Current: iL(0

-)=iL(0

+)

Steady-state Open circuit (I=0) Short circuit (V=0)

Series∑=

=n

k k eq C C 1

11 ∑=

=n

k k eq L L

1

Parallel∑=

=n

k k eq C C

1

∑=

=n

k k eq L L1

11



V

. FIRST-ORDER CIRCUITS

• RC circuit – contains only sources, resistors, and 1 capacitor

• RL circuit – contains only sources, resistors, and 1 inductor Æ voltages and currents are described by 1

st-order ODE (ordinary differential equation)

RC Circuits RL Circuits

)()()(

t vt vdt

t dv RC ic

c =+ Rt it vdt

t dv RC ic

c ⋅=+ )()()(

R

t vt i

dt

t d L i

R

i L

L )()(

)(=+

)()()(

t it idt

t di

R

Li L

L =+

Time constant: = RC Time constant: τ = L/R

• Tim

erest X(t), using KCL/KVL and IV

Ke-t/τ

as

τ

e-domain Analysis for 1st-order Circuits

1. Write the ODE in terms of the variable of intrelationships for R, L, C.

2. Find the homogeneous solution Xh(t) by setting input to 0 and substituting Xh(t)=the solution to find the time constant τ (τ=RC for RC circuit and τ=L/R for RL circuit) .(Note: The value of K cannot be found until the complete solution is found in Step 4.)

3. Find the particular solution X p(t). Remember the output follows the form of the input:

input function constant exponential sinusoid

particular solution A-αt -αt

Acos( (wt)A e + B·te wt)+Bsin

Gues ut lve d nts.s the form of the sol ion soand the ODE to fin any arbitrary consta(Note: For sinusoidal inputs, the particular solution can be found more easily using complex imped

Combine the homogeneous and particular solutions to get the complete solution: Xance.)

4. (t) =

Xh(t)+X p(t). Use the initial conditions to find the missing variables (i.e., the K in Xh(t)).

Example: Find vc(t>0) for RC circuit w/ vi(t)=VDD, vc(0-)=0V.

1) )()()( t vt vt dv RC icc =+ 2) vc,h(t) = Ke-t/τ Æ 0=+⎟

⎠ ⎞⎜⎛ − RC

dt ⎝

−− τ τ

τ

t t Kee

K Æ τ = RC

Since vi(t) is a constant, s g nto the ODE, A=VDD=v-t/τ

D- +

c n .

No

3) gues vc,p(t)=A. Plug ing i c,p(t).

4) vc(t) = vc,h(t) + vc,p(t) = Ke + V D. vc(0 )=vc(0 ) by capacitor voltage onti uity Æ

-t/τvc(0)=0=K+VDD K=-VDD. So, vc(t) = VDD-VDDe .

te: Xh(t) represents the transient response of the circuit and should decay to 0 as time

• sponse e to decay by 63%

passes. X p(t) represents the steady-state response of the circuit which persists after the

transients have died away and which takes the form of the input.

Time constant τ – amount of time for the transient exponential re-t/τ

-1(e = 0.63). In 5 time constants, the response decays by 99%. Faster circuits have smaller τ.

• General 1st-order Transient Response for Voltage/Current Step

[ ] τ )(

)()(

+−−

+ −+=o

t t

f e X t X X t X (X is any voltage or cur f o rent in the circuit)

Xf = final value, to = time voltage/c n

(1)+

ty (x(0 )=x(0 )) and steady-state

rule circuit, τ=L/R for LR circuit). R is the Thevenin equivalent resistance “seen” by the cap/ind.

urre t step occurred- +

Find initial value X(to ) and final value Xf . Use continui

s (open/short) for cap/ind. (2) Calculate τ (τ=RC for RC



VI. SE

• inary differential equation)

E: Error! Bookmark not

COND-ORDER CIRCUITS

RLC circuit – contains only sources, resistors, 1 capacitor, and 1 inductor Æ voltages and currents are described by 2

nd-order ODE (ord

General 2nd

-order OD

defined. )()(22

2 t f t xo =++ ω α )()(2 t dxt xd

dt dt

ζ = α/

α = damping coefficient, ωo = undamped natural freq (AKA resonant freq)ωo = damping ratio, f(t) = forcing function (related to the input)

Series RLC Circuit Parallel RLC Circuit

dt

dv

L

t i

LC dt

t di

L

R

dt

t id i1)(

1)()(

2

2

=++t )(

dt

t di

C

t v

LC dt

t dv

RC dt

t vd i )(1)(

1)(1)(

2

2

=++

• Time-domain Analysis for 2st-order Circuits

1. Write the ODE in terms of the va X(t), using KCL/KVL and IV

hips for R, L, C.

g the input to 0 and substituting X(t)=Kest

inton are

riable of interest

relations

2. Obtain the characteristic equation by settinthe ODE: s

2+2αs+ ωo

2=0. Find α and ωo. The roots of the characteristic equatio

22 s ω α α −±−= ; the f 2,1 o o

3. Find the homogeneous solution Xh(t) depending on ζ:

α > ωo, ζ > 1

orm of the solution depends on the damping ratio ζ= α/ω .

overdamped: t t h

oo e K e K t X )(

2)(

1

2222

)(ω α α ω α α −−−−+−

+=

critically damped: α = ωo, ζ = 1 h e K t X = 1)( t t te K α α −− + 2

underdamped: α < ωo, ζ < 1 )sin()cos()( 21 t e K t e K t X nt

nt

h ω ω α α −− +=

22α ω ω −= on = damped natural frequency

(Note: The value of 1 d K 2 cannot be f

particular solution X (t). Reme

K an ound until the complete solution is found.)

4. Find the p mber the output follows the form of the input:

input function constant exponential Sinusoid

particular solution A Ae-αt

+ B·te-αt

Acos(wt)+Bsin(wt)

Guess the form of the solution and solve the ODE to find any arbitrary constants.(Note: F s, the olut more ea mplex impedance.)

5. Com us an rticul ge n: X(t) =

Xh(t)).

or sinusoidal input particular s ion can be found sily using co

bine the homogeneo d pa ar solutions to t the complete solutio

Xh(t)+X p(t). Use the initial conditions to find the missing variables (i.e., K 1, K 2 in

LC o

1=ω

L

R

2

1=α

LC

RC

o1

2

1

=

=

ω

α



V

II. SINUSOIDAL STEADY-STATE ANALYSIS

Any steady-state (SS) voltage or current in a linear time-invariant (LTI) circuit with a sinusoidal input source is

sinusoidal with the same frequency. Only the magnitude and phase (relative to the source) may be different.

• Phasors – vectors (i.e., complex numbers) that represent sinusoids. Since all V,I in the circuitare sinusoids with the same frequency, only magnitude & phase are needed to describe any V,I.

sinusoids: v(t) = Vcos(ωt+θ) = Re[Ve j(ωt+θ)] = Re[Ve jθeωt] Æ phasor: Ve jθ = V∠θ v(t) = Vsin(ωt+θ) = Vcos(ωt+θ-π/2)Æ phasor: V∠(θ-π/2)

Æ For convenience, define phasors in terms of cosine (i.e., the real part of a complex exponential)

, ( jx jx

jee x −−=

21)sin(( )• Euler’s Identity: ,)sin()cos( x j xe jx += jx jx ee x −+=

21)cos(

• Differentiation/integration become algebraic operations w/ phasors (i.e., complex exponentials)

ω jdt d ⇔

ω jdt 1⇔∫ Ex: ( ) )()( θ ω θ ω ω ++ = t jt j

dt d e je

• Capacitor Impedance:C j

Z C ω

1= Æ ICE – Current (I) LEADS Voltage (EMF) by 90°

• Inductor Impedance: L j Z L ω = Æ ELI – Voltage (EMF) LEADS Current (I) by 90°

• Complex Impedance/Generalized Ohm’s Law: I

V Z =

Æ allows for easy nodal analysis (no differential equations); series/parallel resistor laws apply

• Maximum Average Power Transfer Theorem

Æ power transferred to load impedance ZL

is maximized when ZL=Zth*

• Decibel (dB) – unit of measure for ratios of power, voltage, and current levels (often used toexpress gain). Power: 1dB=10log10(P1/P2); V,I: 1dB=20log10(V1/V2)=20log10(I1/I2)

• Frequency Response – system’s inputÆoutput transfer function vs. frequency (givensinusoidal input). Both magnitude and phase plots are needed (output freq = input freq)

General transfer function – can be written as a product of poles and zeroes

Error! Bookmark not defined.( )

⋅⋅⋅⎟ ⎞

⎜⎛

+⎟ ⎞

⎜⎛

+

⋅

11j j

j

ω ω

ω ω

ω

⎠⎝ ⎠⎝

⋅=

21

)(

p p

j Ae H ω θ ⋅⋅⋅⎟

⎠ ⎞⎜

⎝ ⎛ +⎟

⎠ ⎞⎜

⎝ ⎛ +

2111

z z n

j jω

ω ω

ω zeroes – roots of the numerator

poles – roots of the denominator

Break point frequency ωBP – poles and zeros are break point freq’sÆ at a zero frequency, the magnitude is +3dB (=√2) and the phase is +45°

Æ at a pole frequency, the magnitude is -3dB (=1/√2) and the phase is -45°

• Bode Plot – logarithmic plots for frequency response

Ae jθ

jω 1/jω (1+jω/ωz) 1/(1+jω/ω p))( j H

to draw Bode plot for general transfer function, add individual pole and zero plots

z ω ω 10

10 z

ω

dB40 decdB20+

dB0

dB20

z ω z ω 10

10 z

ω

2π +

04π +

pω pω 1010

pω

decdB20+

decdB20−

A

)( ω j H dB0 dB0 dB01 1 dB20−

dB40−decdB20−

pω 10 p

ω

pω 10

2π −4π −

0)( j H ∠

2π −

002π +θ



• Filters

Lowpass Filter (LPF) – VC in RC circuit / VR in RL circuit / VC and RLC circuit

(for current output, switch from series to parallel and switch L and C)

R L jV

V

in

out H ω

ω +

==1

1)( RC jV

V

in

out H ω

ω +

==1

1)(( ) LC j RC jV

V

in

out H 2

1

1)(ω ω

ω ++

==

Highpass Filter (HPF) – VL in RL circuit / VR in RC circuit / VL in RLC circuit

(for current output, switch from series to parallel and switch L and C)

R L j

R L j

V

V

in

out H ω

ω ω

+==

1)(

RC j

RC j

V

V

in

out H ω

ω ω

+==

1)( ( )

( ) LC j RC j

LC j

V

V

in

out H 2

2

1)(

ω ω

ω ω

++==

Bandpass Filter (BPF) – VR , IR in RLC circuit

( ) LC j RC j

RC j

V

V

in

out H 2

1)(

ω ω

ω ω

++==

Æ at low freq, cap. impedanceC jC Z

ω 1= dominatesÆ

inout in Z

V

Z

V RCV j IRV CV j I

C

in

tot

in ω ω ≈==≈= ,

Æ at high freq, ind. impedance L j Z L ω = dominatesÆ R L j

V out L j

V

Z

V

Z

V inin

L

in

tot

in IRV I ω ω

≈==≈= ,

Resonant Frequency LC

o1=ω

Æ At ωo, oC L

C jC jZ j Z o

−=−==ω 1 , oC

Lo L jZ j L j Z +=+== ω Æ inout V V =

(capacitor and inductor impedances are equal in magnitude, opposite in sign)

Æ Characteristic Impedance: C L Z o =

BPF Bandwidth Δω = 2α = difference between half-power frequencies

Quality Factor Q – (1) measure of “peakiness” or filter selectivity (high QÆ low bandwidth)

(2) measure of energy stored vs. energy dissipated (high QÆ low loss)

ζ α

ω

ω

ω

21

2===

ΔooQ series RLC:

R

C L

R

Z oQ == parallel RLC:

C L

R Z R

o

Q ==

Tradeoffs: Bandwidth/selectivity/speed/energy loss

(e.g., high QÆ low Δω (high selectivity)Æ low α Æ slow transients e-αt

)



V

III. DIODES

Æ Passive devices that only pass current in one direction

• Shockley Diode Equation: ( 1−= th DV v

S D e I i

IS = reverse-bias saturation current (~10-12 A for Silicon)

Vth = k BT/q = thermal voltage (~26mV @ room temp T=300K)

• Large-Signal Diode Model (simplifies circuit analysis)

2 states: “on” – forward bias (vD = VT): iD ≥ 0

“off” – reverse bias (vD < VT): iD = 0

VT = threshold voltage ~ 0.6V

• Ideal Diode Model (Perfect Rectifier) Æ large-signal diode model with VT = 0

• Zener Diode (simplified) 3 states: forward bias: vD = VT, iD ≥ 0

reverse bias: VBD < vD < VT, iD = 0

breakdown: vD = VBD, iD ≤ 0

• Diode Circuit Analysis – Method of Assumed States

(1) Guess the state of each diode (on or off). For large-signal diode model, replace “on”

diodes with voltage source with voltage drop VT and “off” diodes with open circuits.(2) Solve the circuit using KCL/KVL.

(3) Check if assumptions for diode states were correct (i.e., check that “on” diodes have iD≥ 0

and “off” diodes have vD < VT). If not, start over, guessing new states for the diodes.

• Rectifier Circuit

• Peak Detector Circuit (VT=0)

• AC-DC Converter (VT=0)



I X. MOSFET

Metal Oxide Semiconductor Field Effect Transistor (transistor – a 3+ terminal device in which one terminal controls the current flow between the other two terminals)

Æ For a MOSFET, the gate controls the current flow between source and drain.

For an n-channel MOSFET (NMOS), a positive gate voltage produces current flow

For a p-channel MOSFET (PMOS), a negative gate voltage produces current flow NMOS PMOS

analog

digital

Circuit S mbols: NMOS Ph sical Structure:

• NMOS IV Characteristic – Square Law Model3 regions of operation:

cutoff VGS < VTn IDS = 0

triode/linear VGS > VTn

VDS ≤ VGS - VTnIDS = K n(VGS-VTn-VDS/2)VDS

saturationVGS > VTn

VDS ≥ VGS -VTnIDSAT = ½K n(VGS-VTn)

2

VGS = VG –VS , VDS = VD –VS

VTn = threshold voltage (NMOS)

VDSAT = VGS - VTn = saturation voltageIDSAT = saturation current

K n = constant determined by manufacturing process and transistor size (units: A/V2)

• Channel-Length Modulation Parameter λ Æ In the saturation region, IDS is not perfectly constant for all VDS ≥ VDSAT; as VDS increases,

IDS also increases. An additional factor (1+λVDS) in the IV equation models this effect (the

factor is also added to the triode equation to make the IV curve continuous):

cutoff VGS < VTn IDS = 0

triode/linear VGS > VTn

VDS ≤ VDSATIDS = K n(VGS-VTn-VDS/2)VDS(1+λnVDS)

saturationVGS > VTn

VDS ≥ VDSATIDS = ½K n(VGS-VTn)

2(1+λnVDS)

• PMOS IV Characteristic – Square Law ModelÆ Same as NMOS, but switch polarity for everything (VTp is typically negative)

cutoff VSG < -VTp ISD = 0

triode/linear VSG > -VTp

VSD ≤ VSG + VTpISD = K p(VSG+VTp-VSD/2)VSD(1+λ pVSD)

saturationVSG > -VTp

VSD ≥ VSG +VTpISD = ½K p(VSG+VTp)

2(1+λ pVSD)



X

. MOSFET CIRCUIT ANALYSIS

• Notation: uppercase w/ uppercase subscript (e.g., VIN, VOUT) – DC large signal

lowercase w/ lowercase subscript (e.g., vin, vout) – AC small signal

lowercase w/ uppercase subscript (e.g., vIN, vOUT) – total signal, DC+AC

• Large-signal Analysis – find DC operating point (models nonlinearity of MOSFET IV equation)

Method 1: Load-line (graphical) Analysis. Requires MOSFET IV curves. Method 2: Method of Assumed States.

(1) Guess region of operation for each MOSFET.

(2) Solve circuit with KCL/KVL/nodal analysis, substitutingappropriate IV equation for MOSFET IDS.

(3) Check that assumptions for MOSFET operating regions were

correct (triode: VGS ≥ VT, VDS ≤ VGS-VT; saturation: VGS ≥ VT, VDS ≥ VGS-VT). If not, start over, guessing new operating

regions for the MOSFETs.

Large-signal

Circuit Model

• Small-signal Analysis – find small-signal gain, R in, R out (use a linearized circuit model for the MOSFET)

Æ small-signal circuit model is a linearized model for the MOSFET, only valid for smallsignals near a given DC operating point (AKA “quiescent point”)

Æ allows for linear circuit theory (superposition, phasor analysis)

transconductance:Q

v

im

GS

DS g ∂

∂= output resistance:

Q DS ∂

∂==

11

v

i g o DS ds

r

Note: Evaluate small-signal parameters at DC operating point

small-signal parameter Gm r o

Small-signalCircuit Model

triode/linear KVDS(1+λVDS) small VDS: 1/[K(VGS-VT)]

saturation K(VGS-VT)(1+λVDS) 1/[K(VGS-VT)2λ]

• MOSFET Amplifier Analysis(1) Large-signal analysis – Find DC operating point w/ load-line analysis or method of assumed states.

(2) Small-signal analysis – Zero out all DC sources, replace MOSFETs with small-signal model, and

find gm and r o for each MOSFET at the DC operating point.

To find voltage gain Av = vout/vin, solve for vout using KCL/KVL/nodal analysis.

To find R in and R out, zero out all independent sources and find R th at the input and the output (this

may require VTEST/ITEST method).

• Common Source Amplifier

Large Signal Small Signal

Av=vout/vin = -gm(r o || R D)

R in = ∞

R out = r o || R D



XI. OP-AMPS

• Operational amplifier – high-gain voltage amplifier with differential inputs and single outputCircuit Symbol Circuit Model Input/Output Characteristic

Vo = A(V p-Vn), Vo = [VSS,VDD]Æ Note: Vo cannot exceed the power supply rails VDD and VSS

A = Gain, R in = input resistance, R out = output resistance

• Ideal op-amp: A → ∞, R in→ ∞, R out→ 0

• Negative Feedback – since it’s hard to make the op-amp gain stable over all operating

conditions (the gain fluctuates with temperature, process variation, and power supply noise),negative feedback is used to stabilize the op-amp outputÆ negative feedback usually occurs when the output is connected to the negative input terminal

• Suuming Point Constraint – for ideal op-amp in negative feedback

(1) i p=in=0 (since R in=∞) (2) v p=vn (for stable Vo=A(V p-Vn), A=∞)• Op-amp Analysis – (1) Check for negative feedback. (2) Apply summing point constraint.

(3) Solve the circuit using circuit-analysis techniques (remember that Vo cannot exceed the supply rails).

• Op-amp CircuitsInverting Amplifier Noninverting Amplifier Unity-gain Buffer

Adder Subtractor

1=in

out

V

V

1

2

R

R

V

V

in

out −=2

11 R

R

V

V

in

out +=

( )211

2 V V V R

Rout −=

⎟ ⎠ ⎞⎜

⎝ ⎛ +−= 21

2

3

1

3 V V V R

R

R

Rout

Integrators

( ) LC jV V

in

out

2

1

ω −=

R L jV V

in

out

ω 1−=

RC jV

V

in

out

ω 1−=

Differentiators

R L jin

out

V

V ω −= ( ) LC j

in

out

V

V 2ω −= RC j

in

out

V

V ω −=

• Cascading Op-amp Circuits – Find gain of each stage and multiply them together to get total gain



XII. DIGITAL CIRCUITS

• analog: signals (voltage and current) are continuous with time

digital: signals are discrete (e.g., “0” and “1”) Æ advantage: less sensitive to noise, easier to transmit

• Booelan Algebra – Primitive Rules

Associative A + (B + C) = (A + B) + C A · (B · C) = (A · B) · C

Commutative A + B = B + A A · B = B · A

Distributive A + (B · C) = (A + B) · (A + C) A · (B + C) = (A · B) + (A · C)

Identity A + 1 = 1 A · 0 = 0

Identity A + 0 = A A · 1 = A

ComplementA + A = 1 A · A = 0

Idempotence A + A = A A · A = A

Absorption A + (A · B) = A A · (A + B) = A

AbsorptionA + ( · B) = A + B A · ( + B) = A · B

• Common Gates (Note: Bubble means inversion)

• DeMorgan’s Laws (AKA “bubble pushing”)

(1) B A B A +=⋅

(2) B A B A ⋅=+

• Truth Tables – list output value for each input combination (2n entries for n inputs)

Æ Sum of Products Form – write output logic expression as sum (OR) of

products (ANDs), where each product corresponds to each “1” entry in the truth table

A B C Out

0 0 0 1

0 0 1 0

0 1 0 10 1 1 0

1 0 0 1

1 0 1 0

1 1 0 0

1 1 1 0

Ex: C B AC B AC B AOut ⋅⋅+⋅⋅+⋅⋅=

• MOSFET Switch Models (NMOS)Ideal Switch Model Switch-Resistor Model

• Noise Margins

Æ Voltage Output High/Low:VOH=F(VOL), VOL=F(VOH)

Æ Voltage Input High/Low (VIH, Vw

IL):here voltage transfer curve slope=-1

Æ N

Æ L –VOL

oise Margin High/Low:

NMH = VOH –VIH

NML = VIL –VOL

ogic Swing: VOH



• NMOS Inverter (Resistor Pull-up)Loadline Analysis:

NMOS Inverter Disadvantages:

No rail-to-rail swing (low noise margins)

Large R D required to keep VOL low and power low [I=VDD/(R D+R on)]

Large R D means large area and slow transient response for Vout=0ÆVDD

• CMOS Inverter Voltage-Transfer Characteristic:

Loadline

Analysis:

CMOS Inverter Advantages: Rail-to-rail swing (big noise margins) No static power consumption (either NMOS or PMOS off)

• NMOS Pass Strong “0”, Weak “1” – For Vin=VDD: Since VGS≥VTn for NMOS on and

VGS=VDD –VOUT, VDD –Vout≥VTn, Vout≤VDD –VTn Æ NMOS can’t pass strong “1”

• PMOS Pass Strong “1” , Weak “0” – (same analysis as above)



• General CMOS Logic Gate Implementation

Æ Pull-up network (PUN) and Pull-down n

(PDN) are complementary (only one is “on” at a

time), so Vout is either VDD or GND (“0” or “1”)

Æ PUN

etwork

and PDN are duals of each other (parallel

Procedure

transistors in one network are series transistors

in the other network)

: (1) Express logic as ( ) X F = , the NOT of some logic expression X.

ND, parallel NMOS=OR.

CMOS Inverter Propagation Delay – delay from input to output due to output load capacitance

measured between 50%

put

use switch-resistor model for

high-to-low delay (NMOS on): low-to-high delay (PMOS on):

p = (tpHL+tpLH

eral CMOS Gate Delay itch-resistor model, find R eq for PUN or PDN, t p=0.69R eqCL

(2) Since F=0 when X=1, construct PDN from X. Series NMOS=A

(3) Construct the PUN as the dual of the PDN.

•

Æ

transition points of the in

and output signalsÆ

MOSFETs

tpHL=0.69R nCL tpLH=0.69R pCL

average propagation delay: t )/2

• GenÆ replace MOSFETs with sw

summary notes on electrical engineering

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