Supply Voltage Biasing

Andy Whetzel and Elena WeinbergUniversity of Virginia

Agenda• Background

o FinFET technology• Problem and approach• Our design• Implementation• Results• Discussion• Conclusion

BackgroundFinFET Technology• Scalable• Higher drive strength per unit silicon

Image from: http://www.ece.uc.edu/~kroenker/Research/Research%20Project%20Summaries/FINFET_image004.jpg

Image from: http://www.siliconsemiconductor.net/images/news/image-76523-2012-12-12.jpg

ProblemBody biasing does not work on FinFETs• MOSFET vs. FinFET:

https://www.semiwiki.com/forum/content/attachments/5665d1355855218-planar-vs.-3d-finfet.jpg

ApproachSupply voltage biasing with FreePDK

Contributions:1. Our design for supply voltage biasing2. A new knob3. A new technique for decreasing delay in

integrated circuits (ICs) implementing FinFET technology

Supply Biased Inverter Gate

Ring Oscillator

• 11 Inverters• Swept bias voltage

from -0.1 V to 0.1 Vo 1.1 V nominal

• Measured frequency, active power, and static power vs. bias voltage

Ring Oscillator Results

-0.15 -0.1 -0.05 0 0.05 0.1 0.1502468

1012

Frequency vs. Supply Bias

Bias (V)

Nor

mal

ized

Fre

q.

-0.15 -0.1 -0.05 0 0.05 0.1 0.150

0.5

1

1.5

2

Active Power vs. Supply Bias

Bias (V)

Nor

mal

ized

Pow

er

-0.15 -0.1 -0.05 0 0.05 0.1 0.150

102030405060

Static Power vs. Supply Bias

Bias (V)

Nor

mal

ized

Pow

er

NAND and NOR Gates• Designed similarly to supply biased inverter

o Double the transistors, one high and one low output• Setup in ring oscillator configuration such that

high output is tied to NMOS and low output is tied to PMOS in subsequent gate

• Results were similar, therefore we obtained the motivation to pursue combinational logic other than a ring oscillator

Full Adder

8 Bit Ripple Carry Adder

-150 -100 -50 0 50 100 1500

0.20.40.60.8

11.21.41.6

Delay vs. Supply bias

Bias (mV)

Nor

mal

ized

Del

ay

-150 -100 -50 0 50 100 1500

10203040506070

Static Power vs. Supply Bias

Bias (mV)Nor

mal

ized

Sta

tic

Pow

er

-150 -100 -50 0 50 100 1500.00.51.01.52.02.5

Switching Power vs. Supply Bias

Bias (mV)

Nor

mal

ized

Pow

er

-120 -100 -80 -60 -40 -20 00.00.20.40.60.81.01.2

Static Power vs. Reverse Supply Bias

Bias (mV)Nor

mal

ized

Sta

tic

Pow

er

Discussion

• Our design shows potential to reduce delay in ICs

Trade-offs:• Area• Power

Conclusion• We successfully designed and implemented a new

knob• Our design decreases delay in ICs implementing

FinFET technology• Area and power trade-offs

Future Work• Further investigation of static and switching power in

FinFETs under supply bias• Explore accuracy of gate induced drain leakage (GIDL)• Generating bias voltages

Questions?

Image from: http://www.synopsys.com/Company/Publications/SynopsysInsight/Pages/Art2-finfet-challenges-ip-IssQ3-12.aspx