survey of packet classification algorithms

Survey of

Packet Classification

Algorithms

Outline

Background and problem definition

Classification schemes

– One dimensional classification

– Two dimensional classification

Background

Flow-aware vs. Flow-unaware Routers Flow-aware router

– Keep track of flows and perform similar processing on packets in a flow

Flow-unaware router

– Packet-by-packet router

– Treat each incoming packet individually

Why Flow-aware Router? Additional mechanisms required

– Admission control, resource reservation, per-flow queueing, fair scheduling etc.

Provision of DiffService in ISPs

– Capability to distinguish and isolate traffic belonging to different flows based on negotiated service agreements

Classification

Rules or Policies

Need for DiffService Service

Traffic shaping Traffic filtering Policy routing

ISP1

NAP

E1

E2

ISP2

ISP3Z

X

Y

More Value added Services DiffService

– Regard traffic from Autonomous System #33 as `platinum grade’

Accounting and billing– Treat all video traffic as highest priority and perf

orm accounting for this type of traffic Committed access rate (rate limiting)

– Rate limit WWW traffic from sub interface#739 to 10Mbps

Flow-aware Router-Basic Architectural Components

Special processing

Control

Datapath:per-packet processing

Routing lookup

Routing, resource reservation, admission control

Packet classification

Switching

Scheduling

Flow Classification

Forwarding Engine

Flow Classification

HEADER

Flow Index

Classifier (Policy Database)

Predicate Action

IncomingPacket

Classful Addresses

0

10

110

Network Host

Network

Network

Host

Host

Class A

Class B

Class C

7 24

21 8

14 16

Every address was class A or B or C, easily determined by the first three bits of the address

Classless InterDomain Routing (CIDR)

Prefix can be of arbitrary length

208.12.16/24 208.12.21/24 208.12.31/24

0 232-1Total IPv4 address space

Prefix ranges

208.12.21/24

0 232-1Total IPv4 address space

208.12.16/20

These addresses match both prefixes

An exception prefix

Table Growth of a Backbone Router

From http://www.telstra.net/ops/bgptable.html

Prefix Length Distribution

Problem

Definition-

Packet

Classification

Given a classifier C with N rules, Rj, 1 j N, where Rj consists of three entities

– A regular expression Rj[i], 1 i d, on each of the d header fields,

– A number, pri(Rj), indicating the priority of the rule in the classifier, and

– An action, referred to as action(Rj)

Classification is a Generalization of Lookup

Classifier = routing table

One-dimension (destination address)

Rule = routing table entry

Regular expression = prefix

Action = (next-hop-address, port)

Priority = prefix-length

Metrics for Classification Algorithms Speed

Storage requirements

Low update time

Ability to handle large classifiers

Flexibility in implementation

Low preprocessing time

Scalability in the number of header fields

Flexibility in rule specification

One Dimensional


–

IP Address Lookup

Algorithms

Binary Tries

Prefixesa 0*b 01000*c 011*d 1*e 100*f 1100*g 1101*h 1110*i 1111*

a d

c

b

e

h if g

0

0

0

0

0

0

0

0 0

1

1

1 1

1

11

Path-Compressed Trie


a d

ec

h if g

0

0

0

0 0

1

1 1

1

11

b

0

1

3 2

3

4 4

Legend: x indicates to inspect which bit

Disjoint-prefix Binary Trie


c

b

e

h if g

0

0

0

0

0

0

0

0 0

1

1

1 1

1

11

a1

0

a3

1

a2

1

d1

1

Leaf pushing Disjoint prefixes do not overlap No prefix is itself a prefix of another

Variable-stride Multibit Trie

a

c

01 10

a d d

00 11

c

b

ihgfe

00

0 1

0 101 1011 00 11

01 10

stride=2stride=1


Reduced number of memory accesses Greater wasted space

Caching Addresses

CPU

MAC

LocalBuffer

Memory

LineCard

DMA

MAC

LocalBuffer

Memory

Fast Path

Slow Path

Advantages Increased average lookup performance

Disadvantages Decreased locality in backbone traffic Cache size Cache management overhead Hardware implementation difficult

LineCard

LocalBuffer

Memory

LineCard

DMA DMA

MAC

BufferMemory

Hash-based Scheme Store a hash table for each prefix length Hash key is the prefix value and prefix

length Search scheme

– Linear search on prefix lengths

– Binary search on prefix lengths Need to provide intermediate markers

– Guide to more specific prefix

Need precomputation per marker– Avoid backtracking

Linear Search on Prefix Lengths

Prefixesa 0*b 01000*c 011*d 1*e 100*f 1100*g 1101*h 1110*i 1111*j 01*k 1100001*p 101*

a d

j

c

b

e

h if g

0

0

0

0

0

0

0

0 0

1

1

1 1

1

11

p1

0

0

k1

1

3

2

5

7

6

4

Linear searchon length

Binary Search on Prefix Lengths

Prefixesa 0*b 01000*c 011*d 1*e 100*f 1100*g 1101*h 1110*i 1111*j 01*k 1100001*p 101*

a d

j

c

b

e

h if g

0

0

0

0

0

0

0

0 0

1

1

1 1

1

11

p1

0

0

k1

1

3

2

5

7

6

4

Binary search on length

Lookups with Ternary-CAM

Memory array Priority

encoder

Next-hopmemory

Next-hop

TCAM RAM

01

23

M

0

1

00

1

DestinationAddress

Lookups with Ternary-CAM

Advantages– Suitable for multiple fields– Fast: 16-20 ns (50-66 Mpps)– Simple to understand

Disadvantages– Inflexible: range-to-prefix blow

up– Density: largest available in 200

0 is 32K x 128 (but can be cascaded)

– Management software, and on-chip logic: non-trivial complexity

– Power: 5-8 W– Incremental updates: slow– DRAM-based CAMs: higher dens

ity but soft-error is a problem– Cost: $30-$160 for 1Mb

Two Dimensional


Set-pruning Tries

Rule DA SA

R1 0* 10*

R2 0* 01*

R3 0* 1*

R4 00* 1*

R5 00* 11*

R6 10* 1*

R7 * 00*

Dimension SA

Dimension DA

R7 R2 R1 R5 R7 R2 R1

R3

R7

R6

R7

R4

Hierarchical Tries

Dimension DA

Dimension SA

R5 R2 R1

R3R6

R7

R4

Rule DA SA

R1 0* 10*

R2 0* 01*

R3 0* 1*

R4 00* 1*

R5 00* 11*

R6 10* 1*

R7 * 00*

Grid-of-Tries

Dimension DA

Dimension SA

R5 R2R1

R3R6

R7

R4

Rule DA SA

R1 0* 10*

R2 0* 01*

R3 0* 1*

R4 00* 1*

R5 00* 11*

R6 10* 1*

R7 * 00*

Grid-of-Tries – cont.

Advantages

Good solution for two dimensions

Disadvantages

Static solution Not easily extensible to more than two dimensions

20K entries: 2MB, 9 memory accesses (with expansion)

Bitmap-intersection

R4 R3 R2R1

1

1

0

0

1

0

1

1

R3

R4

R1

R2

Bitmap-intersection – cont.

Advantages

Good solution for multiple dimensions, for small classifiers

Disadvantages

Static solution Large memory bandwidth (scales linearly in N) Large amount of memory (scales quadratically in N) Hardware-optimized

512 rules: 1Mpps with single FPGA (33MHz) and five 1Mb SRAM chips

Cross-producting

R4 R3R2

R1

5

4

3

2

1

6

21 7 8 94 5 63

P1P2

(1,3)

(8,4)

Cross-producting – cont.

Advantages

Fast accesses Suitable for multiple fields

Disadvantages

Large amount of memory Need caching for bigger classifiers (> 50 rules)

50 rules: 1.5MB, need caching (on-demand cross-producting) for bigger classifiers

Need: d 1-D lookups + 1 memory access, O(Nd) space

survey of packet classification algorithms

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