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University of North Carolina at Charlotte

Department of Electrical Engineering

Laboratory Experimentation Report

Name: Ethan Miller Date: June 18, 2013

Course Number: ECGR 2156 Section: L90

Experiment Title: [2] Switch Debouncing, [3] Seven Segment Decoder, [3] Counting Circuits

Experiment Number: 2, 3, 4

Lab Partner: Waqee Hassan

Objective:

Experiment 2:

The objective of this experiment was to experience one of the problems in a

simple digital system design (switch-debouncing circuit). From this circuit, the full effect of the

problem and its solution was found.

Experiment 3:

The objective of this experiment was to build a seven-segment decoder. The

information was stored in the logic circuit by BCD (Binary Coded Decimal). The BCD was used

to store any numbers between 0 and 9. Also to learn basic skills needed to design simple circuits

that involve a BCD to seven-segment decoder.

Experiment 4:

The objective of this experiment was to build and study the methods of sequential

design throughout a synchronous four-bit binary counter with a parallel load. A sequential circuit

involved D, T and J-K flip flops.

Equipment List:

Experiment 2:

7461 counter

SR Latch

Clear and Clock push button

Three 10k ohms resistors

Experiment 3:

Multimeter

Power Supply

Breadboard

One four-bit dip switch

One 7447 (BCD to seven-segment decoder driver)

Seven current limiting resistors (470 Ω)

One common anode seven segment display

Connection wire

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Experiment 4:

LED’S for the outputs

Slide switches

Pulsar

1.2 ohm

SN74191 MSI Counter

Power supply

Jumper Cables

T Flip Flop

D Flip Flop

J-K Flip Flop

Relevant Theory/Background Information:

Experiment 2:

Here are some simple logic gate is involve in the SR latch and the counter, which

involve tables 1-7 and figures 1-7.

Logic Gates:

NOT: In table 1. A number enters the gate and returns the opposite number

Figure1: NOT Gate

Table 1: NOT Gate

OR: In table 2, two or more numbers enter the gate of (0 or 1), but only 1 is the output if

a 1 enters the gate.

Figure 2: OR Gate

A Q

0 1

1 0

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Table 2: OR Gate

A B F

0 0 0

0 1 1

1 0 1

1 1 1

AND: In table 3, two or more numbers enter the gate of (0 or1), but all the numbers enter the

gate have to be 1 for it to return a 1.

Figure 3: AND Gate

Table 3: AND Gate

A B Y

0 0 0

0 1 0

1 0 0

1 1 1

NOR: In table 4, two or more numbers enter the gate of (0 or 1), but only 1 is the output if a 1

enters the gate. When there is an output of 1, then it switches that number to 0 visa versa if it

outputs 0, the gate switches to 1.

Figure 4: NOR Gate

Table 4: NOR Gate

A B Y

0 0 1

0 1 0

1 0 0

1 1 0

NAND: In table 5, two or more numbers enter the gate of (0 or 1), but all the numbers enter the

gate have to be 1 for it to return a 1. When there is an output of 1, then it switches that number to

0 visa versa if it outputs 0, the gate switches to 1.

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Figure 5: NAND Gate

Table 5: NAND Gate

A B Y

0 0 1

0 1 1

1 0 1

1 1 0

XOR: In table 6, two or more numbers enter the gate of (0 or 1), but only 1 is the output if a 1

enters the gate. Also, if two 0’s and two 1’s enter the gate the output will return 0.

Figure 6: XOR Gate

Table 6: XOR Gate

A B Y

0 0 0

0 1 1

1 0 1

1 1 0

XNOR: In table 7, two or more numbers enter the gate of (0 or 1), but only 0 is the output if a 1

enters the gate. Also, if two 0’s and two 1’s enter the gate the output will return 1.

Figure 7: XNOR Gate

Table 7: XNOR Gate

A B Y

0 0 1

0 1 0

1 0 0

1 1 1

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Figure 8: One Switch Bounce circuit

One very important appraise from a digital design circuit was the switch bounce. The

switch bounce mechanisms were related to the mechanical design from a switch and large

electric fields. These electric fields have developed contacts that are very close to each other.

Contacts have known to result in arcing, but soon should make a stable contact. In most designs

the arching was no alarm, but in some situations arch has caused some seriously detrimental

results.

From the circuit in figure 8, there are two push buttons; clock input- to provide a signal to

the counter and a clear input- to provide a clear signal to the counter. The counter that was used

is called the 7461 counter. This counted in binary from 0 to 9, an up counter; with a timing edge-

trigger active low asynchronous clear and an active low synchronous parallel load. To stop the

parallel load an input was connected to 5 volts. The switches are in either logical 1 or logical 0

(on and off positions). Both are in open positions, so both are in logical 1. If the switched was in

closed position, they are in logical 0.

The counter resets to all zeros, as the clear button was pushed. The clear button is

asynchronous, which automatically clears the circuit without any clock pulse. As this happened

the effects of the circuit showed no bouncing. With the clock button released the counter

incremented by 1every time from a leading edge-trigger. A leading edge-trigger was a point at

which the clock pulse started at. Showed in figure 9, the arching or switch bouncing was present,

then there was numerous leading edges which caused the counter to have an unknown clock

pulse input; this bounced back and forth from low to high values. When the contact came to a

finished point, the clock remains at logical 0, until the switch was opened again. Once the switch

was opened the arcing starts again until the contacts were far apart from each other.

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Figure 9: Timing Diagram

The answer to this problem in the de-bouncing circuit was SR latch. This SR latch was

constructed with two NAND logic gates that were cross-coupled showed in figure 10. When

inserting the latch into the circuit the clock push button was known to defeat the bouncing problem

from the set, reset and storage states. In figure 10 shows how a SR latch works, it starts out with a set

state which was logical 1.

Figure 10: SR Latch

Figure 11: Switch Debouncing circuit

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Experiment 3:

A seven-segment decoder was construction by basic logic gates. These logic gates

used BCD system (Binary Coded Decimal) which ranges from 0 to 9 during this circuit. A BCD

system has a four bit code that represents by binary number from 0000 to 1001. BCD and a

seven-segment display allowed the circuit to display binary numbers on a seven-segment display.

The steps that involve of making a circuit were: 1) truth tables- a collection of tables and

numbers that output either 1 for on or 0 for off showed in table 8, 2) K-maps- a way to simplify

the main equation showed in tables 9 to 15, 3) logic gate circuit- a way to display the results for

the design showed in figure 13. From the design that was made for the BCD to seven-segment

decoder, a 7447 (BCD to seven-segment decoder driver) was used. In figure 12 shows how the

circuit was built and design a BCD to seven-segment decoder.

Table 8: Truth Table BCD to Seven-Segment Decoder

# D C B A a b c d e f g

0 0 0 0 0 1 1 1 1 1 1 0

1 0 0 0 1 0 1 1 0 0 0 0

2 0 0 1 0 1 1 0 1 1 0 1

3 0 0 1 1 1 1 1 1 0 0 1

4 0 1 0 0 0 1 1 0 0 1 1

5 0 1 0 1 1 0 1 1 0 1 1

6 0 1 1 0 1 0 1 1 1 1 1

7 0 1 1 1 1 1 1 0 0 0 0

8 1 0 0 0 1 1 1 1 1 1 1

9 1 0 0 1 1 1 1 1 0 1 1

Table 9: K map for a

DC\BA 00 01 11 10

00 1 0 1 1

01 0 1 1 1

11 x x x x

10 1 1 x x

Table 11: K map for c

DC\BA 00 01 11 10 Table 12: K map for d 00 1 1 1 0 DC\BA 00 01 11 10 01 1 1 1 1 00 1 0 1 1 11 x x x x 01 0 1 0 1 10 1 1 x x 11 x x x x 10 1 1 x x

Table 10: K map for b

DC\BA 00 01 11 10

00 1 1 1 1

01 1 0 1 0

11 x x x x

10 1 1 x x

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Figure 12: Circuit Digram for a LCD Display

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Table 13: K map for e

DC\BA 00 01 11 10

00 1 0 0 1

01 0 0 0 1

11 x x x x

10 1 0 x x

Table 15: K map for g

DC\BA 00 01 11 10

00 0 0 1 1

01 1 1 0 1

11 x x x x

10 1 1 x x

Experiment 4:

Counting and Frequency division are some of the most important things when designing

a sequential digital circuit. Counters are measured in bit size and can count up to a binary

number of 2 times the size. From different designs a non-sequential counting sequence was more

desired than a divided frequency circuits.

There are some different ways to build a sequential counter. These are D, T and J-K flip

flop. For this circuit there was a need for a four-bit binary counter. This counter has a parallel

load with a pulse input and parallel data inputs. A logic circuit for a parallel load, feedback logic,

was loaded from the preferred initial state when the Ld pulse was applied. Active low

asynchronous logic circuits with a parallel load have presets and clear input on the flip flops.

Three T flip flops was used in this logic circuit for memory, feedback logic and parallel load was

made from a combination of AND, OR, inverter gates. Each T flip flop was implemented with a

J-K flip flop. The use of two twin trailing-edge-triggered J-K flip flops was designed in a

SN74LS112 counter.

Experiment Data/Analysis:

Experiment 2:

A circuit was built showed in figure 8 on a bread board, the counter outputs was

connected to the LED’s on the bread board to observe the state of counter. The counter was

cleared by pressing the clear push button or reset button. This verified the counter to a state of 0.

As the clock button was selected (but not let go), the count value was recorded. Then the clock

value was selected and the count values were recorded again, which started to have a switch

bouncing in the circuit. This process was repeated 5 times to insure actuate results.

Another circuit was built showed in figure 11 on a bread board, the counter

outputs was connected to the LED’s on the bread board to observe the state of counter. The

counter was cleared by pressing the clear push button or reset button. This verified the counter to

a state of 0. As the clock button was selected (but not let go), the count value was recorded. Then

the clock value was selected and the count values were recorded again, which started to have a

switch bouncing in the circuit. This process was repeated 5 times to insure actuate results.

Table 14: K map for f

DC\BA 00 01 11 10

00 1 0 0 0

01 1 1 0 0

11 x x x x

10 1 1 x x

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Table 16: With no debouncing Switch

Trial Expected Count Value Measured Count Value

# LED 1 LED 2 LED 3 LED 4 LED 1 LED 2 LED3 LED 4

1 0 0 0 1 0 0 0 1

2 0 0 1 0 0 1 0 0

3 0 0 1 1 0 1 0 1

4 0 1 0 0 0 1 1 0

5 0 1 0 1 0 1 1 1

6 0 1 1 0 1 0 0 0

AVG 3.5 5.1

Table 17: With debouncing Switch

Trial Expected Count Value Measured Count Value

# LED 1 LED 2 LED 3 LED 4 LED 1 LED 2 LED3 LED 4

1 0 0 0 1 0 0 0 1

2 0 0 1 0 0 0 1 0

3 0 0 1 1 0 0 1 1

4 0 1 0 0 0 1 0 0

5 0 1 0 1 0 1 0 1

6 0 1 1 0 0 1 1 0

AVG 3.5 3.5

The solution to this problem was a SR latch. This SR latch was connected in a circuit in

figure 11. A SR latch works generally with a set state input, as showed in figure 10. S has a state

of logical 0 and R has a state of logical 1, the Q output then goes to logical 1. When the clock

button was pushed, S goes to logical 1 and R goes to logical 1. This state (storage state) Q output

still stayed the same, Q output was logical 1. When the switch moved from S to R inputs, the

latch stayed the same storage state Q was logical 1 until a contact between the S and R inputs.

With this contact or arc S goes to logical 1 and R goes to logical 0 this was called the reset state.

The Q produced a logical 0 output. From this result the counter experienced and increment by 1

from the set state of 0001 to 0011 or from 1 to 6. This showed in table 17.

As showed in table 16, there was no SR latch so the circuit was bouncing. The start value

was 0001 or 1. Then the circuit started to bounce, but the circuit started at 4 and counted up to 8.

This was what the circuit was doing when the clock push button was executed.

Some applications of a switch debouncing circuit involve a circuit that has one signal of

input and is incremented by some value. These circuits are a digital clock, calculator, and any ac

circuit, pressing keyboard letters and numbers, digital counter, personal computer and a micro-

processor. Basically anything that involves pressing a button or switches that has caused multiple

input signals in one signal switch throw; there will always be a need for a SR latch in the circuit

to stop it from debouncing. Applications that involve a bouncing circuit turn on a lamp or start a

fan motor.

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Experiment 3:

A circuit was constructed showed in figure 12. Again, the process to design this

circuit was: 1) truth tables- a collection of tables and numbers that output either 1 for on or 0 for

off showed in table 8, 2) K-maps- a way to simplify the main equation showed in tables 9 to 15,

3) logic gate circuit- a way to display the results for the design showed in figure 13. From the

design that was made for the BCD to seven-segment decoder, a 7447 (BCD to seven-segment

decoder driver) was used.

Figure 13: Logic Gates for the Seven Segment Display circuit

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Table 18: K map for a

Table 19: K map for b

BA\CD 00 01 11 10

BA\CD 00 01 11 10

00 1 0 x 1

00 1 1 X 1

01 0 1 x 1

01 1 0 X 1

11 1 1 x x

11 1 1 X x

10 1 1 x x

10 1 0 X x

Table 21: K map for d

Table 22: K map for e

BA\CD 00 01 11 10

BA\CD 00 01 11 10

00 1 0 x 1

00 1 0 X 1

01 0 1 x 1

01 0 0 X 0

11 1 0 x x

11 0 0 X x

10 1 1 x x

10 1 0 X x

As, a revised k-maps were done, as showed in tables 18 to 24, these tables resulted in

boolean equations. The following are the boolean equations from the k maps.

a= CA+B+D+ b= D+ BA+ c= A+C+

d= D+ +

e=

f=

g= D+

Table 20: K map for c

BA\CD 00 01 11 10

00 1 1 x 1

01 1 1 x 1

11 1 1 x x

10 0 1 x x

Table 23: K map for f

BA\CD 00 01 11 10

00 1 1 x 1

01 0 1 x 1

11 0 0 x x

10 0 1 x x

Table 24: K map for g

BA\CD 00 01 11 10

00 0 1 X 1

01 0 1 X 1

11 1 0 X x

10 1 1 X x

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From the circuit made in this experiment, the circuit counted in binary numbers from 0 to

9. As the circuit got to 10 and above binary numbers, the circuit had some weird shapes on the

seven segment display. The binary shapes and numbers are showed in table 25. The letters from

the table are the outputs that lit up when the binary number was inputted.

Table 25: Seven Segment Display Results

# input output

0 0000 0000

1 0001 0001

2 0010 0010

3 0011 0011

4 0100 0100

5 0101 0101

6 0110 0110

7 0111 0111

8 1000 1000

9 1001 1001

10 1010 g e d

11 1011 g d c

12 1100 f b g

13 1101 a f g d

14 1110 f g d e

15 1111 no output

When using the 7447, a BCD decoder, with the seven segment display, the 7447 chip has

taken the circuit in figure 13. This decoder had taken in a binary value from 0 to 9 and output

decoded values from a to g. For example, to output the light a on the seven segment display, the

values are shown in table 8. There for the circuit was counting from 0 to 9 from binary numbers.

From experiment 2, the circuit needed a SR latch to make sure that the count does not bounce

from number to number or skipping values. Comparing experiment 2 to 3, the 7447 chip did not

bounce at all, whereas the 7416 chip did bounce from binary number to binary number.

As shown in figure 12 a few changes were made to the diagram. First of all, the seven

segment display had only 10 pins on it. There pins 2, 3,4,5,8 and 9 were as follows pin 2 was “ f

”, pin 3 was “ g “ pin 4 was “ e “, pin 5 was” d “, pin 8 was “ c “, pin 9 was “ b “ and pin 10 was

“ a”. The other pins are as follows pin 1 was “a positive 5 voltages “, pin 6 was “a positive 5

volts “and pin 7 was DP. Pin seven was not used because there was no need in connecting

another seven segment display to the circuit. This pin if connected would light up if there was

another seven segment display the DP light would be light up. Since this circuit was connected

with positive 5 volts or VCC to the led’s on the seven segment display the circuit was called

common anode. If the circuit was connected to ground, it would be called common cathode.

As a result form the experiment the seven segment display counted in binary from 0 to 9.

Once the binary number got above 1001 binary number the circuit started to display different

segments. One way to resolved this was to set the clock pulse to reset once the circuit reached

1001 binary value or set another seven segment display to its clock pulse so the reading on both

segments would read 10.

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Experiment 4:

From experiment 4, a circuit was constructed in figure 14. There was a need to have one

inverter gate (7404), one nand gate (7400), two or gate (7432), three and gate (7421), and two J-

K flip flops (7478), with one dip switch, four led’s. The inverter, nand, or, and gates are in table

1 for the inverter gate, table 2 for the or gate, table 5 for the nand gate, table 5 for the and gate.

In table 26 and figure 15 shows how a J-K flip flop was construct inside the chip of 7478 and the

table shows the truth table the J-K flip flop.

Figure 15: J-K Flip Flop

Table 26: Truth table for the J-K Flip Flop

J K C S R Q

X X 0 X X X Q

0 0 X 0 0 X Q

0 1 1 0 1 X 0

1 0 1 1 0 X 1

1 1 1 Q Q

When making this circuit showed in figure 14, a excitation table and the state transition

table. A excitation table shows the inputs that were necessary to generate a particular next state

in the circuit. A state transition table shows the present state, next state and the output for the

state giving. Tables 27 and 28 are the excitation and state transition table.

Table: 27 Excitation state for a J-K Flip Flop

Q J K

0 0 0 X

0 1 1 X

1 0 X 1

1 1 X 0

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Table 28: Transition state for the J-K Flip Flop

Present State Next State Outputs

QD QC QB QA QD QC QB QA TD TC TB TA

0 0 0 0 0 0 0 1 0 0 0 1

0 0 0 1 0 0 1 0 0 0 1 1

0 0 1 0 0 0 1 1 0 0 0 1

0 0 1 1 0 1 0 0 0 1 1 1

0 1 0 0 0 1 0 1 0 0 0 1

0 1 0 1 0 1 1 0 0 0 1 1

0 1 1 0 0 1 1 1 0 0 0 1

0 1 1 1 1 0 0 0 1 1 1 1

1 0 0 0 1 0 0 1 0 0 0 1

1 0 0 1 1 0 1 0 0 0 1 1

1 0 1 0 1 0 1 1 0 0 0 1

1 0 1 1 1 1 0 0 0 1 1 1

1 1 0 0 1 1 0 1 0 0 0 1

1 1 0 1 1 1 1 0 0 0 1 1

1 1 1 0 1 1 1 1 0 0 0 1

1 1 1 1 0 0 0 0 1 1 1 1

The second part of this experiment was to construct the same circuit with a 74191 chip.

What this chip does was the exact same thing as the circuit in figure 14 does but in a smaller

form. The 74191 chip was connected to the function generator with a frequency of 1 Hz,

amplitude at 2.5, count off at 0 and the function set to square. From constructing this circuit with

the 74191 chip was a bit slower than the overall circuit made in part one of the experiment

numbers 4. Both the circuit was made from all of the and, nand, or, inverter gates, J-K flip flop

and the 74191 chip both count from 0 to 15 in binary. Once the circuit has reached 1111 binary

number or 15 the circuit started itself over. Once the circuit got to the last binary number 1111 or

15, the circuit reset itself due to the logic from the circuit made, showed in tables 29 to 32. This

happen by putting the load to logical 1or high, connected to a voltage source, and each Q was

connected with this load to a nand gate. Then when the output was high the preset was engage

and will reset the J-K flip flop to logical 0.

From distinguishing experiment 4 between experiments 2 and 3, the overall circuit did

not bounce because of the circuit made of the J-K flip flops, preset and clear of the flip flops.

The design from the flip flop were design so that when the circuit would start to bounce there

was a feedback logic from the outputs of Q and were connected back into the circuit of J and

K. When the J and K were connected to the feedback logic, this told the circuit that something

was going on and needs to change, so the circuit from the and gate will only output 1 if both of

the input of K or J was 1 and if the feedback logic was 1 from Q and .

In experiment 3, the circuit was design to count from a binary input to an output of 0 to 9.

Once this circuit got to certain point in the circuit, anything above 9, the circuit started to have

different outputs showed on the seven segment display. From experiment 4, this counting circuit

was counting in binary from 0 to 15. As showed the circuit did not do anything different as found

in experiment 3, experiment 4 counting from 0 to 15 with no problems.

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Table 29: K-Map for TA and TB

QDQC\QBQA 000 001 011 010 110 111 101 100

00 0 0 0 0 1 1 1 1

01 1 1 1 1 0 0 0 0

11 1 1 1 1 0 0 0 0

10 0 0 0 0 1 1 1 1

Table 30: K-map for TC

QDQC\QBQA 000 001 011 010 110 111 101 100

00 0 0 0 0 1 1 1 1

01 0 0 0 0 0 0 0 0

11 1 1 1 1 0 0 0 0

10 0 0 0 0 0 0 0 0

Table 31: K-map for TD

Q3Q2\Q1Q0 000 001 011 010 110 111 101 100

00 0 0 0 0 1 0 0 1

01 0 0 0 0 0 0 0

11 0 1 1 0 0 0 0 0

10 0 0 0 0 0 0 0 0

TA=1

TB=QA+ TC=QBQA+

TD=QCQBQA+

Table: 32 Truth table for the Clear and Preset values

LD A CLR PRE

0 0 1 1

0 1 1 1

1 0 0 1

1 1 1 0

CLR= +A

Pre=

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Figure 14:Counting Circuit

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List of Attachments:

Original Data sheet

Conclusion:

Experiment 2:

In conclusion, from the switch debouncing circuit, the problem involved changing

circuit the 74161 counter so it would not bounce. The answer to this question was put a SR latch

connected to the 74161 as a clock input. Found from the data above the SR latch made the 74161

counter to increment by 1 from the set state. This made the circuit from bouncing one binary

number to the next.

Experiment 3:

In conclusion, from the seven segment display, the problem started when the

display counted anything above the binary number 1001. Once this happened the seven segment

decoder displayed different outputs. As a result to solve this problem the seven segment decoder

need to be connected in another way to continue the counting in binary. Found from the data the

seven segment decoder was connected with another seven segment display with the clock plus

connected to reach other or there was a need to reset the clock pulse once the counter reached a

binary number of 1001.

Experiment 4:

In conclusion from construction of the counting circuit was found when both

circuits the 74191 chip and circuit from figure 14 did indeed count in binary from 0 to 15.

Differences between these two circuit was found that the 74191 chip was a lot easier and faster

to construct but the 74191 chip did not move as fast as the circuit built in figure 14. From the

circuit built in figure 14, this circuit took long to build and to debug but overall more efficient

than the chip 74191.

References: [2] Switch Debouncing

[3] Seven Segment Decoder

[4] Counting Circuits

This report was submitted in compliance with the UNCC Code of Student Academic Integrity

(1997-99 UNCC Catalog, p 336) ____ECM___. (Student’s Initials)