Switched Capacitor DC-DC Converters: Topologies and Applications

Bill Tsang and Eddie Ng

Outline

MotivationsDickson’s Charge PumpOther Various Charge PumpsApplicationsConclusion

Motivations

InductorlessOn-chip integrationLow costHigh switching frequencyEasy to implement (open-loop system) Fast transient but large rippleHigh efficiency but limited output power

Ideal Dickson’s Charge Pump(Phase 1)

clk_bar

VDD Vo

C1 C2 C3

clk

VDD-Vt

2VDD-VtVDD

0

VDD

• Clk=0, Clk_bar=VDD• Finite diode voltage drops, Vt

VDD-Vt

VDD-Vt

Ideal Dickson’s Charge Pump(Phase 2)

clk_bar

VDD Vo

C1 C2 C3

clk

VDD-Vt2VDD-2Vt

2VDD-Vt3VDD-2Vt

VDD

VDD

0

• Clk=VDD, Clk_bar=0• Maximum voltage stress on diodes 2VDD-Vt => reliability issue• Maximum voltage stress on capacitors VCn =n(VDD-Vt) => reliability issue

VDD-Vt

Dickson’s Charge Pump

)( p

o

p CCf

I

CC

CVV

thVV

clk_bar

VDD Vo

V1

V1+dV1

V2

V2+dV2

C1 C2 C3Cp Cp Cp

clk

v1 v2

ttDDout VVVNVV )(*

thVV

C1=C2=C3=C

(Body effect can be significant at later stages)

Non-idealitiesThreshold voltage drop [Mos charge pumps for low-voltage

operation]

Parasitic capacitor divider voltage drop Low conversion efficiency and pumping gain Limited maximum number of stages

FFBSthoth 2φ2φVγVV

F

2

FthoDD

out,max 2φ2φγ

VVV

)( 2122 VVVVVG tnV

[An on-chip High-voltage generator circuit for

EEPROMs with a power supply voltage below 2V]

Modified Switch

VDD

clk

MD1

MS1

2VDD

VDD

clk

MD1

CTS

•Static Charge Transfer Switches (CTS)•Eliminate transistor threshold drop

Modified Dickson’s Charge Pump #1 (NCP-1)

)(*2 1VVV tn

)(*2 2VVV tn

VDD Vo

C1 C2 C3Cp Cp Cp

clk

clk_bar

C4 C5

Cp

MD1 MD2 MD3 MD4

MS1 MS2 MS3 MS4

dV

dV

dV

Cp

v1 v2 v3

v1

V2

v3

To turn on transistor Ms2; Vgs = 2V

Conditions:

1, Clk=Vdd,Clk_bar=0: v2, v3+V

2, Clk=0,Clk_bar=VDD: v1, v2+V,v3

To turn off transistor Ms2; Vgs = 2V impossible

Modified Dickson’s Charge Pump #1 (NCP-1)

Static Charge Transfer Switches (CTS)Better voltage pumping gain than diodes

Lower voltage equals upper voltage of pervious stage Utilizing higher voltage from following stage to drive CTS Reverse charge sharing since CTS cannot turn off completely

VVVGV 122

Modified Switch #2

clk

MD1

MS1

• Eliminate transistor threshold drop• Complete turn-off of switch, MS1

Next stage

MP1MN1

MP1 used to turn on MS1MN1 used to turn off MS1

Modified Dickson’s Charge Pump #2 (NCP-2)

tpVV *2 )(*2 2VVV tn

C1 C2 C3Cp Cp Cp

clk

clk_bar

MD1 MD2 MD3

MS1 MS2 MS3

dV

dV

dV

MP2MN2

v1 v2 v3

)(*2 1VVV tn

To turn on transistor MP2 and MS2; Vgs = 2V

Conditions:

1, Clk=Vdd,Clk_bar=0: v2, v3+V

2, Clk=0,Clk_bar=VDD: v1, v2+V,v3

To turn on transistor MN2 and turn off MS2; Vgs = 2V

Complete Circuit(NCP-2)

Vo

C1 C2 C3Cp Cp Cp

clk

clk_bar

q

C4 C5

Cp

MD1 MD2 MD3 MD4

MS1 MS2 MS3 MS4

dV

dV

dV

Cp

MP2MN2

v1 v2 v3

•Careful PMOS well connection to prevent latch-up

•Diode-connected output stage used

Modified Dickson’s Charge Pump #3 (NCP-3)NCP-3 uses boosted clock at output

stage

ViVo

C1 C2 C3Cp Cp Cp

clk

clk_bar

q

C4

C5

Cp

MD1MD2 MD3 MD4

MS1 MS2 MS3 MS4

dV

dV

dV

HVClock

Generator

clk

Converters Output Voltage Results

Optimum Capacitance Selection

)( pi

out

pi

iDD CCf

I

CC

CVV

VNVV DDout *

i

outDDi

DDoutpiitot C

fIVC

VVCCCNC

/*

)(/

/22 DDout

outDDi

DDpiioutDDipi

i

tot VVfIVC

VCCCfIVCCC

C

C

fV

IC

fV

I

fV

IC

DD

outp

DD

out

DD

outi

2

min,

[A Low-Ripple Switched-Capacitor DC-DC Up converter for Low-voltage applications]

Efficiency and Output Impedance

Power loss due to: Vth, Rds(on), ESR, Cp, etc

Efficiency estimation

Output impedance (slow switching)

in

out

VM

V

*

[Performance limits of switched-capacitor DC-DC Converter]

[Performance limits of switched-capacitor DC-DC Converter]

fCTq

VR

s

outo

1

/

M=ideal conversion ratio

q=charge supplied to the source Vout

Ts=switching periodi= parasitic time constant

si T

Cross-Coupled Charge Pump

1

1

1

LL

L

o

RsCsC

I

V

[Area-efficient CMOS Charge Pumps for LCD Drivers]

)(

2

ondsL

Lddo RR

RVV

LL

Lripple CCCf

IV

1

11

2

M10 M9

phi1phi2

CL1

VDD

Vo

RLC1 C2

• PMOS to transmit 2VDD to output

• Bodies tied to source(highest voltage) to avoid forward biasing junction diodes

H-bridge Topology

Commercial products (Linear Technology, Fairchild, Maxim …)Buck or Boost functionsNegative voltage generation

1

3

Oscillator and Control

2

4

H-bridge Topologies

1

3

2

4

phi1

phi2

phi1

phi2

Vin Vout

Vin

inverter

1

3

2

4

phi1

phi2

phi1

phi2

Vin

Vout

Vin

doubler

4

Vout

1

3

2

phi1

phi2

phi1

phi2

Splitter

Vin

Vout = -Vin

Vout = 2Vin

Vout = 0.5 Vin

Phase 1: transistors in red are on

Phase 2: transistors in blue are on

Application (1): Flash Memory

Floating gate programmingControl gate voltage >> Vdd

[ee141 lecture]

Application (1): Flash Memory

Nominal VDD= 5V

Application (2): Sample Switches

S/H circuit– constant vgs sampling with all input level Reduces distortionReduces Rds(on)

Phi_bar

VSS

C1 C2

Vin

Vo

M1

M2

M3

M4M5

M6

M7

M8

M9

M10 M9

Phi

Phi_bar

VDD

M11

C3

A

Vo+

Vo-

Ci

CL

OTA

+

-

-

+

Ci

CL

Cs

vicm

Cs

vicm

phi1

phi1d

phi1d

Vi+

Vi-

phi1

vicm

phi2d

phi2d

vicm

phi2

phi2

Voltage doubler

Application (3): Low voltage Amplifier

Positive zero in Miller compensation1/gm pole-zero cancellation [charge-pump

assisted low-power/low-voltage CMOS Opamp Design]

V-

Charge pump

VDD

V+>2VGS

Conclusion

Different Dickson’s SC converters discussedOptimal Capacitor size selection Discussion of cross-coupled doublers Commercial product: Full H-bridge Applications: Flash, ADC, Amplifier, LCD driver