syde 192 digital systems - university of waterlootnaqvi/downloads/doc/sd192/2010labs.pdf · syde...

SD 192 - Digital SystemsContents

SECTION APPENDICES DESCRIPTION

1 AB Lab 1 – Introduction

2 C Lab 2 – B2-Logic Circuit Simulation

3 AD Lab 3 – Adders and Multiplexors from Gates

4 AD Lab 4 – Wiring of multiplexors

5 EF Lab 5 – Using programmable gate arrays

6 C Lab 6 – Sequential Circuits: Flipflops

7 Lab 7 – FSM using Xilinx StateCAD

8 FG Lab 8 – Advanced sequential circuit lab

A Digital Interface Board

B Your Digital Systems Kit

C Summary of B2-Logic

D Speedwire Prototype Board

E FPGA Module Summary

F Programming the FPGA

G PIC Module Summary

WWW StateCAD Tutorial

WWW Sample PIC files

WWW PIC chip documentation files

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SD 192 - Digital SystemsLab Page http://eng.uwaterloo.ca/∼tnaqvi/courses/syde192.html

Newsgroup uw.syde.syde192

Introduction:

The digital circuits laboratory of SD 192 – Digital Systems is a crucial element of the course.It is almost impossible to acquire a meaningful knowledge of digital circuits and circuit designwithout having to sit down and wire up a set of chips. The eight laboratory sessions which youwill attend this summer have been carefully designed to exercise all aspects of the theory learnedin the classroom, and to give you practical experience which may be of tremendous use in futurework-terms.

The labs get reorganized every year; feedback from students is crucial in keeping the labs interest-ing, manageable, and pertinent. You are encouraged to talk to the professor, to the lab instructor,or to the TAs. The labs will operate as follows:

• The labs will be done in groups of two, preferably three students.

• Each group will be assigned one three-hour laboratory period per week sometime Tuesday. . . Friday afternoons. Monday afternoons and every morning the lab space is available forgroups to come and test their designs and to do circuit simulations.

• It is imperative that you have circuit designs prepared and most wiring or programmingcompleted before coming to the lab — the three hour lab period will not be sufficient tocomplete the lab exercise without some preparation. A TA will be present during the labperiod to help you troubleshoot your circuits.

• Unless there is a justifiable reason for an absence, it is expected that each member of a labgroup be present during each lab period.

The labs are a significant part of the course, and therefore represent a substantial portion of thecourse grade. Your grade in the labs is based on three factors:

1. Normally each lab will specify certain results / circuits which you are to demonstrate to oneof the lab TAs. The TA will keep a list of groups which have successfully demonstrated theircircuits; it is your responsibility to show your circuit to the TA and to make sure that you arechecked off on this list during your lab period.

2. To encourage good engineering practice, each group is required to maintain a proper, hard-cover laboratory book. This book is meant to contain all of your notes, circuits, pin-outs,sketches, wiring diagrams, equations, Karnaugh maps, or computer code that you will needfor the lab. Furthermore any ideas / changes which you discover during the lab period shouldbe written into the book.

The lab book is not meant to be neat or completely correct — the lab report fulfills that role.This is a “work in progress” kind of book, where you make mistakes and develop your ideas.

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More information on how to maintain a good lab book is contained in the departmental styleguide.

At the beginning of each lab you will need to show your book to the TA, who will check itfor completeness. Do not bring circuits to the lab sketched on scrap paper.

3. There will be one laboratory report required per group. The laboratory report is due oneweek after your lab period; that is, if you’re assigned a Wednesday lab slot then your reportis due on the Wednesday one week later. Lab reports should be placed in the appropriate slotin the assignment box in the E2 corridor.

A formal report is expected for the laboratory writeup; that is, your report should containeach of the following:

• Introduction / Problem summary

• Discussion of circuit design and expected results

• Circuit schematic and a sketch of the speedwire board layout

• Circuit testing / problems encountered / successive design changes etc.

• Summary / Conclusions

Handwritten reports are fine, but should be neat. Figures and tables should be properly la-belled; unless you are particularly good at doing figures and tables with your word-processor,I suggest that you draw circuits, Karnaugh maps etc. by hand.

I am not interested in long labs. Frequently students spend far too much time writing longlab reports. Explain things that need to be explained, but do so efficiently and tersely.

Marks will be deducted for poorly organised reports and for poor grammar and writing style.Some point form is fine; not everything needs to be written out in prose.

The lab exercises try to thread a reasonable balance between theoretical knowledge and practicalmethods used in industry; you will be encountering a lot of different digital circuits and implemen-tation techniques:

• Hand wiring of basic chips and chips of intermediate complexity

• Use of memory arrays (EPROMs) for circuit design

• Use of programmable logic arrays and microcontrollers

• Use of digital circuit simulators

This is a lot of material! The goal is not to become an expert at all of this, rather to acquire afamiliarity with a broad set of ideas and tools.

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Lab 1 – Laboratory Instruments and your Prototype Board:

This lab is intended to familiarize you with the basic equipment used in analogue and digitalcircuits laboratories. The lab will also familiarize you with wiring the speedwire prototype board,the digital interface board, and the digital logic probe; a thorough understanding of these will beof great benefit to you in later labs!

Exercise 1 – Laboratory Instruments

The Oscilloscope is an important tool which visually displays voltage as a function of time. Theinstrument can show pulses shorter than one microsecond (10−6s), although most of thesignals in this course will be in the millisecond range.

There are two Tektronix oscilloscopes at each lab station – an older analogue one and anewer digital one; each of these instruments has pros and cons. Be careful — these are veryexpensive pieces of equipment.

The Power Supply supplies a stable DC voltage to a circuit. The knobs on the front of the supplyset the output voltage and the current limit (maintaining a small current limit can help you toavoid accidentally destroying a circuit).

The Function Generator produces a time-varying voltage. The output signal is weak and ismeant to be a measured input, not to actually power a circuit. The function generator canprovide sinusoidal, square, and triangular waveforms.

A manual for each instrument can be found at the lab station. These manuals must remain in thelab.

Do the following steps; in your lab book, record your answers to the questions which are askedbelow:

1. Take the probe which is already connected to the oscilloscope and clip it to the calibration ter-minal (labelled “Probe Compensation” or “Calibration”). What is the shape of the calibrationsignal? What is the amplitude and frequency of the calibration signal?

2. Find the LEADER function generator and turn it on. Set the function generator to produce a10kHz sine-wave.

3. Now clip the oscilloscope probe to the function generator output. Accurately measure thefrequency and signal amplitude. By how much does the waveform differ from the 10kHzsetting on the function generator dial?

4. Increase the frequency of the function generator while watching the oscilloscope output.What happens at very high frequencies? What is the highest frequency that the functiongenerator can produce?

Try the other settings of the function generator; e.g., triangle waves, square waves etc.

Exercise 2 – The Prototype Board

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244

244

Input from Switchto Your Circuit

Output from yourCircuit to Display

Speedwire BoardInterface Board

0V

5V

0V

Light

Switch

Figure 1: The role of buffers on the speedwire board; essentially to act as intermediaries between yourcircuit and the interface board.

1. You should read Appendix A, D before coming to the lab. If you haven’t read these appen-dices, read them now before proceeding. In particular, make sure you understand how toproperly wire the speedwire board; using an improper technique can lead to poor contactsand / or damaged pins.

You will find the functionality and pin assignments of the relevant digital devices in theTTL data book, the sheets posted in the lab, or on the lab instructor’s home page. Lookup the 74LS244 octal buffer and understand its functionality and pin assignments beforeproceeding! Also remember that data sheets show the top view of the chip, whereas you’rewiring on the bottom; I recommend that you always draw the chip pinouts for the bottomview before you try to wire a circuit. You should sketch the top and/or bottom pinouts, withthe purpose of each pin labeled, in your lab book.

We will be connecting two buffers today as sketched in the figure: one buffer accepts switchinputs to the speedwire board, and the other returns outputs from the board. These two bufferswill remain on your board for the next couple of labs, so it will be worth your while to do acareful job of wiring. Appendix D lists the pin assignments on the connector for the switchinputs and signal outputs. You might want to photocopy that page and paste it into your labbook to have it for convenient reference.

Anti-static wrist-straps are provided at each lab station. As a matter of good practice, studentsshould wear a wrist strap whenever handling integrated circuits, as they can be damaged bystatic electricity.

2. Start by identifying two sockets on the speedwire board which lie close to the ribbon-cableconnector, and which can hold the 20-pin 74LS244 chips.

Connect the eight switch inputs from the ribbon cable (pins 17–24) to the inputs of the firstLS244 buffer; similarly connect the eight outputs of the second LS244 buffer to the eightsignal outputs on the ribbon cable (pins 1–8). You will also need to make two power-supplyconnections for each chip. Finally each of the buffers has two control lines which determinewhether the buffer outputs are active or disabled. We always want the buffer to be active, sothe two control lines (chip pins 1 & 19) need to be set low (i.e., to ground).

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3. Once you have completed the above wiring (always carefully doublecheck your power andground connections to make sure that they were done properly) you are ready to test yourcircuit.

Connect the prototype board to the “Digital Interface Module” (Appendix C) using the ribboncable in your kit. In your kit you will also find a 9V power supply; attach the flat connectorthe interface module (not to the speedwire board).

Set the eight switches on the interface board to 1001 0110. Using the logic probe from yourkit, test each of the outputs of the buffer on the prototype board and verify that they have thecorrect values. Demonstrate your successful test to the TA.

Repeat the test with all of the switches in the opposite positions, e.g., set the switches to 01101001. Again use the logic probe to check the buffer outputs.

No report is required for this lab, however it would be a good idea to write some notes onhow to use the instruments.

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Lab 2 – B2-Logic Circuit Simulation Software.

This lab is intended to familiarize you with digital circuit simulation in general, and with the theB2-Logic circuit simulation software which we have purchased for the lab (and which you willbe using throughout the semester). The software is quite powerful, capable of simulating RAMS,EPROMS, and programmable logic devices in addition to the more usual, basic circuit components.An introduction to this software is provided in Appendix C.

Save any files which you create in the working directory D:\workdir\your_directory.Please note that there is no security on the lab computers – other people may delete, overwrite, ormodify your files. Always back up your files on floppy.

Exercise 1 - Combinational Logic

We’ll start with a relatively simple circuit. The following figure characterises the input/output be-haviour of a digital circuit:

p0 = a0 . b0

p1 = (a0 . b1) . (b0 . a1) + (a0 . b1) . (b0 . a1)

p2 = (a0 . b0) . (a1 . b1)

p3 = (a1 . b1) . (a0 . b0)

a0a1

p0p1p2p3

b0b1

Construct a digital circuit, using one- and two-input gates only, that satisfies this input/outputrelationship. You should try to use as few gates as possible. (You should think about this beforecoming to the lab, and should have the circuit designed and drawn in your lab book.)

1. Construct the circuit using the B2-Logic software. Use two-bit input devices and 1 → 2 busdevices to generate the inputs a and b. The four circuit outputs are most easily viewed on asingle B2-Logic output-probe connected to a 4 → 1 bus device.

2. Write down the truth-table for this circuit.

3. Simulate the circuit (single-stepping is easiest; use the buttons in the upper-right of thescreen), and make sure that your circuit outputs match the entries in your truth-table.

4. By looking at the truth table, figure out what the circuit is doing and describe its functionality.

Exercise 2 - Sequential Logic

Construct the following circuit (each rectangular box is a 74x73 JK-FlipFlop, which you’ll find inthe list of devices on the right hand side of the B2-Logic screen):

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Q Q

J KR

C

Q Q

J KR

C

Q Q

J KR

C

Q Q

J KR

C

Q0 Q1 Q2 Q3

Pulse / Clock

VCC

74x73 74x73 74x73 74x73

1. Construct the circuit using the B2-Logic software.

2. Apply a sequence of pulses to the pulse-input of the circuit. Watch the outputs (Q0, Q1, Q2,Q3); what is the circuit doing?

Attach a fast clock (100ns period) to the pulse input and simulate the circuit; what happensto the outputs? Show the results of a successful simulation to the lab TA. Note: to com-press or stretch the simulation output window (the default is much too wide) go to menuOutput/Customize Trace and set the “Trace Interval” to a larger number; I suggest about2000.

3. Now connect this second circuit to the one which you created in Exercise 1:Q0⇒ a0Q1⇒ a1Q2⇒ b0Q3⇒ b1

Connect a clock to the pulse input and simulate the combined circuit. Look at the outputs(p0, . . ., p3). What is the overall circuit doing?

Report

Produce a report which describes, in detail, the various steps which you took and your observations.Include schematics of the circuits which you produce; the B2-Logic program can output postscriptfiles of circuits etc.

Make sure that you answer / address all of the questions which are posed in the lab exercises.

The reports (one per group) are due one week after your lab session in the SD192 slot in the boxin the E2 hallway.

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Lab 3 - Combinational Circuits: Adders and Multiplexers

The primary goal of this lab is for you to construct a relatively complicated circuit, forcing you tolearn good habits of device layout, planning, and circuit debugging.

Week four of the semester has no scheduled lab; Lab 3 will formally take place the following week.Although no TA will be present, the lab will be open all afternoons during week four, and I wouldstrongly recommend that you come in some afternoon to design and simulate your circuit, leavingthe following week for debugging and demonstrating your constructed circuit to the TAs.

You will be connecting on the order of 12 chips for this lab. With careful planning the wiringshould be straightforward; if you don’t plan ahead you will spend many hours debugging yourcircuit. The essential idea is to be very systematic about circuit design – prepare neat diagrams ofyour chips and their connections viewed from the wiring (bottom) side of the board.

The digital circuits which you will be building are a two-bit full adder, and two four-input multi-plexers. You are permitted to use only the following basic gates: AND, OR, NAND, NOR, NOT;do not use XOR.

There are four signals of interest associated with your adder:

Input A to the adder (values 0 to 3)Input B to the adder (values 0 to 3)The carry input to the adder (values 0 to 1)The output from the adder including the carry (values 0 to 7)

Your task is to use the two multiplexors so that the user (by controlling a couple of switches on theinterface module) can have any one of these four signals sent to the Interface Module and displayedon three outputs.

1. Interface

Start by defining the inputs and outputs. You’ll need inputs to the adder, a carry, control linesfrom the user, and the output lines. Prepare a table which shows which inputs and outputs dowhat (i.e., if someone else wanted to use your circuit, document for them how to use it). Inother words, if someone sat down at your lab station, they wouldn’t know what SW8 does;prepare a table that shows which switches provide which input, and which LEDs show whichoutput.

2. Design

The two-bit full adder takes two 2-bit inputs A,B and a 1-bit input carry Cin to produce a 3-bit output sum. The adder is an extension of the one-bit half adder; in particular, the two-bitfull adder can be constructed by cascading together a few one-bit adders. You will need toprepare some sort of truth table and a detailed circuit diagram.

The four-bit multiplexers are an extension of the two-bit multiplexers which we discussedin class. Each of these multiplexers will provide one of the output bits. However the outputfrom the adder is three bits wide, so you’ll have to include a little bit of multiplexer-like

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Sum

Carry Out

Addend

Carry In

One−Bit Half Adder

Input 1

Input 2

Select

Output

Two−Bit Multiplexor

circuitry to produce the third bit (the output carry) when required. You will need to preparea detailed circuit diagram.

Remember that for both of these circuits you are limited to using the following five basicgates: AND, OR, NAND, NOR, NOT.

3. Simulation

Simulate your circuit before you commit yourself to constructing it. During the formal labperiod, show a successful simulation of your circuit to the lab TA. Include schematics as partof your report.

4. Hardware

Construct the circuit which you designed on your speedwire board, using only the permittedgates. Demonstrate your circuit to the lab TA.

5. Report

Include in your report a description of the design and a discussion of any problems encoun-tered. Also include circuit diagrams and simulations from B2-Logic.

Briefly discuss the following:

• How would you extend your adder to be a general n-bit full adder. Does a modulardesign approach make this straightforward?

• To what extent would your circuit be simplified if we allowed you to use XOR gates?Draw (sketch by hand) a circuit for a two-bit full adder, using as few gates as possible,but where XOR gates are permitted.

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Lab 4 - Multiplexer Design of Combinational Circuits

In Lab 3 I had you design and construct a relatively complicated circuit using only very basic two-input gates. If nothing else, it should be quite clear to you that this would be a very tedious way todesign more complicated circuits (that is, pretty well any circuit that does anything interesting).

In class we saw how we could develop a Karnaugh map for a combinational problem. We alsosaw how we could implement combinational circuits using multiplexers. We’ll explore this latterapproach to combinational circuit design in this lab.

For this lab you will be constructing a voting system for the next summer Olympics. There arefour judges, one from each of four countries, and since life isn’t fair the judges’ decisions are notweighted equally:

American Judge 1 VoteCuban Judge 2 VotesLibyan Judge 3 VotesCanadian Judge 4 Votes

Come to think of it, that looks pretty fair to me.

Each judge has a switch (on your Digital Interface Module) which they will use to vote; if theswitch is ’Off’ then the judge is putting all their votes towards contestant A, and if the switch is’On’ then the judge is casting votes for contestant B. With a total of ten votes to be cast, the resultsare determined as follows:

Sum of Votes for B Decision0 — 4 Contestant A

5 Tie6 — 10 Contestant B

Design a circuit that accepts the four switch inputs from the judges and which produces the fol-lowing three outputs: one which goes high if contestant A is selected, one for a tie, and one forcontestant B. Note that the outputs are mutually exclusive – only one of the three outputs can everbe high.

1. Interface

Start by defining all of the inputs and outputs. You’ll need inputs from the judges, and outputsfor the decisions. Prepare a table which shows which inputs and outputs do which operation.

2. Design

Use three 74x151 eight-input multiplexers to implement the circuit. Use as few other com-ponents as possible. Design and sketch the circuit in your lab book.

3. Simulation

We do not require a formal simulation for this lab, however you are encouraged to simulateyour circuit to demonstrate its correctness. B2-Logic contains the 74x151 multiplexer as partof its component list, so entering your circuit should be very easy.

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4. Hardware

Implement your circuit on the speedwire board. Demonstrate the successful operation ofyour circuit to the lab TA. You should have some test cases (ie, switch settings) preparedahead of time in your lab book which you believe will do a good job of testing your circuit.

5. Report

Prepare a report with boolean expressions, circuit diagrams, design iterations etc.

• We could have done this lab by preparing a Karnaugh map for each output and imple-menting the circuit using gates. Write down the Karnaugh maps and sketch (by hand isfine) the resulting circuit.Discuss the use of multiplexers in combinational circuit design (discuss advantages /disadvantages). How difficult did you find this lab compared to lab 3?

• Suppose I only gave you a bunch of 4-1 multiplexers instead of 8-1. How could youconstruct an 8-1 using 4-1 multiplexers (sketch a circuit diagram).

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Lab 5 -Combinatorial Circuits: Programmable Devices

Whereas Lab 3 forced you to tediously build a circuit from the gate level, and Lab 4 allowed you to step back to the multiplexer level to build circuits more conveniently, in this lab we take circuit design and construction to the limit using a software-programmable device requiring no wiring.

The primary goal of this lab is for you to learn the basics of a logic programming language and to get used to programming software. Later in the term (in Lab 8) you will have the opportunity to build a much more sophisticated and interesting digital controller using this same programmable device.

There are three appendices relevant to this lab:

# Appendix A - figure A-3 Xilinx Spartan 3 Board

# Appendix E -the Xilinx FPGA module

# Appendix F -the Xilinx ISE program and Verilog programming language

The basic steps to realizing any digital circuit using the Xilinx Spartan3 XC3S200 and XC3S400 programmable device are as follows:

1. Read Tutorial#1 and Tutorial #2 (most easily available from the course lab page). These tutoria ls contains step by step guide to program Xilinx Board. Tutorial #1 contains Schematic example and Tutorial #2 contains Verilog example.

2. Write down a concise definition (e.g., truth table or Boolean equations) of the logic to be realized.

3. Using the information in Tutorial #2, write a Verilog code; Use pin definitions from Appendix E to create user constraints file (.UCF). By default, all files containing Verilog code should end in ’.v’ extension.

4. Use Appendix F and your text book by M.Morris Mano for programming syntax reference.

5. Once your bit file is generated successfully you can download the circuit to the FPGA using Xilinx tool called iMPACT. (You don’t have to erase or reset the FPGA in order to download a new circuit.)

6. Test your circuit using the digital interface module. All the steps can be done before coming for your lab session Xilinx software for educational use is available free from the xilinx.com website. The actual loading of your circuit into the FPGA and demonstrating the successful circuit operation to the TA will take place during your lab afternoon.

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It is strongly recommended that you keep all of your files on a personal disk, since files on the hard- disks in the lab may be deleted / overwritten by other lab users. However to speed things up while you’re in the lab, you probably want to put files on the hard disk (use working directory D:\workdir\your_dir ectory).

Although you can simulate your design using Xilinx software, we will not cover the simulation part in the lab, however a detail guide is available form xilinx page for your information. You aren’t required to do simulations.

Part I: We’ll start with a very simple set of Boolean equations to give you a little experience with the Verilog language.

Implement the Boolean expressions of Lab 2, Exercise 1, connecting the circuit inputs and outputs to appropriate FPGA inputs / outputs.

Show the successful operation of your circuit, realized by the FPGA, to the TA. Part II: The circuit here is still pretty straightforward, with two goals:

1. You’ll learn how to create modules (basically like ’C’ functions ) in Verilog. 2. You’ll see how many hours of wiring all those gates for Lab 3 can be replaced by about 4 minutes of typing. This is why industry rather likes programmable devices! Redo all of Lab 3 by following these steps:

# Create a new source .v for equations for a one-bit full adder. Create a one-bit full adder module (modules are described in Appendix F).

# Now using the above module (four times), create a four-bit full adder module. Both modules can reside in the same file.

# Create .v equations for a 2->1 multiplexer and package these into a module.

# Now create a 4->1 multiplexer module (from scratch, or using the 2->1 if you like).

# Although in lab 3 we just needed a two-bit adder, if I gave you a four-bit adder chip instead you would certainly be able to use it to add two two-bit numbers. Use your four-bit adder module and your 4->1 multiplexer module to duplicate Lab 3.

Show the successful operation of your circuit, realized by the FPGA, to the TA.

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Part III: Choose one of the following two tasks. Groups which are pressed for time or feel a little weak in digital circuits may wish to select task 1. Those of you who were bored in Lab 4 are encouraged to do a thorough job of task 2.

1. Use the FPGA to implement Lab 4, but modified. One possible problem with Lab 4 is that the judges don’t necessarily vote at the same time instant, so as some of the judges set their switches other judges may be able to figure out how the voting is going. Let’s add a new input CLOCK: the inputs from the judges are used only at the instant of the rising edge of CLOCK (by which time the judges must have set their inputs). This modification will let you learn a little about sequential circuits and the FPGA. Demonstrate the successful voting system to the TA.

2. This task is rather open-ended, relying upon your inventiveness and initiative: I would like you to explore the speed of the FPGA. Basically, if the FPGA accepts some switch input and produces some output on an LED then you can assess the delay between the switch input and LED output signals. Obviously you can’t do this by eye; you’ll need to use the oscilloscope to observe the signal levels. I suggest that you observe the pins on the connecter that usually goes to the speedwire board (you’ll need some pin sockets for this; ask the TA). At the very least, report the delay times for a 1-bit, 2-bit, 3-bit, and 4-bit ripple adder (we’re interested in the maximum delay, from the first carry input to the last carry output). The FPGA is very fast -some of the delays you may not be able to measure, however you will definitely see the delay in a 4- bit adder if you’re doing things right. Show the 4-bit ripple adder delay time to the TA. It would also be interesting to know the copy delay (the time for the FPGA to just copy an input to an output) and you might want to explore the delays associated with implementing basic gates. I strongly encourage experimentation here. Try something interesting! Be sure to document your approach in your report. How accurate are your delay-time measurements? Are they repeatable? (i.e., if you measure the delay a couple of times, how similar are the numbers you get?)

Report: For the report, include any relevant circuit diagrams (for Part III) and include ALL .v code which you wrote for this lab. Make sure that your code includes at least minimal comments to identify its purpose; we will deduct marks for unreadable / incompre hensible files.

Also think about how you might test the correct functionality of circuits having many inputs / outputs (e.g., large adders and multiplexers) when you’re limited to only eight switches and eight LEDs. That is, it is easy to build a 10-bit adder on the FPGA, but how would you test it? Discuss this in your report.

Lab 6 - Sequential Circuits: FlipFlops and Counters

So far this term, in Labs 1 through 5, we have considered only combinational circuits. The goalof this lab is to explore a variety of common sequential circuits. To allow us to investigate awider array of circuits within a reasonable amount of time, this lab involves only simulation inB2-Logic, you do not have to implement any circuits in hardware.

Even though you won’t be doing any wiring, do not show up at your lab session unprepared — youwill be unable to start from scratch to fully simulating all of these circuits in three hours. Use thefree week preceding this lab to study some of the circuits, prepare drawings in your lab book, andto do some preliminary simulations. Also don’t redevelop each circuit from scratch — the variouscircuits have a lot in common and you can save time by reusing circuitry.

There are two parts to this lab. The first looks at the most fundamental class of sequential circuits:flipflops. You will construct four different kinds (most of which you will have seen in class). Thesecond part looks at the design of some more interesting sequential circuits, all of which can beconstructed as a bank of flipflops connected by combinational logic.

Part I:

Flipflops (FFs) are the most fundamental components used in the construction of sequential cir-cuits. Essentially, a FF is a circuit which has memory – it can store and remember one bit. Themanner in which this one bit (known as the state of the FF) is set or modified depends on the kindof FF in question, and we’ll explore four different options.

FF circuits basically possess two attributes:

1. The manner in which the inputs affect the FF state. The common types are RS, D, T, and JK.

2. The nature of the triggering or clocking of the FF. The common methods are asynchronous,level-triggered, and master-slave / edge-triggered.

This gives us a total of 12 possible FF circuits, many more than we want to study in this lab; we’lllook at four different circuits which will give us a pretty good overview.

Most FFs are clocked; that is, the FF will use the inputs (RS, D, T, or JK) only at certain clockedperiods of time, and the rest of the time the inputs are ignored (and have no effect on the state ofthe FF). This type of FF is known as synchronous (it’s operation is synchronized with the clock).A FF may also be asynchronous (no clock); its internal state may be changed by the inputs at anytime. Although asynchronous circuits are generally much faster than synchronous ones, they arealso much more difficult to design, and we will not spend much time looking at them in this course.

You will see that all FFs have certain circuitry in common, and the main objective of this lab is foryou to thoroughly understand this circuitry, and to see how a variety of FF types can be constructedby building around this core (you’ll also save a lot of time constructing your circuits by reusingparts). We will proceed through four FF designs, each building upon the previous one.

In your report, be sure to answer all of the questions asked throughout the following sections.

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Q

Q

SET

RESET

Figure 1: Asynchronous RS FF

Q

Q

SET

RESET

CLOCK

Figure 2: Level-clocked RS FF

1. Attributes: RS inputs / Asynchronous clocking

This is the simplest possible FF. The two inputs R, S (Reset and Set) control the state of theFF as follows:

• If R and S are both HIGH, then the state Q is unchanged over time.

• If S (Set) goes LOW, then the state Q goes to the HIGH state.

• If R (Reset) goes LOW, then the state Q goes to the LOW state.

• If S and R are both low, then both Q and Q are high, and the state of the FF will dependon which input goes high first. We normally don’t permit both S and R to be low at thesame time.

In B2-Logic, construct and simulate the circuit shown in Figure 1. Prepare a timing diagramfor the FF.

2. Attributes: RS inputs / Level clocked

Modify the previous circuit to form a clocked RS FF as shown in Figure 2:

The purposes of the R and S inputs are unchanged from before, albeit inverted: now Q isunchanged when R and S are both LOW. However the inputs have an effect only when theclock is HIGH; when the clock is LOW R and S are fully ignored.

Draw a timing diagram showing the level of Q for a variety of input (R, S, CLOCK) settings.What happens if R or S change while the CLOCK is HIGH?

3. Attributes: D input / Level clocked

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Q

Q

CLOCK

D

Figure 3: Level-clocked D FF

Q

Q

CLOCK

J

K

Master FlipFlop Slave FlipFlop

Q

Q

m

m

CLR

Figure 4: Master-Slave JK FF

D FFs are very widely used because they are simple and useful: at every clock pulse thevalue of the D input is transferred to the Q state (essentially like a 1-bit memory element).

A level-clocked D FF is shown in Figure 3. Simulate the circuit and construct a timing-diagram for this FF.

4. Attributes: JK inputs / Master-Slave clocking

Construct the circuit for the JK Master-Slave FF in Figure 4. Although the circuit looksrather complicated, we can quite quickly break it down into simpler structures (also see yourtext, p.211ff).

Ignore the JK inputs for now and pretend that they are RS as usual. We essentially have twoRS FFs, one connected to the other, but the clock driving the slave FF is inverted from theclock driving the master. That is, only one of the two FFs will be able to change its state atany time. So when the clock is HIGH, the state of the master FF (Qm, Q̄m) can be changed;when the clock is LOW, the state of the slave FF (Q, Q̄) is changed based on the state of themaster. The feedback lines from the output of the slave to the input of the master are whatmake this a JK FF, rather than an RS.

The CLR input, when low, initializes the FF to a known state. I suggest that you set CLR

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to LOW and then back to HIGH at the start of your simulation, otherwise B2-Logic may getbadly confused.

Simulate the circuit for various values of J and K while the clock is cycling to see what isgoing on. You’ll want the circuit simulator to display some of the internal circuit levels (e.g.,Qm, Q̄m), not just the inputs and outputs. Show a successful simulation to the TA.

Draw the state transition diagram, showing how the state Q is affected by the inputs J, K,CLR. Also draw a timing diagram that shows the effects of different values for J and K onthe FF state. Your timing diagram should include cases in which the values of J and/or Kchange while the clock is low, and similarly cases while the clock is high.

Part II:

Now that we have a pretty clear idea of how FFs are built, we want to explore their use. Mostof the time you just want to use FFs to store state information, in which case D FFs are by farthe most popular. However the added flexibility and functionality of JK FFs can sometimes makecircuit design simpler (i.e., requiring fewer external gates). In terms of timing, Master-Slave/Edge-Triggered FFs are the most popular because they are simple to use: the FF inputs need to bemeaningful only at the instant of the clock edge.

Use edge-triggered D FFs (74x74) to build a four-bit left-right shift register (see text, p.264). Theregister has five inputs: clock, clear, left/right, in-left, in-right. The outputs are just the states ofthe four D FFs. The idea is that the register shifts left or right at each positive clock edge; whenshifting to the left the rightmost FF gets its value from in-right (and vice-versa).

Include a full circuit diagram and simulation output in your report. Many shift registers also allowparallel loading (i.e., add four input lines and a “load” line — at the clock edge the D FFs are setequal to the input if “load” is HIGH). In your report, sketch (but don’t simulate) the circuit for a4-bit shift-register allowing parallel loading.

Demonstrate successful simulation of this circuit to the TA.

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Lab 7 – Finite State Machine using Xilinx StateCAD In this lab you will finally start putting large parts of the material which you have learned in the course to practical use. Whereas previous labs involved only combinational circuits (Labs 2-4) or had you construct already-available sequential circuits (such as shift registers and counters) mainly for pedagogical purposes, in this lab you will design a practical controller for a real-world application: a traffic light controller. You will design a simple traffic light controller as a finite state machine and implement the controller on the Xilinx Spartan 3 board. A traffic light controller is a circuit which senses the presence of cars and switches the traffic light in an appropriate manner. You should be taking the following steps to accomplish this task:

1. Design a state diagram and state table based on a written Traffic Light Specifications given on the next page

2. Demonstrate your ability to implement your state diagram using stateCAD program and generating the HDL code, synthesizing with ISE and downloading the code to the board. To learn how to use stateCAD tool please refer to an online tutorial which is available from the lab page

3. Map your circuit to the Spartan 3 board. Use the built-in 50MHz clock on the Spartan3 board for your system clock. Internal 50MHz clock is quite fast and can be slowed down either using DCM or coding a counter as discussed in the class

4. Use LED’s for your traffic light outputs and switches for your cars inputs

NS EW

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Traffic Light Specifications You’ll be designing a controller for a traffic light; i.e., a circuit which senses the presence of cars and switches the traffic lights in an appropriate manner.

1. Inputs: There are sensors in the road (either pressure or, more commonly, inductive) which sense the presence of a car. You have two sensor inputs - one for each of the E-W and N-S directions. An input of HIGH (1) indicates the presence of a car.

2. Outputs: A total of six outputs: a red, yellow, and green light for each of the two

directions.

3. Operation: After the light changes to green, it will stay green for at least three clock cycles. When the lights change, the yellow light must come on for exactly one cycle, and then both directions must have a red light for exactly one cycle before a green light comes on.

A sensor must indicate the presence of a car for three consecutive clock cycles in order to have the light change (this is meant to model the possibility that a car stops at the intersection, pauses, and turns right; you don’t want the light to change in this case). Demonstrate the functioning circuit to the TA during your lab session. For the report, discuss every step of the circuit design process; that is, show a state diagram, state assignments, StateCAD diagram, Circuit Diagram (combinational logic, flip-flops..), Verilog HDL code, Clock slow down design and code etc. Discuss any problems which you may have encountered.

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Lab 8 -Final Programmable Sequential Circuit If you have found earlier labs to be pointless or boring, here’s your chance to do something “real.” In this lab you’ll start building pretty sophisticated sequential circuits, the likes of which would have seemed very daunting to you at the beginning of the term. This is not meant to scare you — completing this lab should not be so difficult — however those of you interested in a challenge will find plenty of opportunity here to do something interesting. The lab will be implemented in one of three programmable logic platforms (listed in order of increasing capability and sophistication): 1. StateCAD from Lab 7 2. FPGAs / Xilinx ISEfrom Lab5 (Appendix F) 3. Programmable computers on a chip (PICs, Appendix G). This can be a really interesting option; interested students/groups should really come and talk with the instructor. Traffic Light Controller Basically like lab 7, but don’t limit yourself to the controller which I described in lab 7 (which isn’t really a very good model of a traffic light, if you think about it); that is, you decide how you think a light should work. The emphasis here will be on realistic timing — I want your controller to behave like a real traffic light (maybe go to an intersection and observe for a few minutes). Base your design on a 1Hz or 2Hz clock. Implement all side traffic light controller with advanced flashing green (for cars turning left), pedestrian signals etc. You can use 7 segment LED lights to output a down counter for the pedestrian crossing. If your lab group is strong in digital circuits, has an interest in microcode, machine-language / assembly-language programming, or low-level computing, then I would encourage you to do something creative with PIC microcontroller. You can select any interesting topic (see a few suggestions at end of this lab), but you should discuss it with the instructor before proceeding.

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Some of you will want to use the FPGAs – you already have experience with them, and they are relatively easy to program. Spend at least a little time thinking about how to organize and modularize your code. You have to be creative. Multiplier Implement a sequential binary multiplier (discussed in the text, p.330, 475). We’re looking for an implementation of the sequential algorithm. You should try to implements a four-bit multiplier. For bonus marks display the results on 7 segment LED's. Note that although binary multiplication is discussed in the textbook, the solution which they give is a little trickier than the one which is sometimes given in class. I suspect that many of you may f nd the text discussion more confusing than helpful. Other FPGA Project Possibilities: Programmable count-down clock / timer (like on a microwave oven). You need to be able to set, start, stop, and clear the timer. Define the problem carefully and proceed. Designing an ALU with 2bit or 4bit Adder, Subtractor, Comparator, Multiplier which are multiplexed together as shown below and the desired output is displayed on 7 segment LED’s

MUX

Output

Selectors

ADD SUB MUL CMP

X (2) Y (2)

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PIC Project Possibilities: Traff c-light problem, as described above. You have a limited number of inputs, so you’ll need to be creative. Frequency analyzer (of an input square or sine wave). That is, you supply an input (from a function generator) and the frequency of the input (measured in Hz or kHz, whatever) shows up on the LEDs. Simple cycle-computer (eg, speedometer / odometer system). Normal cycle computers get a stream of pulses as the front tire rotates; you can simulate these pulses using one of the pushbuttons. Write a program to keep track of speed and distance; one of the switches should be used to select what is being displayed. I had one group do this, so the project is definitely feasible. Programmable digital thermostat. Takes a temperature as an input, and determines heating / cooling settings. Should be programmable (use some creativity, but obviously the desired temperature needs to be settable, as should time-of-day controls). Programmable count-down clock / timer (like on a microwave oven), but fancier than what might be done under the FPGA. For example, include extra options (pre-programmed settings, minute-plus buttons etc.). Ending Comments: Regardless of which problem you decide to tackle, demonstrate the functioning circuit to the TA during your lab session. For the report, discuss every step of the circuit design process. In particular, you have to show an ASM chart (you can show a state diagram too, if you wish, but you have to prepare an ASM chart) and a block diagram of your data processing circuitry. Also include a printout of any diagram and code (Verilog, StateCAD, PIC etc.). You’ll also want to make sure that you include a textual description of what it is that you actually implemented (i.e., describe in some detail the problem which you actually solved). Discuss problems which you encountered, design tradeoffs which you had to make and recommendation for future readers of your report (i.e., should things be done differently, are there any interesting ways in which to extend your circuit etc.)

Appendix A: Digital Interface Module

The digital interface module is a general binary logic control and display board. The interfacemodule connects to the speedwire prototyping board via ribbon cable.See Appendix A for the speedwire board This interface board will only be used for interfacing Speedwire and PIC boards. Interface board designs support four basic logic input/output features:

1. Logic Switches:

Switches SW1 through SW8 generate eight logic outputs. The outputs of these switches arenot “debounced,” and so should not be used as clocks; for a clock the pulsed switches shouldbe used instead.

2. Pulsed Switches:

There are two pulsed switches - PB1 and PB2. Each switch generates a positive logic levelwhile it is being pressed. These switches are “debounced” (i.e., generate clean low-high andhigh-low transitions) and so are suitable as clock inputs to your circuits.

3. Variable Clock:

Although the pulsed switches can be used as a clock, often you will want a nice regular,periodic clock. A single clock is available whose frequency is controlled by switches S1, S2,and S3. The clock frequency is determined as follows:

S3 S2 S1 Old Interface Board New Interface Board

0 0 0 1 Hz 1 Hz0 0 1 2 Hz 2 Hz0 1 0 4 Hz 4 Hz0 1 1 64 Hz 16 Hz1 0 0 128 Hz 32 Hz1 0 1 256 Hz 64 Hz1 1 0 512 Hz 256 Hz1 1 1 1024 Hz 1024 Hz

4. LED Displays:

The current state of eight logic inputs can be displayed on the board. When an LED is lit itindicates that the corresponding logic level is high; otherwise the LED is unlit.

The new interface board also includes two 7-segment displays, which give a two-digit hex-adecimal display of the same eight logic inputs.

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P O W E R

Xilinx Spartan 3 Board

D9 for External Clock input

Appendix A – Figure A3

29 A

I

Appendix B: Digital Systems Kit

IC Components

Device Qty Cost ($)74LS00 5 0.3074LS02 3 0.5074LS04 1 0.3074LS08 5 0.3074LS32 3 0.3074LS86 1 0.3574LS151 4 0.6074LS153 1 0.6074LS157 2 0.6074LS244 2 0.80

Other Hardware

Item Qty Cost ($)Tackle Box 1 12.00Digital Intface Mod. 1 200.00Speedwire Board 1 250.00Speedwire Pen 1 60.00Speedwire Spools 3 35.00Power Supply 1 25.00IC Puller 1 6.00Wire Pick 1 4.00Wire Cutter 1 9.00Tweezers 1 7.00Ribbon Cable 1 10.00Logic Probe 1 39.00

The total replacement cost of the kit is about $780.

Each group is responsible for their assigned kit and will be held responsible for lost equipment.

Note: additional parts are available for signout. Although you have enough parts in your kits toperform the labs, interested students may want to sign out continuity meters, or possibly other partsfor a more ambitious lab 8.

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SD192 Component Reference List

DEVICE COMBIN/SEQUENTIAL DESCRIPTION

’00 C Quad 2-Input NAND

’02 C Quad 2-Input NOR

’04 C Hex NOT

’08 C Quad 2-Input AND

’32 C Quad 2-Input OR

’74 S Dual D-Type Flipflop

’86 C Dual 2-Input XOR

’107 S Dual JK-Type Flipflop

’151 C Single 8 → 1 MUX

’153 C Dual 4 → 1 MUX

’157 C Quad 2 → 1 MUX

’173 S Quad D Register

’191 S 4-Bit Counter

’244 C Octal Buffer

’374 S Octal D Register

Dual / Quad / Octal refer to the number of devices (2 / 4 / 8) on one chip.

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Appendix C: The B2-Logic Digital Simulation Package

B2 Logic allows you to build a digital circuit on a computer and simulate it. As the simulationprogresses, the changing signal values are reflected in circuit probes, in a timing diagram, andin a spreadsheet. B2 Logic is not a printed circuit board design package. Rather, it is useful forverifying design ideas and for analyzing the timing of circuits. B2 Logic circuits are not currentlyportable to other programs.

To get started, choose New from the File menu to bring a clean circuit window. You will notice twofloating windows, one is the Tools and Time window and the other is the Device Library window.The various windows can be moved around by dragging the title bar, and resized by dragging theedges and corners.

The left part of the Tools and Time window has five tools:

1. The Selection Arrow is used to select device vertices, line segments, and text comments, todrag a rectangle around a group of devices to select them, and to move selected objects.

Double clicking on devices and on pins of devices with the selection arrow brings up their”properties” window. Double clicking on any part of a wire selects the complete wire.

2. The Crosshair is used to draw the line segments that make up the wires. It starts a newsegment every time you click down; the wire is terminated when you double click or clickwith the right mouse button.

3. The Typing Tool is used to create and edit text comments.

4. The Magnifying Glass is used to zoom in on a particular region of the circuit (hold downthe Control Key to zoom out).

5. The Logic Probe is used to view the signal value on any wire in the circuit.

The four buttons in the right part of the Tools and Time window operate the circuit simulation(from left to right): reset the simulation time to 0, stop the simulation, step the simulation by onetime step, and begin running the simulation continuously. The simulation results are shown in theTiming Diagram (use Show Trace). To compress or stretch the simulation output window (thedefault is much too wide) go to menu Output/Customize Trace and set the “Trace Interval” to alarger number; I suggest about 2000.

The first component you might want to put into the circuit is a 1-bit Input Device. To do this,double click on the 1-bit Input in the Device Library, then move the cursor into the circuit area.Click the mouse button to place down the input port. To deselect the input port, click anywhereelse in the circuit area.

Wires between components must always connect onto the circles on the component pins; be accu-rate - if your wire misses the circle, it is not connected. To draw a wire, click on the Crosshairtool in the toolbox, and click on the desired end of the wire. Release the mouse button and movethe mouse; the wire will follow the cursor. Anywhere you want to start a new wire segment, clickonce. Continue drawing segments until you reach one end, then double click. You will know thatthe wire has made a connection because there are small squares where wires meet a pin and where

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wires intersect. To delete a wire, first select it by double clicking on the wire, then hit ctrl-deleteor choose clear from the Edit menu.

Bus-connectors allow you to create groups of wires, which is convenient if you’re sending a bunchof wires to the same place. The top pin of the bus connector is the least significant bit.

There are over 100 device primitives available. In addition to the standard 74xxx series, there area bunch of special devices:

Available Components

Input Ports Bidirectional Port Output ProbeSeven Segment Display 1 ⇒ 2n Bus Connectors 2n ⇒ 1 Bus ConnectorsClock High Voltage GroundPull-Down Resistor Pull-Up Resistor Buffer (Delay Element)S-R Latch Clocked SR Latch JKFF w/ Reset and ClearPLD (generic) Decoder (generic) D Flip Flop (generic)RAM 16x4 Toggle Flip Flop

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A P P E N D I X - D PoweringtheBoard

Each of your kits contains an AC/DC adaptor which supplies powerto the digital interface module;the speedwire board receives power across the ribbon cable. The logic probe is powered from thematching connector on the speedwire board. Throughout Figure A-1, the “5V” and “G” labelsindicate the available VCC and GND connections.

Connection to the Digital Interface Module

The prototype (speedwire) board is connected to the digital interface module via a 26-conductorflat ribbon cable. The ribbon cable has drawn on it a coloured stripe which indicates pin #1; makesure that you plug in the cable in a manner consistent with that shown in Figure A-1 (i.e., red stripeto the outside of the board).

The pin definitions are as follows. Each pin is labeled as an input or output from the point of viewof the speedwire board:

Pin 1 - LED 8 (Output) Pin 9 - CLK (Input) Pin 17 - SW 8 (Input)Pin 2 - LED 7 (Output) Pin 10 - — ( ) Pin 18 - SW 7 (Input)Pin 3 - LED 6 (Output) Pin 11 - PB1 (Input) Pin 19 - SW 6 (Input)Pin 4 - LED 5 (Output) Pin 12 - PB2 (Input) Pin 20 - SW 5 (Input)Pin 5 - LED 4 (Output) Pin 13 - GND (Input) Pin 21 - SW 4 (Input)Pin 6 - LED 3 (Output) Pin 14 - GND (Input) Pin 22 - SW 3 (Input)Pin 7 - LED 2 (Output) Pin 15 - VCC (Input) Pin 23 - SW 2 (Input)Pin 8 - LED 1 (Output) Pin 16 - VCC (Input) Pin 24 - SW 1 (Input)

Note - the VCC and GND connections on pins 13–16 may or may not be present on your board;do not use these pins in any way.

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Appendix E: The FPGA (Gate Array) Module

An FPGA (Field Programmable Gate Array) is a very modern, sophisticated programmable logic device. It allows you to construct and test digital circuits in much the same way that you would write a computer program, without any of the mess or hassle of doing a lot of wiring (which you will experience with the speedwire board). It is precisely for this reason that FPGAs are widely used in industry, and this has motivated their introduction into SY DE 192. The FPGA which you will be using is based on the Xilinx Spartan-3 XC3S200 - containing the equivalent of about 200 000 gates (a LOT more than you can fit on your speedwire board!)

This is a new FPGA board which has built in user interface. The connections between the user interface and the XC3S200 locations (pins) are as follows; the no tions of “input” and “output” are considered from the point of view of the FPGA module:

LEDs The Spartan-3 Starter Kit board has eight individual surface-mount LEDs located above the push button switches. The LEDs are labeled LED7 through LED0. LED7 is the left-most LED, LED0 the right-most LED. The cathode of each LED connects to ground via a 270 ohm resistor. To light an individual LED, drive the associated FPGA control signal High, which is the opposite polarity from lighting one of the 7-segment LEDs. LED Connections to the Spartan-3 FPGA LED LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0 FPGA Pin P11 P12 N12 P13 N14 L12 P14 K12 Slide Switches The Spartan-3 Starter board has eight slide switches. Switches are located along the lower edge of the board, toward the right edge. The switches are labeled SW7 through SW0. Switch SW7 is the left-most switch, and SW0 is the rightmost switch. The switches connect to an associated FPGA pin, as shown below: Slider Switch Connections Switch SW7 SW6 SW5 SW4 SW3 SW2 SW1 SW0 FPGA Pin K13 K14 J13 J14 H13 H14 G12 F12 When in the UP or ON position, a switch connects the FPGA pin to VCCO, a logic High. When DOWN or in the OFF position, the switch connects the FPGA pin to ground, a logic Low. The switches typically exhibit about 2 ms of mechanical bounce and there is no active debouncing circuitry, although such circuitry could easily be added to the FPGA design programmed on the board. A 4.7K ohm series resistor provides nominal input protection. For information on switch debouncing please see a link on the lab page Or refer to pages 359 – 360 in section 9-3 of your text book.

35-A

Push Button Switches The Spartan-3 Starter Kit board has four momentary-contact push button switches. These push buttons are located along the lower edge of the board, toward the right edge. The switches are labeled BTN3 through BTN0. Push button switch BTN3 is the left-most switch, BTN0 the right-most switch. The push but ton switches connect to an associated FPGA pin, as shown below: Push Button Switch Connections Push Button BTN3 (User Reset) BTN2 BTN1 BTN0

FPGA Pin L14 L13 M14 M13 Pressing a push button generates a logic High on the associated FPGA pin. Again, there is no active debouncing circuitry on the push button. The left-most button, BTN3, is also the default User Reset pin. BTN3 electrically behaves identically to the other push buttons. However, when applicable, BTN3 resets the provided reference designs.

7 Segment LED

PIN Location

A B C D E F G DP E14

G13

N15

P15

R16

F13

N16

P16

Clock Sources:

The Spartan-3 board has a dedicated 50 MHz Clock. The 50 MHz clock oscillator is mounted on the bottom side of the board. You can use the 50 MHz clock frequency as is or derive other frequencies using the FPGAs Digital Clock Managers (DCMs). For information how to use DCM please see the Lab page.

Clock Oscillator Sources

Oscillator Source FPGA Pin

50 MHz T9

Socket (IC8) D9

35-B

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Appendix F: Xilinx ISE & Verilog HDL Programming Language The Xilinx ISE software will parse the Verilog Code for the Xilinx Spartan-3 XC3S200 Field Programmable Gate Array (FPGA). The program is installed on all of the machines in the 192 lab (see shortcut menu) and is also available free to download from the lab page. Although Tutorial #1 and Tutorial #2 describe the process in detail, I will also for your convenience would summarize them down here as well: Xilinx ISE Project Navigator Tutorial The objective of this tutorial is to: 1. Learn the basic use of Project Navigator to create a project and then implement their design via Project Navigator. 2. Learn how to use iMPACT to down load a bit file onto the FPGA. Tutorial Overview Project Navigator will allow you to create a project, include your VHDL files, synthesize your VHDL code, translate, map, and place and route your circuit for the FPGA specified in the project. Next, Project Navigator will generate the files to be down loaded onto the FPGA. Finally, Project Navigator will start iMPACT to download your bitmap file onto the FPGA. For this tutorial, we will build a simplified halfadder. Tutorial - Quick Steps 1. Create a new project in Project Navigator. 2. Create your .v files. a. Create halfadder.v and set as a top module 3. Create and edit Top.UCF. 4. Include your files into the Project Navigator project. 5. Implement your design. 6. Run iMPACT to download your bit file onto the FPGA. 7. Test your implementation and refine your design (if necessary). Tutorial - Detail Steps 1. Create a new project in Project Navigator.

a. Start Project Navigator. Double click the Project Navigator ICON on the desktop. When Project Navigator starts, its GUI will be displayed this will include four window panes. b. Create a new Project. i. Click File on the menu bar and select "New Project..." ii. In the New Project dialog box:

1. Enter a project name. 2. Make sure the Project Location is the directory you wish to contain your project. 3. Leave the Top-Level Module Type as HDL. 4. Click the Next button. 5. Verify the Properties are set as follows: 6. Click Next if the properties are correct. Otherwise, correct the properties and click next 7. Click Next again (no changes to Create a New Source). 8. Click Next again (no changes to Add Existing Sources). 9. Review the project specification to make sure they are correct and then click Finish.

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2. Create your .v files. a. Create halfadder.v

3. Create a .UCF file NOTE: The UCF file maps signals in your Verilog code to pins on the Xilinx board. For the UCF file to map a pin on the Xilinx board to a signal in your halfadder.v file, must match the net name in the UCF file. If the names do not match, change the name in your .v file, not the net name in the .UCF file. The software tools you are using run on both Unix and Windows systems. Details of the device we are using: Device Family Spartan3 Device xc3s200 Package ft256 Speed Grade -5 Top-Level Module Type HDL Synthesis Tool XST (VHDL/Verilog) Simulator Modelsim Generated Simulation Language VHDL It is recommended that you strive to keep signal names consistent in your .v and .ucf files. 4. Select the halfadder file and Implement your design (Synthesize, translate, map, place and route, and generate the files)

a. Scroll down the process window and find "Configure Device (iMPACT)". d. Double click "Configure Device (iMPACT)". This will walk through all the steps required to implement your design. If you perfer, you can double click each phase individually. e. If errors are detected, an error message will be displayed in the Console window pane of Project Navigator.

NOTE: Resolve any errors and repeat step 4 until the project completes with no errors. 5. Download your design onto the FPGA. In step 5d, by double clicking "Configure Device (iMPACT)", iMPACT will start automatically. When Impact starts, it will display a series of dialog boxes.

a. In the Configure Devices dialog box, accept default values by clicking Next. b. In the Boundary-Scan Mode Selection dialog box, accept default values by clicking Finish. c. Click the OK button in the Boundary-Scan Contents Summary message box. d. In the Assign New Configuration File dialog box:

i. Make sure the correct director is selected in the Look In: edit box. ii. Select the halfadder.bit file. iii. Click the open button.

e. Click YES in the iMPACT message box. f. Click OK in the warning box (this is expected). g. In the upper window pane in iMPACT, right click on the chip ICON.

i. In the popup menu, select "Program..." The "Program Options" dialog box will appear. ii. Click the OK button. A progress bar will appear while the file is being down loaded. iii. The bitmap generated by your Verilog code is now loaded on the Xilinx board.

7. Test your implementation and refine your design (if necessary).

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Hardware Description Language (HDL) A hardware description language is a language that describes the hardware of digital systems in a textual form. It resembles a programming language, but is specifically oriented to describing hardware structures and behavior. It can be used to represent logic diagrams, Boolean expressions, and other complex digital circuits. There are two standard HDLs that are supported by IEEE. VHDL and Verilog HDL. Because Verilog is an easier language to learn and use, we have chosen if for this course. Verilog HDL has a syntax that describes the legal construct that can be used in the language. Verilog uses about 100 keywords predefined. Examples of keywords are: module endmodule input output wire and or not Any text starts with two slashes (//) will interpreted as a comment. Blank spaces are ignored and names are case sensitive. A module is the building block in Verilog. It starts with the keyword module and is always ends with the keyword endmodule . Here is an example to illustrate some aspects of the language. Example 1 //Description of simplified Halfadder Circuit module smpl_Circuit(A, B, sum, carry) input A,B; output sum, carry; xor gate1(sum,A,B) and gate2(carry,A,B) endmodule Example 2 //Description of simple circuit module smpl_circuit(A,B,C,x,y); input A,B,C; output x,y; wire e; and g1(e,A,B); not g2(x,e,y); endmodule

g1

g2

g3

e

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In example 2 the first line is a comment, describing the function of the circuit. The second line declares the module together with a name and a port list. The name (smpl_circuit in this case) is an identifier that is used to reference the module. The port list provides the interface by which the module communicates with the environment. In example 2, the ports are the inputs and outputs of the circuit. The statement is terminates with a semicolon (;). Internal connections are declared as wires. In example 2 the circuit has one internal connection at terminal e and is declared with the keyword wire. Wire data type is where the target output of an assignment updated continuously. Gate names are used as keywords in the structure of the circuit. Each gate declaration consists of an optional name (such as g1,g2,etc.) followed by the gate output and inputs separated with commas and enclosed in parantheses. The output is always listed first followed by the inputs. The module description ends with the keyword endmodule. There is no semicolon after the endmodule. Boolean Expressions Boolean expressions are specified in Verilog with a continuous assignment statement consisting of the keyword assign followed by a Boolean expression. To distinguish the arithmetic plus from logical OR, Verilog uses the symbols (&), (|), and (~) for AND, OR, and NOT respectively. To describe the circuit in example 2 with a Boolean expression we use the following statement: assign x = ((A & B) | ~C ); Lets use the following Boolean expressions in Verilog code: x = A + BC + B’D y = B’C + BC’D’ Example 3 // Circuit specified with Boolean expressions module circuit_bln (x,y,A,B,C,D); input A,B,C,D; output x,y; assign x = A | (B & C) | (~B & D); assign y = (~B & C) | (B & ~C & ~D); endmodule

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Turth Tables Here is the example of a halfadder defined as a truth table using Verilog Truth table can be defined as UDP (user define primitives) and do not use the keyword module . Here are the rules you should remember:

. It is declared with the keyword primitive followed by a name and port list. . There can only one output and it must be listed first in the port list and declared with an output keyword

Example 4 //Halfadder circuit truth table primitive halfadder(Sum, A,B); output Sum; input A,B;

table // A B : Sum (Note that this is a comment only) 0 0 : 0; 0 1 : 1; 1 0 : 1; 1 1 : 0; endtable

endprimitive Verilog HDL Operators

Symbol Operations + binary addition - binary subtraction

& bit-wise AND | bit-wise OR ̂ bit-wise XOR

~ bit-wise NOT = = equality > greater than > less than

{ } concatenation ?: conditional

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Calling other modules within the main module Example 5 //Fulladder module calling Halfadder module module halfadder (S,C,x,y); input x,y; output S,C; xor (S,x,y); //Instantiate primitive gates and (C,x,y); endmodule module fulladder (S,C,x,y,z); input x,y,z; output S,C; wire S1,D1,D2; //outputs of first XOR and two AND gates halfadder HA1 (S1,D1,x,y), //instantiate the halfadder HA2 (S,D2,S1,z); or g1(C,D2,D1); endmodule

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Hex to 7 Segment LED Example 6 //Displaying Hex values on 7 Segment LED display module hex2led(HEX,LED); input [3:0] HEX; output [7:0] LED; reg [7:0] LED; // reg data type retains its value until a new value is assigned always @(HEX) begin case (HEX) 4'b0001 : LED = 7'b1111001; //1 4’b0001 specifies a 4-digit binary number whose value is 0001 4'b0010 : LED = 7'b0100100; //2 4'b0011 : LED = 7'b0110000; //3 4'b0100 : LED = 7'b0011001; //4 4'b0101 : LED = 7'b0010010; //5 4'b0110 : LED = 7'b0000010; //6 4'b0111 : LED = 7'b1111000; //7 4'b1000 : LED = 7'b0000000; //8 4'b1001 : LED = 7'b0010000; //9 4'b1010 : LED = 7'b0001000; //A 4'b1011 : LED = 7'b0000011; //b 4'b1100 : LED = 7'b1000110; //C 4'b1101 : LED = 7'b0100001; //d 4'b1110 : LED = 7'b0000110; //E 4'b1111 : LED = 7'b0001110; //F default : LED = 7'b1000000; //0 endcase end endmodule Numbers can be specified also in decimal, octal, or hexadecimal with the letters‘d, ‘o, and ‘h, respectively. reg keyword is generally used for input in-terms of memory and wire keyword is for output in-terms of connection.

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Flip-Flops and Latches The best way to understand Verilog code is through example. Example 7 //Description of D latch module D_latch (Q,D,control); output Q; input D,control; reg Q; always @ (control or D) if (control) Q = D; // same as: if (control = =1) endmodule Example 8 //Description of D flip-flop module D_FF (Q,D,CLK); output Q; input D, CLK; reg Q; always @ (posedge CLK) Q = D; endmodule Example 9 //Description of D flip-flop with asynchronous reset module DFF (Q,D,CLK,RST); output Q; input D, CLK, RST; reg Q; always @ (posedge CLK or negedge RST) if (~RST) Q = 1’b0; // same as: if (RST = = 0) else Q = D; endmodule

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Example 10 //Description of T flip-flop from D flip-flop and gates module TTF (Q,T,CLK, RST); output Q; input T, CLK, RST; wire DT; assign DT = Q ^ T; // Instantiate the D flip-flop DFF TF1 (Q,DT,CLK,RST); endmodule Example 11 //Description of JK flip-flop from D flip-flop and gates module JKFF (Q,J,K,CLK, RST); output Q; input J, K, CLK, RST; wire JK; assign JK = (J & ~Q) | (~K & Q); // Instantiate the D flip-flop DFF JK1 (Q,JK,CLK,RST); endmodule

Appendix G: PICs – Programmable Microcontrollers

Details of the programmable microcontroller are available in a separate handout; any group inter-ested in pursuing the PIC approach for Lab 8 should ask the instructor for a copy of this handout(parts of which should also be available on the course home page). The description in this appendixshould be sufficient to give an overview of the device and to allow groups to decide whether they’reinterested. Groups in past years have found to be manageable in terms of time; that is, althoughthere is a bit of a learning curve, once you have figured it out you can make progress very quickly.

The PIC devices are basically a complete computer on a single chip; that is, it has a CPU, programmemory, data memory, and inputs/outputs all on a single chip. Anyone interested in assembly-language programming should love this device. We have built a small module board for you whichcontains a PIC chip and plugs directly into your interface board. Most of the interface board signalsare available:

PIC Line(s) Connected Signal(s)RB0 ... RB7 LED1 ... LED8RA0 ... RA1 PB1 ... PB2RA2 SW5 or external input onto on-board socketRA3 SW6RA4 User controlled clock from interface board

The rate at which the chip executes instructions is controlled by its input clock; this clock can beset in one of four ways:

SW7 SW8 CLKIN Value Description0 0 1 MHz Clock For running code fast0 1 User Clock from Interface Board For running code at moderate, sustained rates1 0 PB2 from Interface Board For stepping through code in single steps1 1 No Connection You don’t want this.

The chip is programmed using a chip writer. Here are the 3 easy steps to follow: 1) You write a program in PIC assembly language using any of your favourite text editor 2) Compile the program using MPASM utility 3) Load the compiled result file .hex to the chip programmer using ChipWin and download the file to the PIC Once the PIC is programmed, the chip will keep its program indefinitely (untilrewritten) - it doesn'trequire any electrical power to hold on to its memory.

The assembly language used to program the device is fairly straightforward, and is described ingreat detail, along with other features (timers, counters, interrupts, reset handling etc.) in thedetailed handout. We can provide you with several sample files (see lab page) to get you started

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syde 192 digital systems - university of waterlootnaqvi/downloads/doc/sd192/2010labs.pdf · syde...

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