syen 3330 digital systems
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SYEN 3330 Digital Systems. Chapter 6 – Part 4. Overview of Chapter 6. Types of Sequential Circuits Storage Elements Latches Flip-Flops Sequential Circuit Analysis State Tables State Diagrams Sequential Circuit Design Specification Assignment of State Codes Implementation - PowerPoint PPT PresentationTRANSCRIPT
SYEN 3330 Digital Systems Jung H. Kim 1
SYEN 3330 Digital Systems
Chapter 6 – Part 4
SYEN 3330 Digital Systems Chapter 6-4 Page 2
Overview of Chapter 6• Types of Sequential Circuits
• Storage Elements– Latches
– Flip-Flops
• Sequential Circuit Analysis– State Tables
– State Diagrams
• Sequential Circuit Design– Specification
– Assignment of State Codes
– Implementation
– HDL Representation
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Developing the State DiagramA state is an abstraction of the history of the past
applied inputs to the circuit (including the “null” input at power-up or reset). The interpretation of “past inputs” is tied to the synchronous operation of the circuit. E. g., an input value is measured only during the setup-hold time interval for an edge-triggered flip-flop.
Examples: State A represents the fact that a 1 input has
occurred among the past inputs. State B represents the fact that a 0 immediately
followed by a 1 has occurred among the most recent past two inputs.
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Developing the State DiagramWhen designing a circuit, states are used to remember
some meaningful property of a past input sequence that is essential to predict future output values.
A sequence recognizer is a sequential circuit that produces a distinct output value whenever a fixed pattern of input symbols occur in sequence, i.e, recognize the input sequence.
We will develop a procedure specific to sequence recognizers to convert a problem statement into a state diagram.
Next, the state diagram, will be converted to a state table.
The state table will be used to design the sequential circuit.
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Sequence Recognizer Procedure
Step 6 is required because the sequential machine must recognize the input sequence regardless of where the input sequence occurs within the overall sequence applied since “reset.”.
To develop a sequence recognizer state diagram:
1. Begin in an initial state in which NONE of the initial portion of the sequence has occurred (typically “reset” state).
2. Add a state which recognizes that the first symbol has occurred. 3. Add states which recognizes each successive symbol has occurred. 4. The final state represents that the input sequence that has
occurred. 5. Add state transition arcs which specify what happens when a
symbol not in the proper sequence has occurred. 6. Add other arcs on non-sequence inputs which transition to states
that represent the input sub-sequence that has occurred.
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Sequence Recognizer Example
Example: Recognize the sequence 1101
Note that the sequence 1111101 contains 1101 and "11" is a proper sub-sequence of the sequence.
Thus, the sequential machine must remember that the first two one's have occurred as it receives another symbol.
Also, the sequence 1101101 contains 1101 as both an initial sequence and a final sequence with some overlap. (ie 1101101 or 1101101 and the 1 in the middle -- 1101101 -- is used in both sequences)
The sequence 1101 must be recognized each time it occurs in the input sequence.
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Example: Recognize 1101We begin by defining states for the recognized sequence
assuming it starts with first symbol and continues through each symbol in the sequence to be recognized. We take output "1" to mean the full sequence has occurred.
Starting in the initial state (Arbitrarily named "A") we:
A B1/01. Add a state that
recognizes the first "1".
State "A" is the initial state, and state "B" is the state which represents the fact that the "first" one in the input sequence has occurred. The output symbol "0" means that the full recognized sequence has not yet occurred.
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Recognize 1101 (Continued)After one more "1" we have:
A B1/0
C1/0 "C" is the state
obtained when the input sequence has two "1"s. Finally, after
"110" and a "1" we have:
Note that the transition arcs are used to denote the output function (Mealy Model).
The output "1" noted on the arc from D means the sequence has been recognized.
What state should the arc from state "D" go to? (Remember: 1101101 ??)
A B1/0
C1/0
D0/0 1/1
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Recognize 1101 (Continued)
A B1/0
C1/0
D0/0 1/1
Clearly the final "1" in the recognized sequence 1101 is a sub-sequence of 1101. It follows a "0" which is not a sub-sequence of 1101. Thus it should represent the same state reached from the the initial state after a first "1" is observed. We obtain:
1/1
A B1/0
C1/0
D0/0
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Recognize 1101 (Continued)
1/1
A B1/0
C1/0
D0/0
The state have the following abstract meanings: A: No proper sub-sequence of the sequence has
occurred. B: The sub-sequence "1" has occurred. C: The sub-sequence "11" has occurred. D: The sub-sequence "110" has occurred.
The "1/1" on the arc from D to B means that the last "1" has occurred and thus, the sequence is recognized.
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Complete the Diagram (1101)The other arcs are added to each state for inputs not yet
listed. Which arcs are missing?
1/1
A B1/0
C1/0
D0/0
Answer: "0" arc from A "0" arc from B "1" arc from C "0" arc from D.
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Add Missing ArcsState transition arcs must represent the fact that an
input sub-sequence has occurred. Thus we get:
1/00/0
0/0
0/0
1/1
A B1/0
C1/0
D0/0
Note that the "1" arc from state C to state C implies that State C means: "two or more 1's have occurred".
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1101 State Table from DiagramFrom the State Diagram, we can fill in the State Table.
Present State
Next State x=0 x=1
Output x=0 x=1
A A B 0 0 B C D
There are 4 states, one input, and one output. We will choose the form with four rows, one for each current state.
1/00/0
0/0
0/0
1/1
A B1/0
C1/0
D0/0
From State A, the “0” and “1” input transitions have been filled in along with the outputs.
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Complete 1101 State TableFrom the
State Diagram, we complete the State Table.
1/00/0
0/0
0/0
1/1
A B1/0
C1/0
D0/0
Present State
Next State x=0 x=1
Output x=0 x=1
A A B 0 0 B A C 0 0 C D C 0 0 D A B 0 1
What would the state diagram and state table look like for the Moore model?
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Moore Model for 1101
For the Moore Model, outputs are associated with states.
We would have to add a state "E" which encoded the output value for the final "1" in the recognized input sequence.
Thus, the state after "D", though similar to "B", would generate an output of "1" and thus be different than "B".
The Moore model may have more states than the Mealy model.
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Moore Diagram for 1101
A/0 B/0 C/0 D/0
0
E/1
0
0
0
11
1
110
We must mark outputs on states for Moore model.
Arcs now show only
state transitions.
Add a new state "E" to produce the output "1"
Note that the new state, "E" produces the same behavior in the future as state "B." But it gives a different output at the present time. Thus these states do represent a different abstraction of the input history.
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Moore State Table for 1101
A/0 B/0 C/0 D/0
0
E/1
0
0
0
11
1
110
Present State
Next State x=0 x=1
Output y
A A B 0 B A C 0 C D C 0 D A E 0 E A C 1
The state table is shown below. Typically, the Moore Model takes more states than the Mealy Model.
Mnemonic aid: "Moore is More"
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Second State Diagram Example
• A register consists of an ordered set of n flip-flops plus combinational logic to determine its next state.
• If a register can be designed as a set of n identical cells, the register cell can be designed as a two-state sequential circuit.
• Next we will consider such as example.
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• Register Specification
• Diagram:
• Table:
Parallel Load Register with Synchronous Clear and Load
Operation CLS LDS Result (Next State)
Hold Reg 0 0 Data_out
Load Reg 0 1 Data_in
Clear Reg 1 - 0000000
CLSLDSCLK
Data_in (7:0)
Data_out(7:0)
Register(7:0)RESET(Async)
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Second Example:Register Cell Design• By definition, a register cell is a
sequential circuit that: contains one flip-flop (2 states) has the flip-flop output as the primary
external register output (Moore model)
• Cell Diagram: CLSLDS
CLK
Data_in (i)
Data_out(i)
Reg. Cell(i)
RESET(Async)
FF
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• Initial State:
• Add Load:
• Add Clear:
Second Example:State Diagram Design
A/0RESET
A/0RESETCLS,LDS,Data_in
A/0RESET B/11, 1
1, 0
B/10, 1, 1
0, 1, 0; 1, -, -
LDS,Data_in
0,1,0; 1,-,-
1, 11, 0State/Data_out(i)
0,1,1
State/Data_out(i)
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• Make the state unchanged (Hold Reg) by adding all unused input combinations for each state.
Second Example:State Diagram Design
A/0RESET
CLS,LDS,Data_in
B/10, 1, 1
0, 1, 0; 1, -, -
0,1,0; 1,-,-; 0,0,-
State/Data_out(i)
0,1,1; 0,0,-
SYEN 3330 Digital Systems Chapter 6-4 Page 23
Second Example: State Table
• From State Diagram: CLS, LDS, Data_in
Input:
State:
000 001 010 011 100 101 110 111 Output
A A A A B A A A A 0
B B B A B A A A A 1