synchronous logical networks ii digital systems m 1
TRANSCRIPT
Synchronous logical networks II
Digital Systems M
1
The value of base 4 counter CB2CLED is decoded and triggers a variation of FF1 (which selects the counter direction)) when 0 is reached if Down (3 if Up) The signal enabling the FF switch acting on the three ways MUX inverted is also the counter enable Therefore when the counter direction inversion is enabled the counter is disabled
2
Decoder
Counter
3
Behavioural simulation
4
A retriggerable one-shot (trigger =gt activation signal) is circuit which generates a Z output pulse lasting T (T presettable) after a positive edge of an input signal X When another positive edge of X occurs during the pulse Z the circuit extends the pulse Z of another T time Design a synchronous retriggerable one-shot (Moore) which using an input signal X asynchronous to a clock (of frequency f=1T) produces in a retriggerable way a pulse of 5T synchronous with the clock
Direct synthesis
3Normal one-shot Retriggerable one-shot
5
After the RESET and until a laquo1raquo occurs on X (trigger) the circuit output is 0 (the Reset acts on the output FF CLR) When X=1 the monoimpulsor sends a lsquo1rsquo to the output FF which swtches to 1 at the next clock positive edge (and keeps 1 because of the feedback OR) and at the same time resets and activates the counter (CLR asynchronous and counter CE = lsquo1rsquo) which will be active until the counter reaches 5 zeroing the circuit output In case of a further input trigger the output FF remains 1 and the counter is Reset (retrigger effect)
A type monoimpulsor
The simulation activates first a reset signal to reset the circuit state then after two clock periods two successive laquo1raquo inputs delayed of two periods are sent to the input It can ve verified that the output remains 1 for (2+5) clock periods The second part of the simulations deals with a not detected too short triggerIn the last part it is verified that the if the input is kept constant 1 the circuits doesnrsquot retrigger (a zero input must be inserted)
Post-Route Simulation
Behavioural Simulation
6
Retrigger ResetNon sampled
input5 periods
Waveforms generation
bull It is possbile to generate periodical waveforms through synchronous circuits whose period is an integer submultiple of che clock period
Example 1 by 2 frequency divider
D0k Q0k
CK D Q
CK Clock
Q
Example 2 generation of a waveform with 5T period (T period of the clock) whose output is high for 3T and low for 2T
Q0 Q1 Q2
CKCx5
C
B
A
01234
DecoderDemux (NB if the outputs were negative true a NAND instead of the OR should be used
Clock
ZZT
3T2T
3T
NB a logical network can only implement frequency dividers and never frequency multipliers (which can be achieved only through non linear analog circuits)
7
What sort of circuit is this
Clock
Q0
Q1
Q2
This is not a synchronous binary counter (it is called also an asynchronous counter) Its FFs do not use the same clock signal and this implies that among the FFs outputs a little disalignment takes place This sort of circuit canrsquot be synthesized as a synchronous circuit and a formal synthesis can be achieved only by considering the circuit as asynchronous that is by ldquoopeningrdquo the FFs (How many states in this case )
D0k Q0k
CK D0 Q0
CK
Q0D0k Q0k
CK D1 Q1
CK
D0k Q0k
CK D2 Q2
CKClock
NB The clock signal is not the same for all FFs (7493)
8
Xilinx asynchronous counter
9
How can a DFF catch a pulse shorter than a clock period
D2 Q2
Q2CKDFF Z
Clock
D1 Q1
Q1CKDFF
D0 Q0
Q0CKDFF
ldquo1rdquo CL
Ths short pulse is laquocapturedraquo by FF 0 (provided it is sufficiently wide for the FF technology) ndash which acts as an integrator ndash whose output is fed to the A type monoimpulsor The output of FF1 resets the FF0 (if CL is ldquopositiverdquotruerdquo)
Type A monoimpulsor ldquorevisitedrdquo
10
NBThis circuits and the previous one underline the fact no network is intrinsically synchronous and that in general it is almost always necessary the use of circuits of different nature This is in any case true because there are always interacting networks which use different clocks and input signals not synchronous
Can a problem arise since the Clear is asynchronous
bull A left (right) shift register is a register made of DFFs which at each clock positive edge copies the value of its right ((left) FF In the last FF on the right (left ) a ldquo0rdquo is copied This type of shift register is called laquologic shift registerraquo
Shift registers
D0kQ0k
CK DnQn
CK
D0kQ0k
CK Dn-1Qn-1
CK
D0kQ0k
CK Dn-2Qn-2
CK
D0kQ0k
CK D0Q0
CK
ldquo0rdquo
Left shift register
bull For the shift registers too there are many versions parallel in serial output serial input parallel output with or without reset load signals etc etc
bull A shift register is also a counter If upon a reset the input of FF0 is kept to 1 the shift register is incrementally filled with laquo1raquo the number of laquo1raquo (or the position of the leftmost 1) indicates the count value
bull Very often the same register can shift either left or right according to an input control signal This is achieved inserting a 2-way Mux before each D input whose inputs are the outputs of either the left or right FF (Qigrave+1 or Qigrave-1) With this configuration the shift register becomes an Updown counter
11
3-bit shift-register
DFFD Q
QR
A_RESET
DFFD Q
QR
A_RESET
DFFD Q
QR
A_RESET
IN
OUT2OUT1OUT0
CK
12
CK
IN
A_RESET
OUT1
OUT2
OUT0
13
3-bit shift-register
Example 74164 (serial IN-parallel OUT)
bull In this shift register for each positive clock edge (CP) data are shifted one position right (Q0 -gt Q1 Q1-gtQ2 etc) The register has a Master Reset (MR ndash negative true) and the bit inserted in Q0 FF is the AND of the two inputs Dsa e Dsb
bull It must be noticed that the shift operation corresponds arithmetically (without sign) to the division and multiplication by 2 Suppose that in Q0 the MSbit is stored and in Q7 the LSbit
011010102 = 10610
Shift left =gt x2 110101002 = 21210
Shift right =gt 2 001101012 = 5310 Weight 64 32 8 2
14
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
LR CK
0 1 1 0 1 0 1 0
bull There are also arithmetic shift registers In these right shift registers instead of inserting a ldquo0rdquo in the most left FF the same logic value is always inserted
Arithmetic Shift
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
D7 D6 D5 D4 D3 D2 D1 D0
ILDCK Example
11001010ArithmeticShift Right 11100101 interpreted as 2rsquos complement
C2 C2
001101102= 5410 000110112= 2710
bull The arithmetic right shift implements a division by 2 maintaining the sign Obviously the same holds for the positive numbers
negative numbers
15
Shifting right
Rotation
In the computers it is often necessary to implement a right or left rotation of a register content This is achieved by a feedback shift register
D0kQ0k
CK DnQn
CK
D0kQ0k
CK Dn-1Qn-1
CK
D0kQ0k
CK Dn-2Qn-2
CK
D0kQ0k
CK D0Q0
CK
Very often the direction must be programmable In this case the input of D0 (through a MUX 21) can be Q1 or Qnand so on
16
Shift register counters Shift register based counter through EX-OR feedback
Q2Q0
3 bit shift rightD
Q1
110 111 011 101 010 001
Disjoint state diagram
A n FF shift register with an EX-OR feedback (with variable inputs selected) is a NON binary counter for 2n-1 (provided it is not preset with all zeros)
000
100
17
Johnson Counter
000-gt100-gt110-gt111-gt011-gt001-gt000-gt
Disjoint state loop 101-gt010-gt101gt1
A Johnson counter with N FFs counts for 2N Since successive Johnson counter configurations differ by a single bit (adjacent configurations) it can be used for generating glitches-free waveforms
FFDD Q
QR
A_RESET
FFDD Q
QR
A_RESET
FFDD Q
QR
A_RESET
OUT2OUT1OUT0
CK
18
Single laquo1raquo ring counter (directly generating a 1 over n code)
FFDD Q
QR
RESET
FFDD Q
QR
RESET
FFDD Q
QPR
RESET
OUT3OUT1OUT0
CK
FFDD Q
QR
RESET
OUT2
0001-gt1000-gt0100-gt0010-gt0010
The ring counter needs N FFs in order to count for N (while with the binary counters the number of FF necessary for a N count is m= |log2N| that is the first integer greater or equal to log2N)
19
bull Synchronous networks exercises presented in the course are based on the state diagram but only for verification Synchronous network synthesis is made WITHOUT the state diagram usinghellip the brain only by decomposing the network in well know blocks (FFs combinatorial networks and ndash see later ndash counters shift registers etcetc)hellip
20
Design a synchronous logical network (SRL) able to detect palindrome 4 bit configurations (that is configurations that are identical when read left to right or viceversa) which are sequentially inserted in a shift register The D input is significant (and therefore valid for the sequence) only when the input Enable is 1 (whichs is not necessarilly the case for four consecutive input bits) The output P is 1 for a single period when a palindrome configuration is detected after a 4 bit sequence is received Then a new 4 bit sequence must be received (by E conditioned) and detected Direct synthesis
RSS
D
VP
D
VP
Exercise 4 synchronous
21
Enable E
To store a 4 bit sequence a Shift Register with Enable (CE) and Clear (CLR) is used A palindrome configuration is detected when the 1st bit is equal to the 4th bit and the 2nd bit is equal to the 3rd bit
22
A by 4 counter is used upon the 4th clock positive edge the network controls whether the configuration is palindrome The DFF after the decoding of 3 (that is when the counter becomes 0 anew) is used because the configuration control must be delayed un period The ENABLE signal is connected to both components (when 0 both the counter and the shift are disabled)
NB The first inserted bit is sampled when the counter is increased from 0 to 1
NB in this circuit Preset and Clear signals are not connected In Xilinx unconnected control signals are inactive
23
POST-ROUTE SIMULATION
Z output is delayed 10 ns from the clock positive edge because of the switch delay
24
Not valid inputEnable=0
Barrel shifter (rotor)A barrel shifter is a shift register able to shift ldquonrdquo positions in a single period its FFs contents A-H inputs are synchronously stored in the FFs when the LDST is activated When LDST is 0 upon each clock positive edge an anticlockwise n-positions rotation takes place where n is the binary value of S0 S1 and S2 signals For instance if rdquo01110000rdquo is rotated 4 positions at the first clock the content becomes ldquo00000111rdquo If then it is rotated 3 positions it becomes ldquo00111000rdquo
It must be noticed that the component is a register with laquonraquo 81 Muxs each one connected to the D inputs of the FFs The Mux control input value n is given by S0 S1 and S2
25
The circuit in figure is one of the eight 81 MUXs which select the values to be stored in the FFs
The last six right signals are the true and inverted selection signals (S1 S1 S2 S2 S3 e S3) for the 81 MUXs
Each 81 MUX is ORed with preset input value which is used together with LOAD (if LOAD=1 the OR preset value is 0) The FF output is ANDed with LOAD this zeroes all MUX outputs allowing the preset values to be stored in the FFs
The first left 8 signals are the values of the FF D inputs in the preceding period
Xilinx schematic
26
MUX
Preset value
27
Si -gt Mux 81 control signal of each FFAH -gt segnals for Preset Load
LDST=LOADWhen LDST signal is 0 all preset ANDs are zero If LDST is 1 the preset signals are enabled and all MUX outputs are zeroed
Preset AND
28
The LOAD (LDST) signal enables the preset inputs of the FFs (see the ANDs of the previous figure) and at the same time zeroes the output of the FFs (see the FFs cascaded ANDs) so as to select the preset value of the OR input
First 4 FFs Preset values
Xilinx schematicS2 S1 S0 selection signals
A B C HInput signals
LDST load signal
Clock
QA QB QC QH Outputs signals
29
Barrel Shifter
LDST=1upont the first clock positive edge the ldquo10010111rdquo value is loaded into the Barrel Shifter
The different values of Si (1 3 5) cause different device rotation Obviously with 8 sigle shifts the value becomes the initial value ldquo10010111rdquo again
A further active LDST loads a new valute into the the Barrel Shifter
This new value can be rotated again according to S signals
30
This is a typical example of how erroneous is not to laquobusraquo signals a-g qa-g and S0-2 It would have been possible to use a compact decomposable binary notation much easier to interpret where all single signals can be however displayed by laquoopeningraquo the bus
EPROM
X0nZ0m
y0kY0k
Clock
D0kQ0k
FFD0k
CK
D0kQ0kCK
EPROM based synchronous networks
Nowadays instead of the EPROMs PLAs (Programmable Logical Arrays) are used that is devices where the combinatorial functions are optimized (combinatorial functions implementations are not necessarily canonical) The basic principle is however the same
31
Design with Xilinx a synchronous logical network using 374 ALU 74181 a counter and other necessary devices which implements in sequence (after a START) signal the sum of two four bits absolute numbers (A and B) then 2rsquos complements the result then exchanges the two MSBits with the two LSBits and eventually divides arythmetically the result by 2
Example
A=1100 B=0101 =gt Sum 0001 Exchange =gt 0100 (410)2rsquos complement =gt 1100 (-410)Arithmetical division (right shift) by two =gt 1110 (-210)
The solution can be decomposed in three subsystems the control and decoding unit the datapath the input and output registersi
This is the basic architecture of the central unit of any computer
The only difference is that for the computers instead of a fixed sequence of elementary operations a new different sequence is generated for each instruction which must be executed
32
Exercise
33
The synchronous network of figure must add modulo 256 the 8 bit data received in parallel on lines D[70] The sum must be updated each clock and presented on the output lines OUT[70] In case the input data is 68H the sum must not be updated and the input data discarded In addition whenever 6 significant data have been received (that is excluding 68H) the output signal F must be set for one clock period during the reception of the sixth data A reset input is also available which zeroes the outputs and resets the data count Direct design
RSS
D[70] OUT[70]
A_RES
F
Exercise
Clock
34
RSSD[70] OUT[70]
A_RES
F
DEC_68 signal synthesis
DEC(68h)D[70] DEC_68
D[70]
A_RES
CLK
OUT[70]
RSS
D[70] OUT[70]
A_RES
F
35
Modulo 256 adder
Full Adder 8 bit
D[70]
A_RES
374
D
A_RES
Q
Q
CLK
0
1
DEC_68
OE
1
OUT[70]
CIN
0
A[70]
B[70]
36
F signal synthesis
8 bit counter
A_RES
A_RES
EN
RES
CLKU2 U1 U0
DEC(5h)
F
DEC_68
F
Synchronous RESET
37
Exercise
A synchronous sequential network must monitor the data received on the 8 lines D[70] the data received are significant only if N=1 The networks must count modulo 256 how many data are divisible by 4 while EN=1 (excluding 0) The network has two more inputs THREE e RESET The signal THREE when asserted indicates that the value for increasing the count (if the data is divisible by 4) must be 3 (on the contrary if THREE is 0 the count must be increased by 1) The synchronous RESET signal overrides all other signals Direct design
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
38
SynchronousSequentialNetwork
EN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70] (Count)
An input data is divisible by 4 of its two Lsbits (I1 and I0) are zero
An 8 integrated bit register is used for the solution
CK
39
Signal DEC(0) is 1 if all input bits are 0
A signal DIV4 decodes whether the input data is divisible by 4 and NOT zero
DIV4 = I1I0DEC(0)
A signal STORE indicates that EN=1 and the input datum is divisible by 4
STORE = ENDIV4
I[70] DEC(0) DEC(0)
40
REG8BIT
ENSTORE + RESET
CK
FA8 bit
A[70]
B[70]
S[70]
CinCout
THREE
lsquo0rsquo
1
0
lsquo3rsquo
lsquo1rsquo
D[70] Z[70] U[70]
RESET
1
0
lsquo0rsquo
8 Mux21
The FA adds 1 or 3 according to signal THREE (provided the input datum is divisble by 4 and is not 0)
41
Exercise
Design a synchronous sequential network which according to two programming bits X1 and X0 generates the following four output sequences of two bits (signals U1 and U0) which end always with 11
10-01-01-10-11 if X1=0 e X0=010-01-10-01-10-10-11 if X1=0 e X0=100-10-00-11 if X1=1 e X0=001-10-10-10-10-11 if X1=1 e X0=1
The programming signals X1 and X0 are significant only when the output is 11 The network has an synchronous RESET Direct synthesis
RSSCK
X1
X0
U1
U0
42
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5rArr10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
The SSN uses a modulo N counter with N coded by the two input signals X1 e X0 (sampled when U1U0=11)
For the solution we can use a module 8 counter with synchronous RES and a combinatorial network with X1 and X0 as inputs Since the signals X1 and X0 are significant only when U1U0 = 1 they must be sampled (X1_C e X0_C) through two flip-flops when the SSN output is U1U0 = 11 The signals U1 and U0 are the decoding of the module 8 counter status according to X1_C and X0_C
The counter must be reset when U1U0 = 11
RSSCK
X1
X0
U1
U0
43
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X1_SX1
X1_S e X0_S synthesis
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X0_SX0
44
U1 and U0 truth table
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5 rArr (0 to 4hellip)
10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
X1_S and X0_S values
Cont | 00 01 11 10000 | 00110 00110 00100 00101001 | 01001 01001 01010 01010010 | 01101 01110 01100 01110011 | 01110 10001 00011 10010 100 | 00011 10110 ------ 10110101 | ------ 11010 ------ 00011 110 | ------ 00011 ------ ------111 | ------ ------ ------ ------
Status U1U0
Is this synthesis of the network safe
No beacuse the donrsquot cares could keep the network stable out of the main cycles
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
- Slide 59
- Slide 60
- Slide 61
- Slide 62
- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
The value of base 4 counter CB2CLED is decoded and triggers a variation of FF1 (which selects the counter direction)) when 0 is reached if Down (3 if Up) The signal enabling the FF switch acting on the three ways MUX inverted is also the counter enable Therefore when the counter direction inversion is enabled the counter is disabled
2
Decoder
Counter
3
Behavioural simulation
4
A retriggerable one-shot (trigger =gt activation signal) is circuit which generates a Z output pulse lasting T (T presettable) after a positive edge of an input signal X When another positive edge of X occurs during the pulse Z the circuit extends the pulse Z of another T time Design a synchronous retriggerable one-shot (Moore) which using an input signal X asynchronous to a clock (of frequency f=1T) produces in a retriggerable way a pulse of 5T synchronous with the clock
Direct synthesis
3Normal one-shot Retriggerable one-shot
5
After the RESET and until a laquo1raquo occurs on X (trigger) the circuit output is 0 (the Reset acts on the output FF CLR) When X=1 the monoimpulsor sends a lsquo1rsquo to the output FF which swtches to 1 at the next clock positive edge (and keeps 1 because of the feedback OR) and at the same time resets and activates the counter (CLR asynchronous and counter CE = lsquo1rsquo) which will be active until the counter reaches 5 zeroing the circuit output In case of a further input trigger the output FF remains 1 and the counter is Reset (retrigger effect)
A type monoimpulsor
The simulation activates first a reset signal to reset the circuit state then after two clock periods two successive laquo1raquo inputs delayed of two periods are sent to the input It can ve verified that the output remains 1 for (2+5) clock periods The second part of the simulations deals with a not detected too short triggerIn the last part it is verified that the if the input is kept constant 1 the circuits doesnrsquot retrigger (a zero input must be inserted)
Post-Route Simulation
Behavioural Simulation
6
Retrigger ResetNon sampled
input5 periods
Waveforms generation
bull It is possbile to generate periodical waveforms through synchronous circuits whose period is an integer submultiple of che clock period
Example 1 by 2 frequency divider
D0k Q0k
CK D Q
CK Clock
Q
Example 2 generation of a waveform with 5T period (T period of the clock) whose output is high for 3T and low for 2T
Q0 Q1 Q2
CKCx5
C
B
A
01234
DecoderDemux (NB if the outputs were negative true a NAND instead of the OR should be used
Clock
ZZT
3T2T
3T
NB a logical network can only implement frequency dividers and never frequency multipliers (which can be achieved only through non linear analog circuits)
7
What sort of circuit is this
Clock
Q0
Q1
Q2
This is not a synchronous binary counter (it is called also an asynchronous counter) Its FFs do not use the same clock signal and this implies that among the FFs outputs a little disalignment takes place This sort of circuit canrsquot be synthesized as a synchronous circuit and a formal synthesis can be achieved only by considering the circuit as asynchronous that is by ldquoopeningrdquo the FFs (How many states in this case )
D0k Q0k
CK D0 Q0
CK
Q0D0k Q0k
CK D1 Q1
CK
D0k Q0k
CK D2 Q2
CKClock
NB The clock signal is not the same for all FFs (7493)
8
Xilinx asynchronous counter
9
How can a DFF catch a pulse shorter than a clock period
D2 Q2
Q2CKDFF Z
Clock
D1 Q1
Q1CKDFF
D0 Q0
Q0CKDFF
ldquo1rdquo CL
Ths short pulse is laquocapturedraquo by FF 0 (provided it is sufficiently wide for the FF technology) ndash which acts as an integrator ndash whose output is fed to the A type monoimpulsor The output of FF1 resets the FF0 (if CL is ldquopositiverdquotruerdquo)
Type A monoimpulsor ldquorevisitedrdquo
10
NBThis circuits and the previous one underline the fact no network is intrinsically synchronous and that in general it is almost always necessary the use of circuits of different nature This is in any case true because there are always interacting networks which use different clocks and input signals not synchronous
Can a problem arise since the Clear is asynchronous
bull A left (right) shift register is a register made of DFFs which at each clock positive edge copies the value of its right ((left) FF In the last FF on the right (left ) a ldquo0rdquo is copied This type of shift register is called laquologic shift registerraquo
Shift registers
D0kQ0k
CK DnQn
CK
D0kQ0k
CK Dn-1Qn-1
CK
D0kQ0k
CK Dn-2Qn-2
CK
D0kQ0k
CK D0Q0
CK
ldquo0rdquo
Left shift register
bull For the shift registers too there are many versions parallel in serial output serial input parallel output with or without reset load signals etc etc
bull A shift register is also a counter If upon a reset the input of FF0 is kept to 1 the shift register is incrementally filled with laquo1raquo the number of laquo1raquo (or the position of the leftmost 1) indicates the count value
bull Very often the same register can shift either left or right according to an input control signal This is achieved inserting a 2-way Mux before each D input whose inputs are the outputs of either the left or right FF (Qigrave+1 or Qigrave-1) With this configuration the shift register becomes an Updown counter
11
3-bit shift-register
DFFD Q
QR
A_RESET
DFFD Q
QR
A_RESET
DFFD Q
QR
A_RESET
IN
OUT2OUT1OUT0
CK
12
CK
IN
A_RESET
OUT1
OUT2
OUT0
13
3-bit shift-register
Example 74164 (serial IN-parallel OUT)
bull In this shift register for each positive clock edge (CP) data are shifted one position right (Q0 -gt Q1 Q1-gtQ2 etc) The register has a Master Reset (MR ndash negative true) and the bit inserted in Q0 FF is the AND of the two inputs Dsa e Dsb
bull It must be noticed that the shift operation corresponds arithmetically (without sign) to the division and multiplication by 2 Suppose that in Q0 the MSbit is stored and in Q7 the LSbit
011010102 = 10610
Shift left =gt x2 110101002 = 21210
Shift right =gt 2 001101012 = 5310 Weight 64 32 8 2
14
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
LR CK
0 1 1 0 1 0 1 0
bull There are also arithmetic shift registers In these right shift registers instead of inserting a ldquo0rdquo in the most left FF the same logic value is always inserted
Arithmetic Shift
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
D7 D6 D5 D4 D3 D2 D1 D0
ILDCK Example
11001010ArithmeticShift Right 11100101 interpreted as 2rsquos complement
C2 C2
001101102= 5410 000110112= 2710
bull The arithmetic right shift implements a division by 2 maintaining the sign Obviously the same holds for the positive numbers
negative numbers
15
Shifting right
Rotation
In the computers it is often necessary to implement a right or left rotation of a register content This is achieved by a feedback shift register
D0kQ0k
CK DnQn
CK
D0kQ0k
CK Dn-1Qn-1
CK
D0kQ0k
CK Dn-2Qn-2
CK
D0kQ0k
CK D0Q0
CK
Very often the direction must be programmable In this case the input of D0 (through a MUX 21) can be Q1 or Qnand so on
16
Shift register counters Shift register based counter through EX-OR feedback
Q2Q0
3 bit shift rightD
Q1
110 111 011 101 010 001
Disjoint state diagram
A n FF shift register with an EX-OR feedback (with variable inputs selected) is a NON binary counter for 2n-1 (provided it is not preset with all zeros)
000
100
17
Johnson Counter
000-gt100-gt110-gt111-gt011-gt001-gt000-gt
Disjoint state loop 101-gt010-gt101gt1
A Johnson counter with N FFs counts for 2N Since successive Johnson counter configurations differ by a single bit (adjacent configurations) it can be used for generating glitches-free waveforms
FFDD Q
QR
A_RESET
FFDD Q
QR
A_RESET
FFDD Q
QR
A_RESET
OUT2OUT1OUT0
CK
18
Single laquo1raquo ring counter (directly generating a 1 over n code)
FFDD Q
QR
RESET
FFDD Q
QR
RESET
FFDD Q
QPR
RESET
OUT3OUT1OUT0
CK
FFDD Q
QR
RESET
OUT2
0001-gt1000-gt0100-gt0010-gt0010
The ring counter needs N FFs in order to count for N (while with the binary counters the number of FF necessary for a N count is m= |log2N| that is the first integer greater or equal to log2N)
19
bull Synchronous networks exercises presented in the course are based on the state diagram but only for verification Synchronous network synthesis is made WITHOUT the state diagram usinghellip the brain only by decomposing the network in well know blocks (FFs combinatorial networks and ndash see later ndash counters shift registers etcetc)hellip
20
Design a synchronous logical network (SRL) able to detect palindrome 4 bit configurations (that is configurations that are identical when read left to right or viceversa) which are sequentially inserted in a shift register The D input is significant (and therefore valid for the sequence) only when the input Enable is 1 (whichs is not necessarilly the case for four consecutive input bits) The output P is 1 for a single period when a palindrome configuration is detected after a 4 bit sequence is received Then a new 4 bit sequence must be received (by E conditioned) and detected Direct synthesis
RSS
D
VP
D
VP
Exercise 4 synchronous
21
Enable E
To store a 4 bit sequence a Shift Register with Enable (CE) and Clear (CLR) is used A palindrome configuration is detected when the 1st bit is equal to the 4th bit and the 2nd bit is equal to the 3rd bit
22
A by 4 counter is used upon the 4th clock positive edge the network controls whether the configuration is palindrome The DFF after the decoding of 3 (that is when the counter becomes 0 anew) is used because the configuration control must be delayed un period The ENABLE signal is connected to both components (when 0 both the counter and the shift are disabled)
NB The first inserted bit is sampled when the counter is increased from 0 to 1
NB in this circuit Preset and Clear signals are not connected In Xilinx unconnected control signals are inactive
23
POST-ROUTE SIMULATION
Z output is delayed 10 ns from the clock positive edge because of the switch delay
24
Not valid inputEnable=0
Barrel shifter (rotor)A barrel shifter is a shift register able to shift ldquonrdquo positions in a single period its FFs contents A-H inputs are synchronously stored in the FFs when the LDST is activated When LDST is 0 upon each clock positive edge an anticlockwise n-positions rotation takes place where n is the binary value of S0 S1 and S2 signals For instance if rdquo01110000rdquo is rotated 4 positions at the first clock the content becomes ldquo00000111rdquo If then it is rotated 3 positions it becomes ldquo00111000rdquo
It must be noticed that the component is a register with laquonraquo 81 Muxs each one connected to the D inputs of the FFs The Mux control input value n is given by S0 S1 and S2
25
The circuit in figure is one of the eight 81 MUXs which select the values to be stored in the FFs
The last six right signals are the true and inverted selection signals (S1 S1 S2 S2 S3 e S3) for the 81 MUXs
Each 81 MUX is ORed with preset input value which is used together with LOAD (if LOAD=1 the OR preset value is 0) The FF output is ANDed with LOAD this zeroes all MUX outputs allowing the preset values to be stored in the FFs
The first left 8 signals are the values of the FF D inputs in the preceding period
Xilinx schematic
26
MUX
Preset value
27
Si -gt Mux 81 control signal of each FFAH -gt segnals for Preset Load
LDST=LOADWhen LDST signal is 0 all preset ANDs are zero If LDST is 1 the preset signals are enabled and all MUX outputs are zeroed
Preset AND
28
The LOAD (LDST) signal enables the preset inputs of the FFs (see the ANDs of the previous figure) and at the same time zeroes the output of the FFs (see the FFs cascaded ANDs) so as to select the preset value of the OR input
First 4 FFs Preset values
Xilinx schematicS2 S1 S0 selection signals
A B C HInput signals
LDST load signal
Clock
QA QB QC QH Outputs signals
29
Barrel Shifter
LDST=1upont the first clock positive edge the ldquo10010111rdquo value is loaded into the Barrel Shifter
The different values of Si (1 3 5) cause different device rotation Obviously with 8 sigle shifts the value becomes the initial value ldquo10010111rdquo again
A further active LDST loads a new valute into the the Barrel Shifter
This new value can be rotated again according to S signals
30
This is a typical example of how erroneous is not to laquobusraquo signals a-g qa-g and S0-2 It would have been possible to use a compact decomposable binary notation much easier to interpret where all single signals can be however displayed by laquoopeningraquo the bus
EPROM
X0nZ0m
y0kY0k
Clock
D0kQ0k
FFD0k
CK
D0kQ0kCK
EPROM based synchronous networks
Nowadays instead of the EPROMs PLAs (Programmable Logical Arrays) are used that is devices where the combinatorial functions are optimized (combinatorial functions implementations are not necessarily canonical) The basic principle is however the same
31
Design with Xilinx a synchronous logical network using 374 ALU 74181 a counter and other necessary devices which implements in sequence (after a START) signal the sum of two four bits absolute numbers (A and B) then 2rsquos complements the result then exchanges the two MSBits with the two LSBits and eventually divides arythmetically the result by 2
Example
A=1100 B=0101 =gt Sum 0001 Exchange =gt 0100 (410)2rsquos complement =gt 1100 (-410)Arithmetical division (right shift) by two =gt 1110 (-210)
The solution can be decomposed in three subsystems the control and decoding unit the datapath the input and output registersi
This is the basic architecture of the central unit of any computer
The only difference is that for the computers instead of a fixed sequence of elementary operations a new different sequence is generated for each instruction which must be executed
32
Exercise
33
The synchronous network of figure must add modulo 256 the 8 bit data received in parallel on lines D[70] The sum must be updated each clock and presented on the output lines OUT[70] In case the input data is 68H the sum must not be updated and the input data discarded In addition whenever 6 significant data have been received (that is excluding 68H) the output signal F must be set for one clock period during the reception of the sixth data A reset input is also available which zeroes the outputs and resets the data count Direct design
RSS
D[70] OUT[70]
A_RES
F
Exercise
Clock
34
RSSD[70] OUT[70]
A_RES
F
DEC_68 signal synthesis
DEC(68h)D[70] DEC_68
D[70]
A_RES
CLK
OUT[70]
RSS
D[70] OUT[70]
A_RES
F
35
Modulo 256 adder
Full Adder 8 bit
D[70]
A_RES
374
D
A_RES
Q
Q
CLK
0
1
DEC_68
OE
1
OUT[70]
CIN
0
A[70]
B[70]
36
F signal synthesis
8 bit counter
A_RES
A_RES
EN
RES
CLKU2 U1 U0
DEC(5h)
F
DEC_68
F
Synchronous RESET
37
Exercise
A synchronous sequential network must monitor the data received on the 8 lines D[70] the data received are significant only if N=1 The networks must count modulo 256 how many data are divisible by 4 while EN=1 (excluding 0) The network has two more inputs THREE e RESET The signal THREE when asserted indicates that the value for increasing the count (if the data is divisible by 4) must be 3 (on the contrary if THREE is 0 the count must be increased by 1) The synchronous RESET signal overrides all other signals Direct design
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
38
SynchronousSequentialNetwork
EN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70] (Count)
An input data is divisible by 4 of its two Lsbits (I1 and I0) are zero
An 8 integrated bit register is used for the solution
CK
39
Signal DEC(0) is 1 if all input bits are 0
A signal DIV4 decodes whether the input data is divisible by 4 and NOT zero
DIV4 = I1I0DEC(0)
A signal STORE indicates that EN=1 and the input datum is divisible by 4
STORE = ENDIV4
I[70] DEC(0) DEC(0)
40
REG8BIT
ENSTORE + RESET
CK
FA8 bit
A[70]
B[70]
S[70]
CinCout
THREE
lsquo0rsquo
1
0
lsquo3rsquo
lsquo1rsquo
D[70] Z[70] U[70]
RESET
1
0
lsquo0rsquo
8 Mux21
The FA adds 1 or 3 according to signal THREE (provided the input datum is divisble by 4 and is not 0)
41
Exercise
Design a synchronous sequential network which according to two programming bits X1 and X0 generates the following four output sequences of two bits (signals U1 and U0) which end always with 11
10-01-01-10-11 if X1=0 e X0=010-01-10-01-10-10-11 if X1=0 e X0=100-10-00-11 if X1=1 e X0=001-10-10-10-10-11 if X1=1 e X0=1
The programming signals X1 and X0 are significant only when the output is 11 The network has an synchronous RESET Direct synthesis
RSSCK
X1
X0
U1
U0
42
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5rArr10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
The SSN uses a modulo N counter with N coded by the two input signals X1 e X0 (sampled when U1U0=11)
For the solution we can use a module 8 counter with synchronous RES and a combinatorial network with X1 and X0 as inputs Since the signals X1 and X0 are significant only when U1U0 = 1 they must be sampled (X1_C e X0_C) through two flip-flops when the SSN output is U1U0 = 11 The signals U1 and U0 are the decoding of the module 8 counter status according to X1_C and X0_C
The counter must be reset when U1U0 = 11
RSSCK
X1
X0
U1
U0
43
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X1_SX1
X1_S e X0_S synthesis
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X0_SX0
44
U1 and U0 truth table
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5 rArr (0 to 4hellip)
10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
X1_S and X0_S values
Cont | 00 01 11 10000 | 00110 00110 00100 00101001 | 01001 01001 01010 01010010 | 01101 01110 01100 01110011 | 01110 10001 00011 10010 100 | 00011 10110 ------ 10110101 | ------ 11010 ------ 00011 110 | ------ 00011 ------ ------111 | ------ ------ ------ ------
Status U1U0
Is this synthesis of the network safe
No beacuse the donrsquot cares could keep the network stable out of the main cycles
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
- Slide 59
- Slide 60
- Slide 61
- Slide 62
- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
3
Behavioural simulation
4
A retriggerable one-shot (trigger =gt activation signal) is circuit which generates a Z output pulse lasting T (T presettable) after a positive edge of an input signal X When another positive edge of X occurs during the pulse Z the circuit extends the pulse Z of another T time Design a synchronous retriggerable one-shot (Moore) which using an input signal X asynchronous to a clock (of frequency f=1T) produces in a retriggerable way a pulse of 5T synchronous with the clock
Direct synthesis
3Normal one-shot Retriggerable one-shot
5
After the RESET and until a laquo1raquo occurs on X (trigger) the circuit output is 0 (the Reset acts on the output FF CLR) When X=1 the monoimpulsor sends a lsquo1rsquo to the output FF which swtches to 1 at the next clock positive edge (and keeps 1 because of the feedback OR) and at the same time resets and activates the counter (CLR asynchronous and counter CE = lsquo1rsquo) which will be active until the counter reaches 5 zeroing the circuit output In case of a further input trigger the output FF remains 1 and the counter is Reset (retrigger effect)
A type monoimpulsor
The simulation activates first a reset signal to reset the circuit state then after two clock periods two successive laquo1raquo inputs delayed of two periods are sent to the input It can ve verified that the output remains 1 for (2+5) clock periods The second part of the simulations deals with a not detected too short triggerIn the last part it is verified that the if the input is kept constant 1 the circuits doesnrsquot retrigger (a zero input must be inserted)
Post-Route Simulation
Behavioural Simulation
6
Retrigger ResetNon sampled
input5 periods
Waveforms generation
bull It is possbile to generate periodical waveforms through synchronous circuits whose period is an integer submultiple of che clock period
Example 1 by 2 frequency divider
D0k Q0k
CK D Q
CK Clock
Q
Example 2 generation of a waveform with 5T period (T period of the clock) whose output is high for 3T and low for 2T
Q0 Q1 Q2
CKCx5
C
B
A
01234
DecoderDemux (NB if the outputs were negative true a NAND instead of the OR should be used
Clock
ZZT
3T2T
3T
NB a logical network can only implement frequency dividers and never frequency multipliers (which can be achieved only through non linear analog circuits)
7
What sort of circuit is this
Clock
Q0
Q1
Q2
This is not a synchronous binary counter (it is called also an asynchronous counter) Its FFs do not use the same clock signal and this implies that among the FFs outputs a little disalignment takes place This sort of circuit canrsquot be synthesized as a synchronous circuit and a formal synthesis can be achieved only by considering the circuit as asynchronous that is by ldquoopeningrdquo the FFs (How many states in this case )
D0k Q0k
CK D0 Q0
CK
Q0D0k Q0k
CK D1 Q1
CK
D0k Q0k
CK D2 Q2
CKClock
NB The clock signal is not the same for all FFs (7493)
8
Xilinx asynchronous counter
9
How can a DFF catch a pulse shorter than a clock period
D2 Q2
Q2CKDFF Z
Clock
D1 Q1
Q1CKDFF
D0 Q0
Q0CKDFF
ldquo1rdquo CL
Ths short pulse is laquocapturedraquo by FF 0 (provided it is sufficiently wide for the FF technology) ndash which acts as an integrator ndash whose output is fed to the A type monoimpulsor The output of FF1 resets the FF0 (if CL is ldquopositiverdquotruerdquo)
Type A monoimpulsor ldquorevisitedrdquo
10
NBThis circuits and the previous one underline the fact no network is intrinsically synchronous and that in general it is almost always necessary the use of circuits of different nature This is in any case true because there are always interacting networks which use different clocks and input signals not synchronous
Can a problem arise since the Clear is asynchronous
bull A left (right) shift register is a register made of DFFs which at each clock positive edge copies the value of its right ((left) FF In the last FF on the right (left ) a ldquo0rdquo is copied This type of shift register is called laquologic shift registerraquo
Shift registers
D0kQ0k
CK DnQn
CK
D0kQ0k
CK Dn-1Qn-1
CK
D0kQ0k
CK Dn-2Qn-2
CK
D0kQ0k
CK D0Q0
CK
ldquo0rdquo
Left shift register
bull For the shift registers too there are many versions parallel in serial output serial input parallel output with or without reset load signals etc etc
bull A shift register is also a counter If upon a reset the input of FF0 is kept to 1 the shift register is incrementally filled with laquo1raquo the number of laquo1raquo (or the position of the leftmost 1) indicates the count value
bull Very often the same register can shift either left or right according to an input control signal This is achieved inserting a 2-way Mux before each D input whose inputs are the outputs of either the left or right FF (Qigrave+1 or Qigrave-1) With this configuration the shift register becomes an Updown counter
11
3-bit shift-register
DFFD Q
QR
A_RESET
DFFD Q
QR
A_RESET
DFFD Q
QR
A_RESET
IN
OUT2OUT1OUT0
CK
12
CK
IN
A_RESET
OUT1
OUT2
OUT0
13
3-bit shift-register
Example 74164 (serial IN-parallel OUT)
bull In this shift register for each positive clock edge (CP) data are shifted one position right (Q0 -gt Q1 Q1-gtQ2 etc) The register has a Master Reset (MR ndash negative true) and the bit inserted in Q0 FF is the AND of the two inputs Dsa e Dsb
bull It must be noticed that the shift operation corresponds arithmetically (without sign) to the division and multiplication by 2 Suppose that in Q0 the MSbit is stored and in Q7 the LSbit
011010102 = 10610
Shift left =gt x2 110101002 = 21210
Shift right =gt 2 001101012 = 5310 Weight 64 32 8 2
14
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
LR CK
0 1 1 0 1 0 1 0
bull There are also arithmetic shift registers In these right shift registers instead of inserting a ldquo0rdquo in the most left FF the same logic value is always inserted
Arithmetic Shift
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
D7 D6 D5 D4 D3 D2 D1 D0
ILDCK Example
11001010ArithmeticShift Right 11100101 interpreted as 2rsquos complement
C2 C2
001101102= 5410 000110112= 2710
bull The arithmetic right shift implements a division by 2 maintaining the sign Obviously the same holds for the positive numbers
negative numbers
15
Shifting right
Rotation
In the computers it is often necessary to implement a right or left rotation of a register content This is achieved by a feedback shift register
D0kQ0k
CK DnQn
CK
D0kQ0k
CK Dn-1Qn-1
CK
D0kQ0k
CK Dn-2Qn-2
CK
D0kQ0k
CK D0Q0
CK
Very often the direction must be programmable In this case the input of D0 (through a MUX 21) can be Q1 or Qnand so on
16
Shift register counters Shift register based counter through EX-OR feedback
Q2Q0
3 bit shift rightD
Q1
110 111 011 101 010 001
Disjoint state diagram
A n FF shift register with an EX-OR feedback (with variable inputs selected) is a NON binary counter for 2n-1 (provided it is not preset with all zeros)
000
100
17
Johnson Counter
000-gt100-gt110-gt111-gt011-gt001-gt000-gt
Disjoint state loop 101-gt010-gt101gt1
A Johnson counter with N FFs counts for 2N Since successive Johnson counter configurations differ by a single bit (adjacent configurations) it can be used for generating glitches-free waveforms
FFDD Q
QR
A_RESET
FFDD Q
QR
A_RESET
FFDD Q
QR
A_RESET
OUT2OUT1OUT0
CK
18
Single laquo1raquo ring counter (directly generating a 1 over n code)
FFDD Q
QR
RESET
FFDD Q
QR
RESET
FFDD Q
QPR
RESET
OUT3OUT1OUT0
CK
FFDD Q
QR
RESET
OUT2
0001-gt1000-gt0100-gt0010-gt0010
The ring counter needs N FFs in order to count for N (while with the binary counters the number of FF necessary for a N count is m= |log2N| that is the first integer greater or equal to log2N)
19
bull Synchronous networks exercises presented in the course are based on the state diagram but only for verification Synchronous network synthesis is made WITHOUT the state diagram usinghellip the brain only by decomposing the network in well know blocks (FFs combinatorial networks and ndash see later ndash counters shift registers etcetc)hellip
20
Design a synchronous logical network (SRL) able to detect palindrome 4 bit configurations (that is configurations that are identical when read left to right or viceversa) which are sequentially inserted in a shift register The D input is significant (and therefore valid for the sequence) only when the input Enable is 1 (whichs is not necessarilly the case for four consecutive input bits) The output P is 1 for a single period when a palindrome configuration is detected after a 4 bit sequence is received Then a new 4 bit sequence must be received (by E conditioned) and detected Direct synthesis
RSS
D
VP
D
VP
Exercise 4 synchronous
21
Enable E
To store a 4 bit sequence a Shift Register with Enable (CE) and Clear (CLR) is used A palindrome configuration is detected when the 1st bit is equal to the 4th bit and the 2nd bit is equal to the 3rd bit
22
A by 4 counter is used upon the 4th clock positive edge the network controls whether the configuration is palindrome The DFF after the decoding of 3 (that is when the counter becomes 0 anew) is used because the configuration control must be delayed un period The ENABLE signal is connected to both components (when 0 both the counter and the shift are disabled)
NB The first inserted bit is sampled when the counter is increased from 0 to 1
NB in this circuit Preset and Clear signals are not connected In Xilinx unconnected control signals are inactive
23
POST-ROUTE SIMULATION
Z output is delayed 10 ns from the clock positive edge because of the switch delay
24
Not valid inputEnable=0
Barrel shifter (rotor)A barrel shifter is a shift register able to shift ldquonrdquo positions in a single period its FFs contents A-H inputs are synchronously stored in the FFs when the LDST is activated When LDST is 0 upon each clock positive edge an anticlockwise n-positions rotation takes place where n is the binary value of S0 S1 and S2 signals For instance if rdquo01110000rdquo is rotated 4 positions at the first clock the content becomes ldquo00000111rdquo If then it is rotated 3 positions it becomes ldquo00111000rdquo
It must be noticed that the component is a register with laquonraquo 81 Muxs each one connected to the D inputs of the FFs The Mux control input value n is given by S0 S1 and S2
25
The circuit in figure is one of the eight 81 MUXs which select the values to be stored in the FFs
The last six right signals are the true and inverted selection signals (S1 S1 S2 S2 S3 e S3) for the 81 MUXs
Each 81 MUX is ORed with preset input value which is used together with LOAD (if LOAD=1 the OR preset value is 0) The FF output is ANDed with LOAD this zeroes all MUX outputs allowing the preset values to be stored in the FFs
The first left 8 signals are the values of the FF D inputs in the preceding period
Xilinx schematic
26
MUX
Preset value
27
Si -gt Mux 81 control signal of each FFAH -gt segnals for Preset Load
LDST=LOADWhen LDST signal is 0 all preset ANDs are zero If LDST is 1 the preset signals are enabled and all MUX outputs are zeroed
Preset AND
28
The LOAD (LDST) signal enables the preset inputs of the FFs (see the ANDs of the previous figure) and at the same time zeroes the output of the FFs (see the FFs cascaded ANDs) so as to select the preset value of the OR input
First 4 FFs Preset values
Xilinx schematicS2 S1 S0 selection signals
A B C HInput signals
LDST load signal
Clock
QA QB QC QH Outputs signals
29
Barrel Shifter
LDST=1upont the first clock positive edge the ldquo10010111rdquo value is loaded into the Barrel Shifter
The different values of Si (1 3 5) cause different device rotation Obviously with 8 sigle shifts the value becomes the initial value ldquo10010111rdquo again
A further active LDST loads a new valute into the the Barrel Shifter
This new value can be rotated again according to S signals
30
This is a typical example of how erroneous is not to laquobusraquo signals a-g qa-g and S0-2 It would have been possible to use a compact decomposable binary notation much easier to interpret where all single signals can be however displayed by laquoopeningraquo the bus
EPROM
X0nZ0m
y0kY0k
Clock
D0kQ0k
FFD0k
CK
D0kQ0kCK
EPROM based synchronous networks
Nowadays instead of the EPROMs PLAs (Programmable Logical Arrays) are used that is devices where the combinatorial functions are optimized (combinatorial functions implementations are not necessarily canonical) The basic principle is however the same
31
Design with Xilinx a synchronous logical network using 374 ALU 74181 a counter and other necessary devices which implements in sequence (after a START) signal the sum of two four bits absolute numbers (A and B) then 2rsquos complements the result then exchanges the two MSBits with the two LSBits and eventually divides arythmetically the result by 2
Example
A=1100 B=0101 =gt Sum 0001 Exchange =gt 0100 (410)2rsquos complement =gt 1100 (-410)Arithmetical division (right shift) by two =gt 1110 (-210)
The solution can be decomposed in three subsystems the control and decoding unit the datapath the input and output registersi
This is the basic architecture of the central unit of any computer
The only difference is that for the computers instead of a fixed sequence of elementary operations a new different sequence is generated for each instruction which must be executed
32
Exercise
33
The synchronous network of figure must add modulo 256 the 8 bit data received in parallel on lines D[70] The sum must be updated each clock and presented on the output lines OUT[70] In case the input data is 68H the sum must not be updated and the input data discarded In addition whenever 6 significant data have been received (that is excluding 68H) the output signal F must be set for one clock period during the reception of the sixth data A reset input is also available which zeroes the outputs and resets the data count Direct design
RSS
D[70] OUT[70]
A_RES
F
Exercise
Clock
34
RSSD[70] OUT[70]
A_RES
F
DEC_68 signal synthesis
DEC(68h)D[70] DEC_68
D[70]
A_RES
CLK
OUT[70]
RSS
D[70] OUT[70]
A_RES
F
35
Modulo 256 adder
Full Adder 8 bit
D[70]
A_RES
374
D
A_RES
Q
Q
CLK
0
1
DEC_68
OE
1
OUT[70]
CIN
0
A[70]
B[70]
36
F signal synthesis
8 bit counter
A_RES
A_RES
EN
RES
CLKU2 U1 U0
DEC(5h)
F
DEC_68
F
Synchronous RESET
37
Exercise
A synchronous sequential network must monitor the data received on the 8 lines D[70] the data received are significant only if N=1 The networks must count modulo 256 how many data are divisible by 4 while EN=1 (excluding 0) The network has two more inputs THREE e RESET The signal THREE when asserted indicates that the value for increasing the count (if the data is divisible by 4) must be 3 (on the contrary if THREE is 0 the count must be increased by 1) The synchronous RESET signal overrides all other signals Direct design
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
38
SynchronousSequentialNetwork
EN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70] (Count)
An input data is divisible by 4 of its two Lsbits (I1 and I0) are zero
An 8 integrated bit register is used for the solution
CK
39
Signal DEC(0) is 1 if all input bits are 0
A signal DIV4 decodes whether the input data is divisible by 4 and NOT zero
DIV4 = I1I0DEC(0)
A signal STORE indicates that EN=1 and the input datum is divisible by 4
STORE = ENDIV4
I[70] DEC(0) DEC(0)
40
REG8BIT
ENSTORE + RESET
CK
FA8 bit
A[70]
B[70]
S[70]
CinCout
THREE
lsquo0rsquo
1
0
lsquo3rsquo
lsquo1rsquo
D[70] Z[70] U[70]
RESET
1
0
lsquo0rsquo
8 Mux21
The FA adds 1 or 3 according to signal THREE (provided the input datum is divisble by 4 and is not 0)
41
Exercise
Design a synchronous sequential network which according to two programming bits X1 and X0 generates the following four output sequences of two bits (signals U1 and U0) which end always with 11
10-01-01-10-11 if X1=0 e X0=010-01-10-01-10-10-11 if X1=0 e X0=100-10-00-11 if X1=1 e X0=001-10-10-10-10-11 if X1=1 e X0=1
The programming signals X1 and X0 are significant only when the output is 11 The network has an synchronous RESET Direct synthesis
RSSCK
X1
X0
U1
U0
42
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5rArr10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
The SSN uses a modulo N counter with N coded by the two input signals X1 e X0 (sampled when U1U0=11)
For the solution we can use a module 8 counter with synchronous RES and a combinatorial network with X1 and X0 as inputs Since the signals X1 and X0 are significant only when U1U0 = 1 they must be sampled (X1_C e X0_C) through two flip-flops when the SSN output is U1U0 = 11 The signals U1 and U0 are the decoding of the module 8 counter status according to X1_C and X0_C
The counter must be reset when U1U0 = 11
RSSCK
X1
X0
U1
U0
43
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X1_SX1
X1_S e X0_S synthesis
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X0_SX0
44
U1 and U0 truth table
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5 rArr (0 to 4hellip)
10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
X1_S and X0_S values
Cont | 00 01 11 10000 | 00110 00110 00100 00101001 | 01001 01001 01010 01010010 | 01101 01110 01100 01110011 | 01110 10001 00011 10010 100 | 00011 10110 ------ 10110101 | ------ 11010 ------ 00011 110 | ------ 00011 ------ ------111 | ------ ------ ------ ------
Status U1U0
Is this synthesis of the network safe
No beacuse the donrsquot cares could keep the network stable out of the main cycles
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
- Slide 59
- Slide 60
- Slide 61
- Slide 62
- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
4
A retriggerable one-shot (trigger =gt activation signal) is circuit which generates a Z output pulse lasting T (T presettable) after a positive edge of an input signal X When another positive edge of X occurs during the pulse Z the circuit extends the pulse Z of another T time Design a synchronous retriggerable one-shot (Moore) which using an input signal X asynchronous to a clock (of frequency f=1T) produces in a retriggerable way a pulse of 5T synchronous with the clock
Direct synthesis
3Normal one-shot Retriggerable one-shot
5
After the RESET and until a laquo1raquo occurs on X (trigger) the circuit output is 0 (the Reset acts on the output FF CLR) When X=1 the monoimpulsor sends a lsquo1rsquo to the output FF which swtches to 1 at the next clock positive edge (and keeps 1 because of the feedback OR) and at the same time resets and activates the counter (CLR asynchronous and counter CE = lsquo1rsquo) which will be active until the counter reaches 5 zeroing the circuit output In case of a further input trigger the output FF remains 1 and the counter is Reset (retrigger effect)
A type monoimpulsor
The simulation activates first a reset signal to reset the circuit state then after two clock periods two successive laquo1raquo inputs delayed of two periods are sent to the input It can ve verified that the output remains 1 for (2+5) clock periods The second part of the simulations deals with a not detected too short triggerIn the last part it is verified that the if the input is kept constant 1 the circuits doesnrsquot retrigger (a zero input must be inserted)
Post-Route Simulation
Behavioural Simulation
6
Retrigger ResetNon sampled
input5 periods
Waveforms generation
bull It is possbile to generate periodical waveforms through synchronous circuits whose period is an integer submultiple of che clock period
Example 1 by 2 frequency divider
D0k Q0k
CK D Q
CK Clock
Q
Example 2 generation of a waveform with 5T period (T period of the clock) whose output is high for 3T and low for 2T
Q0 Q1 Q2
CKCx5
C
B
A
01234
DecoderDemux (NB if the outputs were negative true a NAND instead of the OR should be used
Clock
ZZT
3T2T
3T
NB a logical network can only implement frequency dividers and never frequency multipliers (which can be achieved only through non linear analog circuits)
7
What sort of circuit is this
Clock
Q0
Q1
Q2
This is not a synchronous binary counter (it is called also an asynchronous counter) Its FFs do not use the same clock signal and this implies that among the FFs outputs a little disalignment takes place This sort of circuit canrsquot be synthesized as a synchronous circuit and a formal synthesis can be achieved only by considering the circuit as asynchronous that is by ldquoopeningrdquo the FFs (How many states in this case )
D0k Q0k
CK D0 Q0
CK
Q0D0k Q0k
CK D1 Q1
CK
D0k Q0k
CK D2 Q2
CKClock
NB The clock signal is not the same for all FFs (7493)
8
Xilinx asynchronous counter
9
How can a DFF catch a pulse shorter than a clock period
D2 Q2
Q2CKDFF Z
Clock
D1 Q1
Q1CKDFF
D0 Q0
Q0CKDFF
ldquo1rdquo CL
Ths short pulse is laquocapturedraquo by FF 0 (provided it is sufficiently wide for the FF technology) ndash which acts as an integrator ndash whose output is fed to the A type monoimpulsor The output of FF1 resets the FF0 (if CL is ldquopositiverdquotruerdquo)
Type A monoimpulsor ldquorevisitedrdquo
10
NBThis circuits and the previous one underline the fact no network is intrinsically synchronous and that in general it is almost always necessary the use of circuits of different nature This is in any case true because there are always interacting networks which use different clocks and input signals not synchronous
Can a problem arise since the Clear is asynchronous
bull A left (right) shift register is a register made of DFFs which at each clock positive edge copies the value of its right ((left) FF In the last FF on the right (left ) a ldquo0rdquo is copied This type of shift register is called laquologic shift registerraquo
Shift registers
D0kQ0k
CK DnQn
CK
D0kQ0k
CK Dn-1Qn-1
CK
D0kQ0k
CK Dn-2Qn-2
CK
D0kQ0k
CK D0Q0
CK
ldquo0rdquo
Left shift register
bull For the shift registers too there are many versions parallel in serial output serial input parallel output with or without reset load signals etc etc
bull A shift register is also a counter If upon a reset the input of FF0 is kept to 1 the shift register is incrementally filled with laquo1raquo the number of laquo1raquo (or the position of the leftmost 1) indicates the count value
bull Very often the same register can shift either left or right according to an input control signal This is achieved inserting a 2-way Mux before each D input whose inputs are the outputs of either the left or right FF (Qigrave+1 or Qigrave-1) With this configuration the shift register becomes an Updown counter
11
3-bit shift-register
DFFD Q
QR
A_RESET
DFFD Q
QR
A_RESET
DFFD Q
QR
A_RESET
IN
OUT2OUT1OUT0
CK
12
CK
IN
A_RESET
OUT1
OUT2
OUT0
13
3-bit shift-register
Example 74164 (serial IN-parallel OUT)
bull In this shift register for each positive clock edge (CP) data are shifted one position right (Q0 -gt Q1 Q1-gtQ2 etc) The register has a Master Reset (MR ndash negative true) and the bit inserted in Q0 FF is the AND of the two inputs Dsa e Dsb
bull It must be noticed that the shift operation corresponds arithmetically (without sign) to the division and multiplication by 2 Suppose that in Q0 the MSbit is stored and in Q7 the LSbit
011010102 = 10610
Shift left =gt x2 110101002 = 21210
Shift right =gt 2 001101012 = 5310 Weight 64 32 8 2
14
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
LR CK
0 1 1 0 1 0 1 0
bull There are also arithmetic shift registers In these right shift registers instead of inserting a ldquo0rdquo in the most left FF the same logic value is always inserted
Arithmetic Shift
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
D7 D6 D5 D4 D3 D2 D1 D0
ILDCK Example
11001010ArithmeticShift Right 11100101 interpreted as 2rsquos complement
C2 C2
001101102= 5410 000110112= 2710
bull The arithmetic right shift implements a division by 2 maintaining the sign Obviously the same holds for the positive numbers
negative numbers
15
Shifting right
Rotation
In the computers it is often necessary to implement a right or left rotation of a register content This is achieved by a feedback shift register
D0kQ0k
CK DnQn
CK
D0kQ0k
CK Dn-1Qn-1
CK
D0kQ0k
CK Dn-2Qn-2
CK
D0kQ0k
CK D0Q0
CK
Very often the direction must be programmable In this case the input of D0 (through a MUX 21) can be Q1 or Qnand so on
16
Shift register counters Shift register based counter through EX-OR feedback
Q2Q0
3 bit shift rightD
Q1
110 111 011 101 010 001
Disjoint state diagram
A n FF shift register with an EX-OR feedback (with variable inputs selected) is a NON binary counter for 2n-1 (provided it is not preset with all zeros)
000
100
17
Johnson Counter
000-gt100-gt110-gt111-gt011-gt001-gt000-gt
Disjoint state loop 101-gt010-gt101gt1
A Johnson counter with N FFs counts for 2N Since successive Johnson counter configurations differ by a single bit (adjacent configurations) it can be used for generating glitches-free waveforms
FFDD Q
QR
A_RESET
FFDD Q
QR
A_RESET
FFDD Q
QR
A_RESET
OUT2OUT1OUT0
CK
18
Single laquo1raquo ring counter (directly generating a 1 over n code)
FFDD Q
QR
RESET
FFDD Q
QR
RESET
FFDD Q
QPR
RESET
OUT3OUT1OUT0
CK
FFDD Q
QR
RESET
OUT2
0001-gt1000-gt0100-gt0010-gt0010
The ring counter needs N FFs in order to count for N (while with the binary counters the number of FF necessary for a N count is m= |log2N| that is the first integer greater or equal to log2N)
19
bull Synchronous networks exercises presented in the course are based on the state diagram but only for verification Synchronous network synthesis is made WITHOUT the state diagram usinghellip the brain only by decomposing the network in well know blocks (FFs combinatorial networks and ndash see later ndash counters shift registers etcetc)hellip
20
Design a synchronous logical network (SRL) able to detect palindrome 4 bit configurations (that is configurations that are identical when read left to right or viceversa) which are sequentially inserted in a shift register The D input is significant (and therefore valid for the sequence) only when the input Enable is 1 (whichs is not necessarilly the case for four consecutive input bits) The output P is 1 for a single period when a palindrome configuration is detected after a 4 bit sequence is received Then a new 4 bit sequence must be received (by E conditioned) and detected Direct synthesis
RSS
D
VP
D
VP
Exercise 4 synchronous
21
Enable E
To store a 4 bit sequence a Shift Register with Enable (CE) and Clear (CLR) is used A palindrome configuration is detected when the 1st bit is equal to the 4th bit and the 2nd bit is equal to the 3rd bit
22
A by 4 counter is used upon the 4th clock positive edge the network controls whether the configuration is palindrome The DFF after the decoding of 3 (that is when the counter becomes 0 anew) is used because the configuration control must be delayed un period The ENABLE signal is connected to both components (when 0 both the counter and the shift are disabled)
NB The first inserted bit is sampled when the counter is increased from 0 to 1
NB in this circuit Preset and Clear signals are not connected In Xilinx unconnected control signals are inactive
23
POST-ROUTE SIMULATION
Z output is delayed 10 ns from the clock positive edge because of the switch delay
24
Not valid inputEnable=0
Barrel shifter (rotor)A barrel shifter is a shift register able to shift ldquonrdquo positions in a single period its FFs contents A-H inputs are synchronously stored in the FFs when the LDST is activated When LDST is 0 upon each clock positive edge an anticlockwise n-positions rotation takes place where n is the binary value of S0 S1 and S2 signals For instance if rdquo01110000rdquo is rotated 4 positions at the first clock the content becomes ldquo00000111rdquo If then it is rotated 3 positions it becomes ldquo00111000rdquo
It must be noticed that the component is a register with laquonraquo 81 Muxs each one connected to the D inputs of the FFs The Mux control input value n is given by S0 S1 and S2
25
The circuit in figure is one of the eight 81 MUXs which select the values to be stored in the FFs
The last six right signals are the true and inverted selection signals (S1 S1 S2 S2 S3 e S3) for the 81 MUXs
Each 81 MUX is ORed with preset input value which is used together with LOAD (if LOAD=1 the OR preset value is 0) The FF output is ANDed with LOAD this zeroes all MUX outputs allowing the preset values to be stored in the FFs
The first left 8 signals are the values of the FF D inputs in the preceding period
Xilinx schematic
26
MUX
Preset value
27
Si -gt Mux 81 control signal of each FFAH -gt segnals for Preset Load
LDST=LOADWhen LDST signal is 0 all preset ANDs are zero If LDST is 1 the preset signals are enabled and all MUX outputs are zeroed
Preset AND
28
The LOAD (LDST) signal enables the preset inputs of the FFs (see the ANDs of the previous figure) and at the same time zeroes the output of the FFs (see the FFs cascaded ANDs) so as to select the preset value of the OR input
First 4 FFs Preset values
Xilinx schematicS2 S1 S0 selection signals
A B C HInput signals
LDST load signal
Clock
QA QB QC QH Outputs signals
29
Barrel Shifter
LDST=1upont the first clock positive edge the ldquo10010111rdquo value is loaded into the Barrel Shifter
The different values of Si (1 3 5) cause different device rotation Obviously with 8 sigle shifts the value becomes the initial value ldquo10010111rdquo again
A further active LDST loads a new valute into the the Barrel Shifter
This new value can be rotated again according to S signals
30
This is a typical example of how erroneous is not to laquobusraquo signals a-g qa-g and S0-2 It would have been possible to use a compact decomposable binary notation much easier to interpret where all single signals can be however displayed by laquoopeningraquo the bus
EPROM
X0nZ0m
y0kY0k
Clock
D0kQ0k
FFD0k
CK
D0kQ0kCK
EPROM based synchronous networks
Nowadays instead of the EPROMs PLAs (Programmable Logical Arrays) are used that is devices where the combinatorial functions are optimized (combinatorial functions implementations are not necessarily canonical) The basic principle is however the same
31
Design with Xilinx a synchronous logical network using 374 ALU 74181 a counter and other necessary devices which implements in sequence (after a START) signal the sum of two four bits absolute numbers (A and B) then 2rsquos complements the result then exchanges the two MSBits with the two LSBits and eventually divides arythmetically the result by 2
Example
A=1100 B=0101 =gt Sum 0001 Exchange =gt 0100 (410)2rsquos complement =gt 1100 (-410)Arithmetical division (right shift) by two =gt 1110 (-210)
The solution can be decomposed in three subsystems the control and decoding unit the datapath the input and output registersi
This is the basic architecture of the central unit of any computer
The only difference is that for the computers instead of a fixed sequence of elementary operations a new different sequence is generated for each instruction which must be executed
32
Exercise
33
The synchronous network of figure must add modulo 256 the 8 bit data received in parallel on lines D[70] The sum must be updated each clock and presented on the output lines OUT[70] In case the input data is 68H the sum must not be updated and the input data discarded In addition whenever 6 significant data have been received (that is excluding 68H) the output signal F must be set for one clock period during the reception of the sixth data A reset input is also available which zeroes the outputs and resets the data count Direct design
RSS
D[70] OUT[70]
A_RES
F
Exercise
Clock
34
RSSD[70] OUT[70]
A_RES
F
DEC_68 signal synthesis
DEC(68h)D[70] DEC_68
D[70]
A_RES
CLK
OUT[70]
RSS
D[70] OUT[70]
A_RES
F
35
Modulo 256 adder
Full Adder 8 bit
D[70]
A_RES
374
D
A_RES
Q
Q
CLK
0
1
DEC_68
OE
1
OUT[70]
CIN
0
A[70]
B[70]
36
F signal synthesis
8 bit counter
A_RES
A_RES
EN
RES
CLKU2 U1 U0
DEC(5h)
F
DEC_68
F
Synchronous RESET
37
Exercise
A synchronous sequential network must monitor the data received on the 8 lines D[70] the data received are significant only if N=1 The networks must count modulo 256 how many data are divisible by 4 while EN=1 (excluding 0) The network has two more inputs THREE e RESET The signal THREE when asserted indicates that the value for increasing the count (if the data is divisible by 4) must be 3 (on the contrary if THREE is 0 the count must be increased by 1) The synchronous RESET signal overrides all other signals Direct design
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
38
SynchronousSequentialNetwork
EN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70] (Count)
An input data is divisible by 4 of its two Lsbits (I1 and I0) are zero
An 8 integrated bit register is used for the solution
CK
39
Signal DEC(0) is 1 if all input bits are 0
A signal DIV4 decodes whether the input data is divisible by 4 and NOT zero
DIV4 = I1I0DEC(0)
A signal STORE indicates that EN=1 and the input datum is divisible by 4
STORE = ENDIV4
I[70] DEC(0) DEC(0)
40
REG8BIT
ENSTORE + RESET
CK
FA8 bit
A[70]
B[70]
S[70]
CinCout
THREE
lsquo0rsquo
1
0
lsquo3rsquo
lsquo1rsquo
D[70] Z[70] U[70]
RESET
1
0
lsquo0rsquo
8 Mux21
The FA adds 1 or 3 according to signal THREE (provided the input datum is divisble by 4 and is not 0)
41
Exercise
Design a synchronous sequential network which according to two programming bits X1 and X0 generates the following four output sequences of two bits (signals U1 and U0) which end always with 11
10-01-01-10-11 if X1=0 e X0=010-01-10-01-10-10-11 if X1=0 e X0=100-10-00-11 if X1=1 e X0=001-10-10-10-10-11 if X1=1 e X0=1
The programming signals X1 and X0 are significant only when the output is 11 The network has an synchronous RESET Direct synthesis
RSSCK
X1
X0
U1
U0
42
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5rArr10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
The SSN uses a modulo N counter with N coded by the two input signals X1 e X0 (sampled when U1U0=11)
For the solution we can use a module 8 counter with synchronous RES and a combinatorial network with X1 and X0 as inputs Since the signals X1 and X0 are significant only when U1U0 = 1 they must be sampled (X1_C e X0_C) through two flip-flops when the SSN output is U1U0 = 11 The signals U1 and U0 are the decoding of the module 8 counter status according to X1_C and X0_C
The counter must be reset when U1U0 = 11
RSSCK
X1
X0
U1
U0
43
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X1_SX1
X1_S e X0_S synthesis
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X0_SX0
44
U1 and U0 truth table
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5 rArr (0 to 4hellip)
10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
X1_S and X0_S values
Cont | 00 01 11 10000 | 00110 00110 00100 00101001 | 01001 01001 01010 01010010 | 01101 01110 01100 01110011 | 01110 10001 00011 10010 100 | 00011 10110 ------ 10110101 | ------ 11010 ------ 00011 110 | ------ 00011 ------ ------111 | ------ ------ ------ ------
Status U1U0
Is this synthesis of the network safe
No beacuse the donrsquot cares could keep the network stable out of the main cycles
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
- Slide 59
- Slide 60
- Slide 61
- Slide 62
- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
5
After the RESET and until a laquo1raquo occurs on X (trigger) the circuit output is 0 (the Reset acts on the output FF CLR) When X=1 the monoimpulsor sends a lsquo1rsquo to the output FF which swtches to 1 at the next clock positive edge (and keeps 1 because of the feedback OR) and at the same time resets and activates the counter (CLR asynchronous and counter CE = lsquo1rsquo) which will be active until the counter reaches 5 zeroing the circuit output In case of a further input trigger the output FF remains 1 and the counter is Reset (retrigger effect)
A type monoimpulsor
The simulation activates first a reset signal to reset the circuit state then after two clock periods two successive laquo1raquo inputs delayed of two periods are sent to the input It can ve verified that the output remains 1 for (2+5) clock periods The second part of the simulations deals with a not detected too short triggerIn the last part it is verified that the if the input is kept constant 1 the circuits doesnrsquot retrigger (a zero input must be inserted)
Post-Route Simulation
Behavioural Simulation
6
Retrigger ResetNon sampled
input5 periods
Waveforms generation
bull It is possbile to generate periodical waveforms through synchronous circuits whose period is an integer submultiple of che clock period
Example 1 by 2 frequency divider
D0k Q0k
CK D Q
CK Clock
Q
Example 2 generation of a waveform with 5T period (T period of the clock) whose output is high for 3T and low for 2T
Q0 Q1 Q2
CKCx5
C
B
A
01234
DecoderDemux (NB if the outputs were negative true a NAND instead of the OR should be used
Clock
ZZT
3T2T
3T
NB a logical network can only implement frequency dividers and never frequency multipliers (which can be achieved only through non linear analog circuits)
7
What sort of circuit is this
Clock
Q0
Q1
Q2
This is not a synchronous binary counter (it is called also an asynchronous counter) Its FFs do not use the same clock signal and this implies that among the FFs outputs a little disalignment takes place This sort of circuit canrsquot be synthesized as a synchronous circuit and a formal synthesis can be achieved only by considering the circuit as asynchronous that is by ldquoopeningrdquo the FFs (How many states in this case )
D0k Q0k
CK D0 Q0
CK
Q0D0k Q0k
CK D1 Q1
CK
D0k Q0k
CK D2 Q2
CKClock
NB The clock signal is not the same for all FFs (7493)
8
Xilinx asynchronous counter
9
How can a DFF catch a pulse shorter than a clock period
D2 Q2
Q2CKDFF Z
Clock
D1 Q1
Q1CKDFF
D0 Q0
Q0CKDFF
ldquo1rdquo CL
Ths short pulse is laquocapturedraquo by FF 0 (provided it is sufficiently wide for the FF technology) ndash which acts as an integrator ndash whose output is fed to the A type monoimpulsor The output of FF1 resets the FF0 (if CL is ldquopositiverdquotruerdquo)
Type A monoimpulsor ldquorevisitedrdquo
10
NBThis circuits and the previous one underline the fact no network is intrinsically synchronous and that in general it is almost always necessary the use of circuits of different nature This is in any case true because there are always interacting networks which use different clocks and input signals not synchronous
Can a problem arise since the Clear is asynchronous
bull A left (right) shift register is a register made of DFFs which at each clock positive edge copies the value of its right ((left) FF In the last FF on the right (left ) a ldquo0rdquo is copied This type of shift register is called laquologic shift registerraquo
Shift registers
D0kQ0k
CK DnQn
CK
D0kQ0k
CK Dn-1Qn-1
CK
D0kQ0k
CK Dn-2Qn-2
CK
D0kQ0k
CK D0Q0
CK
ldquo0rdquo
Left shift register
bull For the shift registers too there are many versions parallel in serial output serial input parallel output with or without reset load signals etc etc
bull A shift register is also a counter If upon a reset the input of FF0 is kept to 1 the shift register is incrementally filled with laquo1raquo the number of laquo1raquo (or the position of the leftmost 1) indicates the count value
bull Very often the same register can shift either left or right according to an input control signal This is achieved inserting a 2-way Mux before each D input whose inputs are the outputs of either the left or right FF (Qigrave+1 or Qigrave-1) With this configuration the shift register becomes an Updown counter
11
3-bit shift-register
DFFD Q
QR
A_RESET
DFFD Q
QR
A_RESET
DFFD Q
QR
A_RESET
IN
OUT2OUT1OUT0
CK
12
CK
IN
A_RESET
OUT1
OUT2
OUT0
13
3-bit shift-register
Example 74164 (serial IN-parallel OUT)
bull In this shift register for each positive clock edge (CP) data are shifted one position right (Q0 -gt Q1 Q1-gtQ2 etc) The register has a Master Reset (MR ndash negative true) and the bit inserted in Q0 FF is the AND of the two inputs Dsa e Dsb
bull It must be noticed that the shift operation corresponds arithmetically (without sign) to the division and multiplication by 2 Suppose that in Q0 the MSbit is stored and in Q7 the LSbit
011010102 = 10610
Shift left =gt x2 110101002 = 21210
Shift right =gt 2 001101012 = 5310 Weight 64 32 8 2
14
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
LR CK
0 1 1 0 1 0 1 0
bull There are also arithmetic shift registers In these right shift registers instead of inserting a ldquo0rdquo in the most left FF the same logic value is always inserted
Arithmetic Shift
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
D7 D6 D5 D4 D3 D2 D1 D0
ILDCK Example
11001010ArithmeticShift Right 11100101 interpreted as 2rsquos complement
C2 C2
001101102= 5410 000110112= 2710
bull The arithmetic right shift implements a division by 2 maintaining the sign Obviously the same holds for the positive numbers
negative numbers
15
Shifting right
Rotation
In the computers it is often necessary to implement a right or left rotation of a register content This is achieved by a feedback shift register
D0kQ0k
CK DnQn
CK
D0kQ0k
CK Dn-1Qn-1
CK
D0kQ0k
CK Dn-2Qn-2
CK
D0kQ0k
CK D0Q0
CK
Very often the direction must be programmable In this case the input of D0 (through a MUX 21) can be Q1 or Qnand so on
16
Shift register counters Shift register based counter through EX-OR feedback
Q2Q0
3 bit shift rightD
Q1
110 111 011 101 010 001
Disjoint state diagram
A n FF shift register with an EX-OR feedback (with variable inputs selected) is a NON binary counter for 2n-1 (provided it is not preset with all zeros)
000
100
17
Johnson Counter
000-gt100-gt110-gt111-gt011-gt001-gt000-gt
Disjoint state loop 101-gt010-gt101gt1
A Johnson counter with N FFs counts for 2N Since successive Johnson counter configurations differ by a single bit (adjacent configurations) it can be used for generating glitches-free waveforms
FFDD Q
QR
A_RESET
FFDD Q
QR
A_RESET
FFDD Q
QR
A_RESET
OUT2OUT1OUT0
CK
18
Single laquo1raquo ring counter (directly generating a 1 over n code)
FFDD Q
QR
RESET
FFDD Q
QR
RESET
FFDD Q
QPR
RESET
OUT3OUT1OUT0
CK
FFDD Q
QR
RESET
OUT2
0001-gt1000-gt0100-gt0010-gt0010
The ring counter needs N FFs in order to count for N (while with the binary counters the number of FF necessary for a N count is m= |log2N| that is the first integer greater or equal to log2N)
19
bull Synchronous networks exercises presented in the course are based on the state diagram but only for verification Synchronous network synthesis is made WITHOUT the state diagram usinghellip the brain only by decomposing the network in well know blocks (FFs combinatorial networks and ndash see later ndash counters shift registers etcetc)hellip
20
Design a synchronous logical network (SRL) able to detect palindrome 4 bit configurations (that is configurations that are identical when read left to right or viceversa) which are sequentially inserted in a shift register The D input is significant (and therefore valid for the sequence) only when the input Enable is 1 (whichs is not necessarilly the case for four consecutive input bits) The output P is 1 for a single period when a palindrome configuration is detected after a 4 bit sequence is received Then a new 4 bit sequence must be received (by E conditioned) and detected Direct synthesis
RSS
D
VP
D
VP
Exercise 4 synchronous
21
Enable E
To store a 4 bit sequence a Shift Register with Enable (CE) and Clear (CLR) is used A palindrome configuration is detected when the 1st bit is equal to the 4th bit and the 2nd bit is equal to the 3rd bit
22
A by 4 counter is used upon the 4th clock positive edge the network controls whether the configuration is palindrome The DFF after the decoding of 3 (that is when the counter becomes 0 anew) is used because the configuration control must be delayed un period The ENABLE signal is connected to both components (when 0 both the counter and the shift are disabled)
NB The first inserted bit is sampled when the counter is increased from 0 to 1
NB in this circuit Preset and Clear signals are not connected In Xilinx unconnected control signals are inactive
23
POST-ROUTE SIMULATION
Z output is delayed 10 ns from the clock positive edge because of the switch delay
24
Not valid inputEnable=0
Barrel shifter (rotor)A barrel shifter is a shift register able to shift ldquonrdquo positions in a single period its FFs contents A-H inputs are synchronously stored in the FFs when the LDST is activated When LDST is 0 upon each clock positive edge an anticlockwise n-positions rotation takes place where n is the binary value of S0 S1 and S2 signals For instance if rdquo01110000rdquo is rotated 4 positions at the first clock the content becomes ldquo00000111rdquo If then it is rotated 3 positions it becomes ldquo00111000rdquo
It must be noticed that the component is a register with laquonraquo 81 Muxs each one connected to the D inputs of the FFs The Mux control input value n is given by S0 S1 and S2
25
The circuit in figure is one of the eight 81 MUXs which select the values to be stored in the FFs
The last six right signals are the true and inverted selection signals (S1 S1 S2 S2 S3 e S3) for the 81 MUXs
Each 81 MUX is ORed with preset input value which is used together with LOAD (if LOAD=1 the OR preset value is 0) The FF output is ANDed with LOAD this zeroes all MUX outputs allowing the preset values to be stored in the FFs
The first left 8 signals are the values of the FF D inputs in the preceding period
Xilinx schematic
26
MUX
Preset value
27
Si -gt Mux 81 control signal of each FFAH -gt segnals for Preset Load
LDST=LOADWhen LDST signal is 0 all preset ANDs are zero If LDST is 1 the preset signals are enabled and all MUX outputs are zeroed
Preset AND
28
The LOAD (LDST) signal enables the preset inputs of the FFs (see the ANDs of the previous figure) and at the same time zeroes the output of the FFs (see the FFs cascaded ANDs) so as to select the preset value of the OR input
First 4 FFs Preset values
Xilinx schematicS2 S1 S0 selection signals
A B C HInput signals
LDST load signal
Clock
QA QB QC QH Outputs signals
29
Barrel Shifter
LDST=1upont the first clock positive edge the ldquo10010111rdquo value is loaded into the Barrel Shifter
The different values of Si (1 3 5) cause different device rotation Obviously with 8 sigle shifts the value becomes the initial value ldquo10010111rdquo again
A further active LDST loads a new valute into the the Barrel Shifter
This new value can be rotated again according to S signals
30
This is a typical example of how erroneous is not to laquobusraquo signals a-g qa-g and S0-2 It would have been possible to use a compact decomposable binary notation much easier to interpret where all single signals can be however displayed by laquoopeningraquo the bus
EPROM
X0nZ0m
y0kY0k
Clock
D0kQ0k
FFD0k
CK
D0kQ0kCK
EPROM based synchronous networks
Nowadays instead of the EPROMs PLAs (Programmable Logical Arrays) are used that is devices where the combinatorial functions are optimized (combinatorial functions implementations are not necessarily canonical) The basic principle is however the same
31
Design with Xilinx a synchronous logical network using 374 ALU 74181 a counter and other necessary devices which implements in sequence (after a START) signal the sum of two four bits absolute numbers (A and B) then 2rsquos complements the result then exchanges the two MSBits with the two LSBits and eventually divides arythmetically the result by 2
Example
A=1100 B=0101 =gt Sum 0001 Exchange =gt 0100 (410)2rsquos complement =gt 1100 (-410)Arithmetical division (right shift) by two =gt 1110 (-210)
The solution can be decomposed in three subsystems the control and decoding unit the datapath the input and output registersi
This is the basic architecture of the central unit of any computer
The only difference is that for the computers instead of a fixed sequence of elementary operations a new different sequence is generated for each instruction which must be executed
32
Exercise
33
The synchronous network of figure must add modulo 256 the 8 bit data received in parallel on lines D[70] The sum must be updated each clock and presented on the output lines OUT[70] In case the input data is 68H the sum must not be updated and the input data discarded In addition whenever 6 significant data have been received (that is excluding 68H) the output signal F must be set for one clock period during the reception of the sixth data A reset input is also available which zeroes the outputs and resets the data count Direct design
RSS
D[70] OUT[70]
A_RES
F
Exercise
Clock
34
RSSD[70] OUT[70]
A_RES
F
DEC_68 signal synthesis
DEC(68h)D[70] DEC_68
D[70]
A_RES
CLK
OUT[70]
RSS
D[70] OUT[70]
A_RES
F
35
Modulo 256 adder
Full Adder 8 bit
D[70]
A_RES
374
D
A_RES
Q
Q
CLK
0
1
DEC_68
OE
1
OUT[70]
CIN
0
A[70]
B[70]
36
F signal synthesis
8 bit counter
A_RES
A_RES
EN
RES
CLKU2 U1 U0
DEC(5h)
F
DEC_68
F
Synchronous RESET
37
Exercise
A synchronous sequential network must monitor the data received on the 8 lines D[70] the data received are significant only if N=1 The networks must count modulo 256 how many data are divisible by 4 while EN=1 (excluding 0) The network has two more inputs THREE e RESET The signal THREE when asserted indicates that the value for increasing the count (if the data is divisible by 4) must be 3 (on the contrary if THREE is 0 the count must be increased by 1) The synchronous RESET signal overrides all other signals Direct design
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
38
SynchronousSequentialNetwork
EN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70] (Count)
An input data is divisible by 4 of its two Lsbits (I1 and I0) are zero
An 8 integrated bit register is used for the solution
CK
39
Signal DEC(0) is 1 if all input bits are 0
A signal DIV4 decodes whether the input data is divisible by 4 and NOT zero
DIV4 = I1I0DEC(0)
A signal STORE indicates that EN=1 and the input datum is divisible by 4
STORE = ENDIV4
I[70] DEC(0) DEC(0)
40
REG8BIT
ENSTORE + RESET
CK
FA8 bit
A[70]
B[70]
S[70]
CinCout
THREE
lsquo0rsquo
1
0
lsquo3rsquo
lsquo1rsquo
D[70] Z[70] U[70]
RESET
1
0
lsquo0rsquo
8 Mux21
The FA adds 1 or 3 according to signal THREE (provided the input datum is divisble by 4 and is not 0)
41
Exercise
Design a synchronous sequential network which according to two programming bits X1 and X0 generates the following four output sequences of two bits (signals U1 and U0) which end always with 11
10-01-01-10-11 if X1=0 e X0=010-01-10-01-10-10-11 if X1=0 e X0=100-10-00-11 if X1=1 e X0=001-10-10-10-10-11 if X1=1 e X0=1
The programming signals X1 and X0 are significant only when the output is 11 The network has an synchronous RESET Direct synthesis
RSSCK
X1
X0
U1
U0
42
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5rArr10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
The SSN uses a modulo N counter with N coded by the two input signals X1 e X0 (sampled when U1U0=11)
For the solution we can use a module 8 counter with synchronous RES and a combinatorial network with X1 and X0 as inputs Since the signals X1 and X0 are significant only when U1U0 = 1 they must be sampled (X1_C e X0_C) through two flip-flops when the SSN output is U1U0 = 11 The signals U1 and U0 are the decoding of the module 8 counter status according to X1_C and X0_C
The counter must be reset when U1U0 = 11
RSSCK
X1
X0
U1
U0
43
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X1_SX1
X1_S e X0_S synthesis
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X0_SX0
44
U1 and U0 truth table
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5 rArr (0 to 4hellip)
10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
X1_S and X0_S values
Cont | 00 01 11 10000 | 00110 00110 00100 00101001 | 01001 01001 01010 01010010 | 01101 01110 01100 01110011 | 01110 10001 00011 10010 100 | 00011 10110 ------ 10110101 | ------ 11010 ------ 00011 110 | ------ 00011 ------ ------111 | ------ ------ ------ ------
Status U1U0
Is this synthesis of the network safe
No beacuse the donrsquot cares could keep the network stable out of the main cycles
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
- Slide 59
- Slide 60
- Slide 61
- Slide 62
- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
The simulation activates first a reset signal to reset the circuit state then after two clock periods two successive laquo1raquo inputs delayed of two periods are sent to the input It can ve verified that the output remains 1 for (2+5) clock periods The second part of the simulations deals with a not detected too short triggerIn the last part it is verified that the if the input is kept constant 1 the circuits doesnrsquot retrigger (a zero input must be inserted)
Post-Route Simulation
Behavioural Simulation
6
Retrigger ResetNon sampled
input5 periods
Waveforms generation
bull It is possbile to generate periodical waveforms through synchronous circuits whose period is an integer submultiple of che clock period
Example 1 by 2 frequency divider
D0k Q0k
CK D Q
CK Clock
Q
Example 2 generation of a waveform with 5T period (T period of the clock) whose output is high for 3T and low for 2T
Q0 Q1 Q2
CKCx5
C
B
A
01234
DecoderDemux (NB if the outputs were negative true a NAND instead of the OR should be used
Clock
ZZT
3T2T
3T
NB a logical network can only implement frequency dividers and never frequency multipliers (which can be achieved only through non linear analog circuits)
7
What sort of circuit is this
Clock
Q0
Q1
Q2
This is not a synchronous binary counter (it is called also an asynchronous counter) Its FFs do not use the same clock signal and this implies that among the FFs outputs a little disalignment takes place This sort of circuit canrsquot be synthesized as a synchronous circuit and a formal synthesis can be achieved only by considering the circuit as asynchronous that is by ldquoopeningrdquo the FFs (How many states in this case )
D0k Q0k
CK D0 Q0
CK
Q0D0k Q0k
CK D1 Q1
CK
D0k Q0k
CK D2 Q2
CKClock
NB The clock signal is not the same for all FFs (7493)
8
Xilinx asynchronous counter
9
How can a DFF catch a pulse shorter than a clock period
D2 Q2
Q2CKDFF Z
Clock
D1 Q1
Q1CKDFF
D0 Q0
Q0CKDFF
ldquo1rdquo CL
Ths short pulse is laquocapturedraquo by FF 0 (provided it is sufficiently wide for the FF technology) ndash which acts as an integrator ndash whose output is fed to the A type monoimpulsor The output of FF1 resets the FF0 (if CL is ldquopositiverdquotruerdquo)
Type A monoimpulsor ldquorevisitedrdquo
10
NBThis circuits and the previous one underline the fact no network is intrinsically synchronous and that in general it is almost always necessary the use of circuits of different nature This is in any case true because there are always interacting networks which use different clocks and input signals not synchronous
Can a problem arise since the Clear is asynchronous
bull A left (right) shift register is a register made of DFFs which at each clock positive edge copies the value of its right ((left) FF In the last FF on the right (left ) a ldquo0rdquo is copied This type of shift register is called laquologic shift registerraquo
Shift registers
D0kQ0k
CK DnQn
CK
D0kQ0k
CK Dn-1Qn-1
CK
D0kQ0k
CK Dn-2Qn-2
CK
D0kQ0k
CK D0Q0
CK
ldquo0rdquo
Left shift register
bull For the shift registers too there are many versions parallel in serial output serial input parallel output with or without reset load signals etc etc
bull A shift register is also a counter If upon a reset the input of FF0 is kept to 1 the shift register is incrementally filled with laquo1raquo the number of laquo1raquo (or the position of the leftmost 1) indicates the count value
bull Very often the same register can shift either left or right according to an input control signal This is achieved inserting a 2-way Mux before each D input whose inputs are the outputs of either the left or right FF (Qigrave+1 or Qigrave-1) With this configuration the shift register becomes an Updown counter
11
3-bit shift-register
DFFD Q
QR
A_RESET
DFFD Q
QR
A_RESET
DFFD Q
QR
A_RESET
IN
OUT2OUT1OUT0
CK
12
CK
IN
A_RESET
OUT1
OUT2
OUT0
13
3-bit shift-register
Example 74164 (serial IN-parallel OUT)
bull In this shift register for each positive clock edge (CP) data are shifted one position right (Q0 -gt Q1 Q1-gtQ2 etc) The register has a Master Reset (MR ndash negative true) and the bit inserted in Q0 FF is the AND of the two inputs Dsa e Dsb
bull It must be noticed that the shift operation corresponds arithmetically (without sign) to the division and multiplication by 2 Suppose that in Q0 the MSbit is stored and in Q7 the LSbit
011010102 = 10610
Shift left =gt x2 110101002 = 21210
Shift right =gt 2 001101012 = 5310 Weight 64 32 8 2
14
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
LR CK
0 1 1 0 1 0 1 0
bull There are also arithmetic shift registers In these right shift registers instead of inserting a ldquo0rdquo in the most left FF the same logic value is always inserted
Arithmetic Shift
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
D7 D6 D5 D4 D3 D2 D1 D0
ILDCK Example
11001010ArithmeticShift Right 11100101 interpreted as 2rsquos complement
C2 C2
001101102= 5410 000110112= 2710
bull The arithmetic right shift implements a division by 2 maintaining the sign Obviously the same holds for the positive numbers
negative numbers
15
Shifting right
Rotation
In the computers it is often necessary to implement a right or left rotation of a register content This is achieved by a feedback shift register
D0kQ0k
CK DnQn
CK
D0kQ0k
CK Dn-1Qn-1
CK
D0kQ0k
CK Dn-2Qn-2
CK
D0kQ0k
CK D0Q0
CK
Very often the direction must be programmable In this case the input of D0 (through a MUX 21) can be Q1 or Qnand so on
16
Shift register counters Shift register based counter through EX-OR feedback
Q2Q0
3 bit shift rightD
Q1
110 111 011 101 010 001
Disjoint state diagram
A n FF shift register with an EX-OR feedback (with variable inputs selected) is a NON binary counter for 2n-1 (provided it is not preset with all zeros)
000
100
17
Johnson Counter
000-gt100-gt110-gt111-gt011-gt001-gt000-gt
Disjoint state loop 101-gt010-gt101gt1
A Johnson counter with N FFs counts for 2N Since successive Johnson counter configurations differ by a single bit (adjacent configurations) it can be used for generating glitches-free waveforms
FFDD Q
QR
A_RESET
FFDD Q
QR
A_RESET
FFDD Q
QR
A_RESET
OUT2OUT1OUT0
CK
18
Single laquo1raquo ring counter (directly generating a 1 over n code)
FFDD Q
QR
RESET
FFDD Q
QR
RESET
FFDD Q
QPR
RESET
OUT3OUT1OUT0
CK
FFDD Q
QR
RESET
OUT2
0001-gt1000-gt0100-gt0010-gt0010
The ring counter needs N FFs in order to count for N (while with the binary counters the number of FF necessary for a N count is m= |log2N| that is the first integer greater or equal to log2N)
19
bull Synchronous networks exercises presented in the course are based on the state diagram but only for verification Synchronous network synthesis is made WITHOUT the state diagram usinghellip the brain only by decomposing the network in well know blocks (FFs combinatorial networks and ndash see later ndash counters shift registers etcetc)hellip
20
Design a synchronous logical network (SRL) able to detect palindrome 4 bit configurations (that is configurations that are identical when read left to right or viceversa) which are sequentially inserted in a shift register The D input is significant (and therefore valid for the sequence) only when the input Enable is 1 (whichs is not necessarilly the case for four consecutive input bits) The output P is 1 for a single period when a palindrome configuration is detected after a 4 bit sequence is received Then a new 4 bit sequence must be received (by E conditioned) and detected Direct synthesis
RSS
D
VP
D
VP
Exercise 4 synchronous
21
Enable E
To store a 4 bit sequence a Shift Register with Enable (CE) and Clear (CLR) is used A palindrome configuration is detected when the 1st bit is equal to the 4th bit and the 2nd bit is equal to the 3rd bit
22
A by 4 counter is used upon the 4th clock positive edge the network controls whether the configuration is palindrome The DFF after the decoding of 3 (that is when the counter becomes 0 anew) is used because the configuration control must be delayed un period The ENABLE signal is connected to both components (when 0 both the counter and the shift are disabled)
NB The first inserted bit is sampled when the counter is increased from 0 to 1
NB in this circuit Preset and Clear signals are not connected In Xilinx unconnected control signals are inactive
23
POST-ROUTE SIMULATION
Z output is delayed 10 ns from the clock positive edge because of the switch delay
24
Not valid inputEnable=0
Barrel shifter (rotor)A barrel shifter is a shift register able to shift ldquonrdquo positions in a single period its FFs contents A-H inputs are synchronously stored in the FFs when the LDST is activated When LDST is 0 upon each clock positive edge an anticlockwise n-positions rotation takes place where n is the binary value of S0 S1 and S2 signals For instance if rdquo01110000rdquo is rotated 4 positions at the first clock the content becomes ldquo00000111rdquo If then it is rotated 3 positions it becomes ldquo00111000rdquo
It must be noticed that the component is a register with laquonraquo 81 Muxs each one connected to the D inputs of the FFs The Mux control input value n is given by S0 S1 and S2
25
The circuit in figure is one of the eight 81 MUXs which select the values to be stored in the FFs
The last six right signals are the true and inverted selection signals (S1 S1 S2 S2 S3 e S3) for the 81 MUXs
Each 81 MUX is ORed with preset input value which is used together with LOAD (if LOAD=1 the OR preset value is 0) The FF output is ANDed with LOAD this zeroes all MUX outputs allowing the preset values to be stored in the FFs
The first left 8 signals are the values of the FF D inputs in the preceding period
Xilinx schematic
26
MUX
Preset value
27
Si -gt Mux 81 control signal of each FFAH -gt segnals for Preset Load
LDST=LOADWhen LDST signal is 0 all preset ANDs are zero If LDST is 1 the preset signals are enabled and all MUX outputs are zeroed
Preset AND
28
The LOAD (LDST) signal enables the preset inputs of the FFs (see the ANDs of the previous figure) and at the same time zeroes the output of the FFs (see the FFs cascaded ANDs) so as to select the preset value of the OR input
First 4 FFs Preset values
Xilinx schematicS2 S1 S0 selection signals
A B C HInput signals
LDST load signal
Clock
QA QB QC QH Outputs signals
29
Barrel Shifter
LDST=1upont the first clock positive edge the ldquo10010111rdquo value is loaded into the Barrel Shifter
The different values of Si (1 3 5) cause different device rotation Obviously with 8 sigle shifts the value becomes the initial value ldquo10010111rdquo again
A further active LDST loads a new valute into the the Barrel Shifter
This new value can be rotated again according to S signals
30
This is a typical example of how erroneous is not to laquobusraquo signals a-g qa-g and S0-2 It would have been possible to use a compact decomposable binary notation much easier to interpret where all single signals can be however displayed by laquoopeningraquo the bus
EPROM
X0nZ0m
y0kY0k
Clock
D0kQ0k
FFD0k
CK
D0kQ0kCK
EPROM based synchronous networks
Nowadays instead of the EPROMs PLAs (Programmable Logical Arrays) are used that is devices where the combinatorial functions are optimized (combinatorial functions implementations are not necessarily canonical) The basic principle is however the same
31
Design with Xilinx a synchronous logical network using 374 ALU 74181 a counter and other necessary devices which implements in sequence (after a START) signal the sum of two four bits absolute numbers (A and B) then 2rsquos complements the result then exchanges the two MSBits with the two LSBits and eventually divides arythmetically the result by 2
Example
A=1100 B=0101 =gt Sum 0001 Exchange =gt 0100 (410)2rsquos complement =gt 1100 (-410)Arithmetical division (right shift) by two =gt 1110 (-210)
The solution can be decomposed in three subsystems the control and decoding unit the datapath the input and output registersi
This is the basic architecture of the central unit of any computer
The only difference is that for the computers instead of a fixed sequence of elementary operations a new different sequence is generated for each instruction which must be executed
32
Exercise
33
The synchronous network of figure must add modulo 256 the 8 bit data received in parallel on lines D[70] The sum must be updated each clock and presented on the output lines OUT[70] In case the input data is 68H the sum must not be updated and the input data discarded In addition whenever 6 significant data have been received (that is excluding 68H) the output signal F must be set for one clock period during the reception of the sixth data A reset input is also available which zeroes the outputs and resets the data count Direct design
RSS
D[70] OUT[70]
A_RES
F
Exercise
Clock
34
RSSD[70] OUT[70]
A_RES
F
DEC_68 signal synthesis
DEC(68h)D[70] DEC_68
D[70]
A_RES
CLK
OUT[70]
RSS
D[70] OUT[70]
A_RES
F
35
Modulo 256 adder
Full Adder 8 bit
D[70]
A_RES
374
D
A_RES
Q
Q
CLK
0
1
DEC_68
OE
1
OUT[70]
CIN
0
A[70]
B[70]
36
F signal synthesis
8 bit counter
A_RES
A_RES
EN
RES
CLKU2 U1 U0
DEC(5h)
F
DEC_68
F
Synchronous RESET
37
Exercise
A synchronous sequential network must monitor the data received on the 8 lines D[70] the data received are significant only if N=1 The networks must count modulo 256 how many data are divisible by 4 while EN=1 (excluding 0) The network has two more inputs THREE e RESET The signal THREE when asserted indicates that the value for increasing the count (if the data is divisible by 4) must be 3 (on the contrary if THREE is 0 the count must be increased by 1) The synchronous RESET signal overrides all other signals Direct design
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
38
SynchronousSequentialNetwork
EN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70] (Count)
An input data is divisible by 4 of its two Lsbits (I1 and I0) are zero
An 8 integrated bit register is used for the solution
CK
39
Signal DEC(0) is 1 if all input bits are 0
A signal DIV4 decodes whether the input data is divisible by 4 and NOT zero
DIV4 = I1I0DEC(0)
A signal STORE indicates that EN=1 and the input datum is divisible by 4
STORE = ENDIV4
I[70] DEC(0) DEC(0)
40
REG8BIT
ENSTORE + RESET
CK
FA8 bit
A[70]
B[70]
S[70]
CinCout
THREE
lsquo0rsquo
1
0
lsquo3rsquo
lsquo1rsquo
D[70] Z[70] U[70]
RESET
1
0
lsquo0rsquo
8 Mux21
The FA adds 1 or 3 according to signal THREE (provided the input datum is divisble by 4 and is not 0)
41
Exercise
Design a synchronous sequential network which according to two programming bits X1 and X0 generates the following four output sequences of two bits (signals U1 and U0) which end always with 11
10-01-01-10-11 if X1=0 e X0=010-01-10-01-10-10-11 if X1=0 e X0=100-10-00-11 if X1=1 e X0=001-10-10-10-10-11 if X1=1 e X0=1
The programming signals X1 and X0 are significant only when the output is 11 The network has an synchronous RESET Direct synthesis
RSSCK
X1
X0
U1
U0
42
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5rArr10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
The SSN uses a modulo N counter with N coded by the two input signals X1 e X0 (sampled when U1U0=11)
For the solution we can use a module 8 counter with synchronous RES and a combinatorial network with X1 and X0 as inputs Since the signals X1 and X0 are significant only when U1U0 = 1 they must be sampled (X1_C e X0_C) through two flip-flops when the SSN output is U1U0 = 11 The signals U1 and U0 are the decoding of the module 8 counter status according to X1_C and X0_C
The counter must be reset when U1U0 = 11
RSSCK
X1
X0
U1
U0
43
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X1_SX1
X1_S e X0_S synthesis
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X0_SX0
44
U1 and U0 truth table
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5 rArr (0 to 4hellip)
10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
X1_S and X0_S values
Cont | 00 01 11 10000 | 00110 00110 00100 00101001 | 01001 01001 01010 01010010 | 01101 01110 01100 01110011 | 01110 10001 00011 10010 100 | 00011 10110 ------ 10110101 | ------ 11010 ------ 00011 110 | ------ 00011 ------ ------111 | ------ ------ ------ ------
Status U1U0
Is this synthesis of the network safe
No beacuse the donrsquot cares could keep the network stable out of the main cycles
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
- Slide 59
- Slide 60
- Slide 61
- Slide 62
- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
Waveforms generation
bull It is possbile to generate periodical waveforms through synchronous circuits whose period is an integer submultiple of che clock period
Example 1 by 2 frequency divider
D0k Q0k
CK D Q
CK Clock
Q
Example 2 generation of a waveform with 5T period (T period of the clock) whose output is high for 3T and low for 2T
Q0 Q1 Q2
CKCx5
C
B
A
01234
DecoderDemux (NB if the outputs were negative true a NAND instead of the OR should be used
Clock
ZZT
3T2T
3T
NB a logical network can only implement frequency dividers and never frequency multipliers (which can be achieved only through non linear analog circuits)
7
What sort of circuit is this
Clock
Q0
Q1
Q2
This is not a synchronous binary counter (it is called also an asynchronous counter) Its FFs do not use the same clock signal and this implies that among the FFs outputs a little disalignment takes place This sort of circuit canrsquot be synthesized as a synchronous circuit and a formal synthesis can be achieved only by considering the circuit as asynchronous that is by ldquoopeningrdquo the FFs (How many states in this case )
D0k Q0k
CK D0 Q0
CK
Q0D0k Q0k
CK D1 Q1
CK
D0k Q0k
CK D2 Q2
CKClock
NB The clock signal is not the same for all FFs (7493)
8
Xilinx asynchronous counter
9
How can a DFF catch a pulse shorter than a clock period
D2 Q2
Q2CKDFF Z
Clock
D1 Q1
Q1CKDFF
D0 Q0
Q0CKDFF
ldquo1rdquo CL
Ths short pulse is laquocapturedraquo by FF 0 (provided it is sufficiently wide for the FF technology) ndash which acts as an integrator ndash whose output is fed to the A type monoimpulsor The output of FF1 resets the FF0 (if CL is ldquopositiverdquotruerdquo)
Type A monoimpulsor ldquorevisitedrdquo
10
NBThis circuits and the previous one underline the fact no network is intrinsically synchronous and that in general it is almost always necessary the use of circuits of different nature This is in any case true because there are always interacting networks which use different clocks and input signals not synchronous
Can a problem arise since the Clear is asynchronous
bull A left (right) shift register is a register made of DFFs which at each clock positive edge copies the value of its right ((left) FF In the last FF on the right (left ) a ldquo0rdquo is copied This type of shift register is called laquologic shift registerraquo
Shift registers
D0kQ0k
CK DnQn
CK
D0kQ0k
CK Dn-1Qn-1
CK
D0kQ0k
CK Dn-2Qn-2
CK
D0kQ0k
CK D0Q0
CK
ldquo0rdquo
Left shift register
bull For the shift registers too there are many versions parallel in serial output serial input parallel output with or without reset load signals etc etc
bull A shift register is also a counter If upon a reset the input of FF0 is kept to 1 the shift register is incrementally filled with laquo1raquo the number of laquo1raquo (or the position of the leftmost 1) indicates the count value
bull Very often the same register can shift either left or right according to an input control signal This is achieved inserting a 2-way Mux before each D input whose inputs are the outputs of either the left or right FF (Qigrave+1 or Qigrave-1) With this configuration the shift register becomes an Updown counter
11
3-bit shift-register
DFFD Q
QR
A_RESET
DFFD Q
QR
A_RESET
DFFD Q
QR
A_RESET
IN
OUT2OUT1OUT0
CK
12
CK
IN
A_RESET
OUT1
OUT2
OUT0
13
3-bit shift-register
Example 74164 (serial IN-parallel OUT)
bull In this shift register for each positive clock edge (CP) data are shifted one position right (Q0 -gt Q1 Q1-gtQ2 etc) The register has a Master Reset (MR ndash negative true) and the bit inserted in Q0 FF is the AND of the two inputs Dsa e Dsb
bull It must be noticed that the shift operation corresponds arithmetically (without sign) to the division and multiplication by 2 Suppose that in Q0 the MSbit is stored and in Q7 the LSbit
011010102 = 10610
Shift left =gt x2 110101002 = 21210
Shift right =gt 2 001101012 = 5310 Weight 64 32 8 2
14
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
LR CK
0 1 1 0 1 0 1 0
bull There are also arithmetic shift registers In these right shift registers instead of inserting a ldquo0rdquo in the most left FF the same logic value is always inserted
Arithmetic Shift
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
D7 D6 D5 D4 D3 D2 D1 D0
ILDCK Example
11001010ArithmeticShift Right 11100101 interpreted as 2rsquos complement
C2 C2
001101102= 5410 000110112= 2710
bull The arithmetic right shift implements a division by 2 maintaining the sign Obviously the same holds for the positive numbers
negative numbers
15
Shifting right
Rotation
In the computers it is often necessary to implement a right or left rotation of a register content This is achieved by a feedback shift register
D0kQ0k
CK DnQn
CK
D0kQ0k
CK Dn-1Qn-1
CK
D0kQ0k
CK Dn-2Qn-2
CK
D0kQ0k
CK D0Q0
CK
Very often the direction must be programmable In this case the input of D0 (through a MUX 21) can be Q1 or Qnand so on
16
Shift register counters Shift register based counter through EX-OR feedback
Q2Q0
3 bit shift rightD
Q1
110 111 011 101 010 001
Disjoint state diagram
A n FF shift register with an EX-OR feedback (with variable inputs selected) is a NON binary counter for 2n-1 (provided it is not preset with all zeros)
000
100
17
Johnson Counter
000-gt100-gt110-gt111-gt011-gt001-gt000-gt
Disjoint state loop 101-gt010-gt101gt1
A Johnson counter with N FFs counts for 2N Since successive Johnson counter configurations differ by a single bit (adjacent configurations) it can be used for generating glitches-free waveforms
FFDD Q
QR
A_RESET
FFDD Q
QR
A_RESET
FFDD Q
QR
A_RESET
OUT2OUT1OUT0
CK
18
Single laquo1raquo ring counter (directly generating a 1 over n code)
FFDD Q
QR
RESET
FFDD Q
QR
RESET
FFDD Q
QPR
RESET
OUT3OUT1OUT0
CK
FFDD Q
QR
RESET
OUT2
0001-gt1000-gt0100-gt0010-gt0010
The ring counter needs N FFs in order to count for N (while with the binary counters the number of FF necessary for a N count is m= |log2N| that is the first integer greater or equal to log2N)
19
bull Synchronous networks exercises presented in the course are based on the state diagram but only for verification Synchronous network synthesis is made WITHOUT the state diagram usinghellip the brain only by decomposing the network in well know blocks (FFs combinatorial networks and ndash see later ndash counters shift registers etcetc)hellip
20
Design a synchronous logical network (SRL) able to detect palindrome 4 bit configurations (that is configurations that are identical when read left to right or viceversa) which are sequentially inserted in a shift register The D input is significant (and therefore valid for the sequence) only when the input Enable is 1 (whichs is not necessarilly the case for four consecutive input bits) The output P is 1 for a single period when a palindrome configuration is detected after a 4 bit sequence is received Then a new 4 bit sequence must be received (by E conditioned) and detected Direct synthesis
RSS
D
VP
D
VP
Exercise 4 synchronous
21
Enable E
To store a 4 bit sequence a Shift Register with Enable (CE) and Clear (CLR) is used A palindrome configuration is detected when the 1st bit is equal to the 4th bit and the 2nd bit is equal to the 3rd bit
22
A by 4 counter is used upon the 4th clock positive edge the network controls whether the configuration is palindrome The DFF after the decoding of 3 (that is when the counter becomes 0 anew) is used because the configuration control must be delayed un period The ENABLE signal is connected to both components (when 0 both the counter and the shift are disabled)
NB The first inserted bit is sampled when the counter is increased from 0 to 1
NB in this circuit Preset and Clear signals are not connected In Xilinx unconnected control signals are inactive
23
POST-ROUTE SIMULATION
Z output is delayed 10 ns from the clock positive edge because of the switch delay
24
Not valid inputEnable=0
Barrel shifter (rotor)A barrel shifter is a shift register able to shift ldquonrdquo positions in a single period its FFs contents A-H inputs are synchronously stored in the FFs when the LDST is activated When LDST is 0 upon each clock positive edge an anticlockwise n-positions rotation takes place where n is the binary value of S0 S1 and S2 signals For instance if rdquo01110000rdquo is rotated 4 positions at the first clock the content becomes ldquo00000111rdquo If then it is rotated 3 positions it becomes ldquo00111000rdquo
It must be noticed that the component is a register with laquonraquo 81 Muxs each one connected to the D inputs of the FFs The Mux control input value n is given by S0 S1 and S2
25
The circuit in figure is one of the eight 81 MUXs which select the values to be stored in the FFs
The last six right signals are the true and inverted selection signals (S1 S1 S2 S2 S3 e S3) for the 81 MUXs
Each 81 MUX is ORed with preset input value which is used together with LOAD (if LOAD=1 the OR preset value is 0) The FF output is ANDed with LOAD this zeroes all MUX outputs allowing the preset values to be stored in the FFs
The first left 8 signals are the values of the FF D inputs in the preceding period
Xilinx schematic
26
MUX
Preset value
27
Si -gt Mux 81 control signal of each FFAH -gt segnals for Preset Load
LDST=LOADWhen LDST signal is 0 all preset ANDs are zero If LDST is 1 the preset signals are enabled and all MUX outputs are zeroed
Preset AND
28
The LOAD (LDST) signal enables the preset inputs of the FFs (see the ANDs of the previous figure) and at the same time zeroes the output of the FFs (see the FFs cascaded ANDs) so as to select the preset value of the OR input
First 4 FFs Preset values
Xilinx schematicS2 S1 S0 selection signals
A B C HInput signals
LDST load signal
Clock
QA QB QC QH Outputs signals
29
Barrel Shifter
LDST=1upont the first clock positive edge the ldquo10010111rdquo value is loaded into the Barrel Shifter
The different values of Si (1 3 5) cause different device rotation Obviously with 8 sigle shifts the value becomes the initial value ldquo10010111rdquo again
A further active LDST loads a new valute into the the Barrel Shifter
This new value can be rotated again according to S signals
30
This is a typical example of how erroneous is not to laquobusraquo signals a-g qa-g and S0-2 It would have been possible to use a compact decomposable binary notation much easier to interpret where all single signals can be however displayed by laquoopeningraquo the bus
EPROM
X0nZ0m
y0kY0k
Clock
D0kQ0k
FFD0k
CK
D0kQ0kCK
EPROM based synchronous networks
Nowadays instead of the EPROMs PLAs (Programmable Logical Arrays) are used that is devices where the combinatorial functions are optimized (combinatorial functions implementations are not necessarily canonical) The basic principle is however the same
31
Design with Xilinx a synchronous logical network using 374 ALU 74181 a counter and other necessary devices which implements in sequence (after a START) signal the sum of two four bits absolute numbers (A and B) then 2rsquos complements the result then exchanges the two MSBits with the two LSBits and eventually divides arythmetically the result by 2
Example
A=1100 B=0101 =gt Sum 0001 Exchange =gt 0100 (410)2rsquos complement =gt 1100 (-410)Arithmetical division (right shift) by two =gt 1110 (-210)
The solution can be decomposed in three subsystems the control and decoding unit the datapath the input and output registersi
This is the basic architecture of the central unit of any computer
The only difference is that for the computers instead of a fixed sequence of elementary operations a new different sequence is generated for each instruction which must be executed
32
Exercise
33
The synchronous network of figure must add modulo 256 the 8 bit data received in parallel on lines D[70] The sum must be updated each clock and presented on the output lines OUT[70] In case the input data is 68H the sum must not be updated and the input data discarded In addition whenever 6 significant data have been received (that is excluding 68H) the output signal F must be set for one clock period during the reception of the sixth data A reset input is also available which zeroes the outputs and resets the data count Direct design
RSS
D[70] OUT[70]
A_RES
F
Exercise
Clock
34
RSSD[70] OUT[70]
A_RES
F
DEC_68 signal synthesis
DEC(68h)D[70] DEC_68
D[70]
A_RES
CLK
OUT[70]
RSS
D[70] OUT[70]
A_RES
F
35
Modulo 256 adder
Full Adder 8 bit
D[70]
A_RES
374
D
A_RES
Q
Q
CLK
0
1
DEC_68
OE
1
OUT[70]
CIN
0
A[70]
B[70]
36
F signal synthesis
8 bit counter
A_RES
A_RES
EN
RES
CLKU2 U1 U0
DEC(5h)
F
DEC_68
F
Synchronous RESET
37
Exercise
A synchronous sequential network must monitor the data received on the 8 lines D[70] the data received are significant only if N=1 The networks must count modulo 256 how many data are divisible by 4 while EN=1 (excluding 0) The network has two more inputs THREE e RESET The signal THREE when asserted indicates that the value for increasing the count (if the data is divisible by 4) must be 3 (on the contrary if THREE is 0 the count must be increased by 1) The synchronous RESET signal overrides all other signals Direct design
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
38
SynchronousSequentialNetwork
EN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70] (Count)
An input data is divisible by 4 of its two Lsbits (I1 and I0) are zero
An 8 integrated bit register is used for the solution
CK
39
Signal DEC(0) is 1 if all input bits are 0
A signal DIV4 decodes whether the input data is divisible by 4 and NOT zero
DIV4 = I1I0DEC(0)
A signal STORE indicates that EN=1 and the input datum is divisible by 4
STORE = ENDIV4
I[70] DEC(0) DEC(0)
40
REG8BIT
ENSTORE + RESET
CK
FA8 bit
A[70]
B[70]
S[70]
CinCout
THREE
lsquo0rsquo
1
0
lsquo3rsquo
lsquo1rsquo
D[70] Z[70] U[70]
RESET
1
0
lsquo0rsquo
8 Mux21
The FA adds 1 or 3 according to signal THREE (provided the input datum is divisble by 4 and is not 0)
41
Exercise
Design a synchronous sequential network which according to two programming bits X1 and X0 generates the following four output sequences of two bits (signals U1 and U0) which end always with 11
10-01-01-10-11 if X1=0 e X0=010-01-10-01-10-10-11 if X1=0 e X0=100-10-00-11 if X1=1 e X0=001-10-10-10-10-11 if X1=1 e X0=1
The programming signals X1 and X0 are significant only when the output is 11 The network has an synchronous RESET Direct synthesis
RSSCK
X1
X0
U1
U0
42
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5rArr10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
The SSN uses a modulo N counter with N coded by the two input signals X1 e X0 (sampled when U1U0=11)
For the solution we can use a module 8 counter with synchronous RES and a combinatorial network with X1 and X0 as inputs Since the signals X1 and X0 are significant only when U1U0 = 1 they must be sampled (X1_C e X0_C) through two flip-flops when the SSN output is U1U0 = 11 The signals U1 and U0 are the decoding of the module 8 counter status according to X1_C and X0_C
The counter must be reset when U1U0 = 11
RSSCK
X1
X0
U1
U0
43
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X1_SX1
X1_S e X0_S synthesis
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X0_SX0
44
U1 and U0 truth table
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5 rArr (0 to 4hellip)
10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
X1_S and X0_S values
Cont | 00 01 11 10000 | 00110 00110 00100 00101001 | 01001 01001 01010 01010010 | 01101 01110 01100 01110011 | 01110 10001 00011 10010 100 | 00011 10110 ------ 10110101 | ------ 11010 ------ 00011 110 | ------ 00011 ------ ------111 | ------ ------ ------ ------
Status U1U0
Is this synthesis of the network safe
No beacuse the donrsquot cares could keep the network stable out of the main cycles
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
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- Slide 60
- Slide 61
- Slide 62
- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
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- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
What sort of circuit is this
Clock
Q0
Q1
Q2
This is not a synchronous binary counter (it is called also an asynchronous counter) Its FFs do not use the same clock signal and this implies that among the FFs outputs a little disalignment takes place This sort of circuit canrsquot be synthesized as a synchronous circuit and a formal synthesis can be achieved only by considering the circuit as asynchronous that is by ldquoopeningrdquo the FFs (How many states in this case )
D0k Q0k
CK D0 Q0
CK
Q0D0k Q0k
CK D1 Q1
CK
D0k Q0k
CK D2 Q2
CKClock
NB The clock signal is not the same for all FFs (7493)
8
Xilinx asynchronous counter
9
How can a DFF catch a pulse shorter than a clock period
D2 Q2
Q2CKDFF Z
Clock
D1 Q1
Q1CKDFF
D0 Q0
Q0CKDFF
ldquo1rdquo CL
Ths short pulse is laquocapturedraquo by FF 0 (provided it is sufficiently wide for the FF technology) ndash which acts as an integrator ndash whose output is fed to the A type monoimpulsor The output of FF1 resets the FF0 (if CL is ldquopositiverdquotruerdquo)
Type A monoimpulsor ldquorevisitedrdquo
10
NBThis circuits and the previous one underline the fact no network is intrinsically synchronous and that in general it is almost always necessary the use of circuits of different nature This is in any case true because there are always interacting networks which use different clocks and input signals not synchronous
Can a problem arise since the Clear is asynchronous
bull A left (right) shift register is a register made of DFFs which at each clock positive edge copies the value of its right ((left) FF In the last FF on the right (left ) a ldquo0rdquo is copied This type of shift register is called laquologic shift registerraquo
Shift registers
D0kQ0k
CK DnQn
CK
D0kQ0k
CK Dn-1Qn-1
CK
D0kQ0k
CK Dn-2Qn-2
CK
D0kQ0k
CK D0Q0
CK
ldquo0rdquo
Left shift register
bull For the shift registers too there are many versions parallel in serial output serial input parallel output with or without reset load signals etc etc
bull A shift register is also a counter If upon a reset the input of FF0 is kept to 1 the shift register is incrementally filled with laquo1raquo the number of laquo1raquo (or the position of the leftmost 1) indicates the count value
bull Very often the same register can shift either left or right according to an input control signal This is achieved inserting a 2-way Mux before each D input whose inputs are the outputs of either the left or right FF (Qigrave+1 or Qigrave-1) With this configuration the shift register becomes an Updown counter
11
3-bit shift-register
DFFD Q
QR
A_RESET
DFFD Q
QR
A_RESET
DFFD Q
QR
A_RESET
IN
OUT2OUT1OUT0
CK
12
CK
IN
A_RESET
OUT1
OUT2
OUT0
13
3-bit shift-register
Example 74164 (serial IN-parallel OUT)
bull In this shift register for each positive clock edge (CP) data are shifted one position right (Q0 -gt Q1 Q1-gtQ2 etc) The register has a Master Reset (MR ndash negative true) and the bit inserted in Q0 FF is the AND of the two inputs Dsa e Dsb
bull It must be noticed that the shift operation corresponds arithmetically (without sign) to the division and multiplication by 2 Suppose that in Q0 the MSbit is stored and in Q7 the LSbit
011010102 = 10610
Shift left =gt x2 110101002 = 21210
Shift right =gt 2 001101012 = 5310 Weight 64 32 8 2
14
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
LR CK
0 1 1 0 1 0 1 0
bull There are also arithmetic shift registers In these right shift registers instead of inserting a ldquo0rdquo in the most left FF the same logic value is always inserted
Arithmetic Shift
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
D7 D6 D5 D4 D3 D2 D1 D0
ILDCK Example
11001010ArithmeticShift Right 11100101 interpreted as 2rsquos complement
C2 C2
001101102= 5410 000110112= 2710
bull The arithmetic right shift implements a division by 2 maintaining the sign Obviously the same holds for the positive numbers
negative numbers
15
Shifting right
Rotation
In the computers it is often necessary to implement a right or left rotation of a register content This is achieved by a feedback shift register
D0kQ0k
CK DnQn
CK
D0kQ0k
CK Dn-1Qn-1
CK
D0kQ0k
CK Dn-2Qn-2
CK
D0kQ0k
CK D0Q0
CK
Very often the direction must be programmable In this case the input of D0 (through a MUX 21) can be Q1 or Qnand so on
16
Shift register counters Shift register based counter through EX-OR feedback
Q2Q0
3 bit shift rightD
Q1
110 111 011 101 010 001
Disjoint state diagram
A n FF shift register with an EX-OR feedback (with variable inputs selected) is a NON binary counter for 2n-1 (provided it is not preset with all zeros)
000
100
17
Johnson Counter
000-gt100-gt110-gt111-gt011-gt001-gt000-gt
Disjoint state loop 101-gt010-gt101gt1
A Johnson counter with N FFs counts for 2N Since successive Johnson counter configurations differ by a single bit (adjacent configurations) it can be used for generating glitches-free waveforms
FFDD Q
QR
A_RESET
FFDD Q
QR
A_RESET
FFDD Q
QR
A_RESET
OUT2OUT1OUT0
CK
18
Single laquo1raquo ring counter (directly generating a 1 over n code)
FFDD Q
QR
RESET
FFDD Q
QR
RESET
FFDD Q
QPR
RESET
OUT3OUT1OUT0
CK
FFDD Q
QR
RESET
OUT2
0001-gt1000-gt0100-gt0010-gt0010
The ring counter needs N FFs in order to count for N (while with the binary counters the number of FF necessary for a N count is m= |log2N| that is the first integer greater or equal to log2N)
19
bull Synchronous networks exercises presented in the course are based on the state diagram but only for verification Synchronous network synthesis is made WITHOUT the state diagram usinghellip the brain only by decomposing the network in well know blocks (FFs combinatorial networks and ndash see later ndash counters shift registers etcetc)hellip
20
Design a synchronous logical network (SRL) able to detect palindrome 4 bit configurations (that is configurations that are identical when read left to right or viceversa) which are sequentially inserted in a shift register The D input is significant (and therefore valid for the sequence) only when the input Enable is 1 (whichs is not necessarilly the case for four consecutive input bits) The output P is 1 for a single period when a palindrome configuration is detected after a 4 bit sequence is received Then a new 4 bit sequence must be received (by E conditioned) and detected Direct synthesis
RSS
D
VP
D
VP
Exercise 4 synchronous
21
Enable E
To store a 4 bit sequence a Shift Register with Enable (CE) and Clear (CLR) is used A palindrome configuration is detected when the 1st bit is equal to the 4th bit and the 2nd bit is equal to the 3rd bit
22
A by 4 counter is used upon the 4th clock positive edge the network controls whether the configuration is palindrome The DFF after the decoding of 3 (that is when the counter becomes 0 anew) is used because the configuration control must be delayed un period The ENABLE signal is connected to both components (when 0 both the counter and the shift are disabled)
NB The first inserted bit is sampled when the counter is increased from 0 to 1
NB in this circuit Preset and Clear signals are not connected In Xilinx unconnected control signals are inactive
23
POST-ROUTE SIMULATION
Z output is delayed 10 ns from the clock positive edge because of the switch delay
24
Not valid inputEnable=0
Barrel shifter (rotor)A barrel shifter is a shift register able to shift ldquonrdquo positions in a single period its FFs contents A-H inputs are synchronously stored in the FFs when the LDST is activated When LDST is 0 upon each clock positive edge an anticlockwise n-positions rotation takes place where n is the binary value of S0 S1 and S2 signals For instance if rdquo01110000rdquo is rotated 4 positions at the first clock the content becomes ldquo00000111rdquo If then it is rotated 3 positions it becomes ldquo00111000rdquo
It must be noticed that the component is a register with laquonraquo 81 Muxs each one connected to the D inputs of the FFs The Mux control input value n is given by S0 S1 and S2
25
The circuit in figure is one of the eight 81 MUXs which select the values to be stored in the FFs
The last six right signals are the true and inverted selection signals (S1 S1 S2 S2 S3 e S3) for the 81 MUXs
Each 81 MUX is ORed with preset input value which is used together with LOAD (if LOAD=1 the OR preset value is 0) The FF output is ANDed with LOAD this zeroes all MUX outputs allowing the preset values to be stored in the FFs
The first left 8 signals are the values of the FF D inputs in the preceding period
Xilinx schematic
26
MUX
Preset value
27
Si -gt Mux 81 control signal of each FFAH -gt segnals for Preset Load
LDST=LOADWhen LDST signal is 0 all preset ANDs are zero If LDST is 1 the preset signals are enabled and all MUX outputs are zeroed
Preset AND
28
The LOAD (LDST) signal enables the preset inputs of the FFs (see the ANDs of the previous figure) and at the same time zeroes the output of the FFs (see the FFs cascaded ANDs) so as to select the preset value of the OR input
First 4 FFs Preset values
Xilinx schematicS2 S1 S0 selection signals
A B C HInput signals
LDST load signal
Clock
QA QB QC QH Outputs signals
29
Barrel Shifter
LDST=1upont the first clock positive edge the ldquo10010111rdquo value is loaded into the Barrel Shifter
The different values of Si (1 3 5) cause different device rotation Obviously with 8 sigle shifts the value becomes the initial value ldquo10010111rdquo again
A further active LDST loads a new valute into the the Barrel Shifter
This new value can be rotated again according to S signals
30
This is a typical example of how erroneous is not to laquobusraquo signals a-g qa-g and S0-2 It would have been possible to use a compact decomposable binary notation much easier to interpret where all single signals can be however displayed by laquoopeningraquo the bus
EPROM
X0nZ0m
y0kY0k
Clock
D0kQ0k
FFD0k
CK
D0kQ0kCK
EPROM based synchronous networks
Nowadays instead of the EPROMs PLAs (Programmable Logical Arrays) are used that is devices where the combinatorial functions are optimized (combinatorial functions implementations are not necessarily canonical) The basic principle is however the same
31
Design with Xilinx a synchronous logical network using 374 ALU 74181 a counter and other necessary devices which implements in sequence (after a START) signal the sum of two four bits absolute numbers (A and B) then 2rsquos complements the result then exchanges the two MSBits with the two LSBits and eventually divides arythmetically the result by 2
Example
A=1100 B=0101 =gt Sum 0001 Exchange =gt 0100 (410)2rsquos complement =gt 1100 (-410)Arithmetical division (right shift) by two =gt 1110 (-210)
The solution can be decomposed in three subsystems the control and decoding unit the datapath the input and output registersi
This is the basic architecture of the central unit of any computer
The only difference is that for the computers instead of a fixed sequence of elementary operations a new different sequence is generated for each instruction which must be executed
32
Exercise
33
The synchronous network of figure must add modulo 256 the 8 bit data received in parallel on lines D[70] The sum must be updated each clock and presented on the output lines OUT[70] In case the input data is 68H the sum must not be updated and the input data discarded In addition whenever 6 significant data have been received (that is excluding 68H) the output signal F must be set for one clock period during the reception of the sixth data A reset input is also available which zeroes the outputs and resets the data count Direct design
RSS
D[70] OUT[70]
A_RES
F
Exercise
Clock
34
RSSD[70] OUT[70]
A_RES
F
DEC_68 signal synthesis
DEC(68h)D[70] DEC_68
D[70]
A_RES
CLK
OUT[70]
RSS
D[70] OUT[70]
A_RES
F
35
Modulo 256 adder
Full Adder 8 bit
D[70]
A_RES
374
D
A_RES
Q
Q
CLK
0
1
DEC_68
OE
1
OUT[70]
CIN
0
A[70]
B[70]
36
F signal synthesis
8 bit counter
A_RES
A_RES
EN
RES
CLKU2 U1 U0
DEC(5h)
F
DEC_68
F
Synchronous RESET
37
Exercise
A synchronous sequential network must monitor the data received on the 8 lines D[70] the data received are significant only if N=1 The networks must count modulo 256 how many data are divisible by 4 while EN=1 (excluding 0) The network has two more inputs THREE e RESET The signal THREE when asserted indicates that the value for increasing the count (if the data is divisible by 4) must be 3 (on the contrary if THREE is 0 the count must be increased by 1) The synchronous RESET signal overrides all other signals Direct design
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
38
SynchronousSequentialNetwork
EN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70] (Count)
An input data is divisible by 4 of its two Lsbits (I1 and I0) are zero
An 8 integrated bit register is used for the solution
CK
39
Signal DEC(0) is 1 if all input bits are 0
A signal DIV4 decodes whether the input data is divisible by 4 and NOT zero
DIV4 = I1I0DEC(0)
A signal STORE indicates that EN=1 and the input datum is divisible by 4
STORE = ENDIV4
I[70] DEC(0) DEC(0)
40
REG8BIT
ENSTORE + RESET
CK
FA8 bit
A[70]
B[70]
S[70]
CinCout
THREE
lsquo0rsquo
1
0
lsquo3rsquo
lsquo1rsquo
D[70] Z[70] U[70]
RESET
1
0
lsquo0rsquo
8 Mux21
The FA adds 1 or 3 according to signal THREE (provided the input datum is divisble by 4 and is not 0)
41
Exercise
Design a synchronous sequential network which according to two programming bits X1 and X0 generates the following four output sequences of two bits (signals U1 and U0) which end always with 11
10-01-01-10-11 if X1=0 e X0=010-01-10-01-10-10-11 if X1=0 e X0=100-10-00-11 if X1=1 e X0=001-10-10-10-10-11 if X1=1 e X0=1
The programming signals X1 and X0 are significant only when the output is 11 The network has an synchronous RESET Direct synthesis
RSSCK
X1
X0
U1
U0
42
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5rArr10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
The SSN uses a modulo N counter with N coded by the two input signals X1 e X0 (sampled when U1U0=11)
For the solution we can use a module 8 counter with synchronous RES and a combinatorial network with X1 and X0 as inputs Since the signals X1 and X0 are significant only when U1U0 = 1 they must be sampled (X1_C e X0_C) through two flip-flops when the SSN output is U1U0 = 11 The signals U1 and U0 are the decoding of the module 8 counter status according to X1_C and X0_C
The counter must be reset when U1U0 = 11
RSSCK
X1
X0
U1
U0
43
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X1_SX1
X1_S e X0_S synthesis
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X0_SX0
44
U1 and U0 truth table
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5 rArr (0 to 4hellip)
10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
X1_S and X0_S values
Cont | 00 01 11 10000 | 00110 00110 00100 00101001 | 01001 01001 01010 01010010 | 01101 01110 01100 01110011 | 01110 10001 00011 10010 100 | 00011 10110 ------ 10110101 | ------ 11010 ------ 00011 110 | ------ 00011 ------ ------111 | ------ ------ ------ ------
Status U1U0
Is this synthesis of the network safe
No beacuse the donrsquot cares could keep the network stable out of the main cycles
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
- Slide 59
- Slide 60
- Slide 61
- Slide 62
- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
Xilinx asynchronous counter
9
How can a DFF catch a pulse shorter than a clock period
D2 Q2
Q2CKDFF Z
Clock
D1 Q1
Q1CKDFF
D0 Q0
Q0CKDFF
ldquo1rdquo CL
Ths short pulse is laquocapturedraquo by FF 0 (provided it is sufficiently wide for the FF technology) ndash which acts as an integrator ndash whose output is fed to the A type monoimpulsor The output of FF1 resets the FF0 (if CL is ldquopositiverdquotruerdquo)
Type A monoimpulsor ldquorevisitedrdquo
10
NBThis circuits and the previous one underline the fact no network is intrinsically synchronous and that in general it is almost always necessary the use of circuits of different nature This is in any case true because there are always interacting networks which use different clocks and input signals not synchronous
Can a problem arise since the Clear is asynchronous
bull A left (right) shift register is a register made of DFFs which at each clock positive edge copies the value of its right ((left) FF In the last FF on the right (left ) a ldquo0rdquo is copied This type of shift register is called laquologic shift registerraquo
Shift registers
D0kQ0k
CK DnQn
CK
D0kQ0k
CK Dn-1Qn-1
CK
D0kQ0k
CK Dn-2Qn-2
CK
D0kQ0k
CK D0Q0
CK
ldquo0rdquo
Left shift register
bull For the shift registers too there are many versions parallel in serial output serial input parallel output with or without reset load signals etc etc
bull A shift register is also a counter If upon a reset the input of FF0 is kept to 1 the shift register is incrementally filled with laquo1raquo the number of laquo1raquo (or the position of the leftmost 1) indicates the count value
bull Very often the same register can shift either left or right according to an input control signal This is achieved inserting a 2-way Mux before each D input whose inputs are the outputs of either the left or right FF (Qigrave+1 or Qigrave-1) With this configuration the shift register becomes an Updown counter
11
3-bit shift-register
DFFD Q
QR
A_RESET
DFFD Q
QR
A_RESET
DFFD Q
QR
A_RESET
IN
OUT2OUT1OUT0
CK
12
CK
IN
A_RESET
OUT1
OUT2
OUT0
13
3-bit shift-register
Example 74164 (serial IN-parallel OUT)
bull In this shift register for each positive clock edge (CP) data are shifted one position right (Q0 -gt Q1 Q1-gtQ2 etc) The register has a Master Reset (MR ndash negative true) and the bit inserted in Q0 FF is the AND of the two inputs Dsa e Dsb
bull It must be noticed that the shift operation corresponds arithmetically (without sign) to the division and multiplication by 2 Suppose that in Q0 the MSbit is stored and in Q7 the LSbit
011010102 = 10610
Shift left =gt x2 110101002 = 21210
Shift right =gt 2 001101012 = 5310 Weight 64 32 8 2
14
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
LR CK
0 1 1 0 1 0 1 0
bull There are also arithmetic shift registers In these right shift registers instead of inserting a ldquo0rdquo in the most left FF the same logic value is always inserted
Arithmetic Shift
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
D7 D6 D5 D4 D3 D2 D1 D0
ILDCK Example
11001010ArithmeticShift Right 11100101 interpreted as 2rsquos complement
C2 C2
001101102= 5410 000110112= 2710
bull The arithmetic right shift implements a division by 2 maintaining the sign Obviously the same holds for the positive numbers
negative numbers
15
Shifting right
Rotation
In the computers it is often necessary to implement a right or left rotation of a register content This is achieved by a feedback shift register
D0kQ0k
CK DnQn
CK
D0kQ0k
CK Dn-1Qn-1
CK
D0kQ0k
CK Dn-2Qn-2
CK
D0kQ0k
CK D0Q0
CK
Very often the direction must be programmable In this case the input of D0 (through a MUX 21) can be Q1 or Qnand so on
16
Shift register counters Shift register based counter through EX-OR feedback
Q2Q0
3 bit shift rightD
Q1
110 111 011 101 010 001
Disjoint state diagram
A n FF shift register with an EX-OR feedback (with variable inputs selected) is a NON binary counter for 2n-1 (provided it is not preset with all zeros)
000
100
17
Johnson Counter
000-gt100-gt110-gt111-gt011-gt001-gt000-gt
Disjoint state loop 101-gt010-gt101gt1
A Johnson counter with N FFs counts for 2N Since successive Johnson counter configurations differ by a single bit (adjacent configurations) it can be used for generating glitches-free waveforms
FFDD Q
QR
A_RESET
FFDD Q
QR
A_RESET
FFDD Q
QR
A_RESET
OUT2OUT1OUT0
CK
18
Single laquo1raquo ring counter (directly generating a 1 over n code)
FFDD Q
QR
RESET
FFDD Q
QR
RESET
FFDD Q
QPR
RESET
OUT3OUT1OUT0
CK
FFDD Q
QR
RESET
OUT2
0001-gt1000-gt0100-gt0010-gt0010
The ring counter needs N FFs in order to count for N (while with the binary counters the number of FF necessary for a N count is m= |log2N| that is the first integer greater or equal to log2N)
19
bull Synchronous networks exercises presented in the course are based on the state diagram but only for verification Synchronous network synthesis is made WITHOUT the state diagram usinghellip the brain only by decomposing the network in well know blocks (FFs combinatorial networks and ndash see later ndash counters shift registers etcetc)hellip
20
Design a synchronous logical network (SRL) able to detect palindrome 4 bit configurations (that is configurations that are identical when read left to right or viceversa) which are sequentially inserted in a shift register The D input is significant (and therefore valid for the sequence) only when the input Enable is 1 (whichs is not necessarilly the case for four consecutive input bits) The output P is 1 for a single period when a palindrome configuration is detected after a 4 bit sequence is received Then a new 4 bit sequence must be received (by E conditioned) and detected Direct synthesis
RSS
D
VP
D
VP
Exercise 4 synchronous
21
Enable E
To store a 4 bit sequence a Shift Register with Enable (CE) and Clear (CLR) is used A palindrome configuration is detected when the 1st bit is equal to the 4th bit and the 2nd bit is equal to the 3rd bit
22
A by 4 counter is used upon the 4th clock positive edge the network controls whether the configuration is palindrome The DFF after the decoding of 3 (that is when the counter becomes 0 anew) is used because the configuration control must be delayed un period The ENABLE signal is connected to both components (when 0 both the counter and the shift are disabled)
NB The first inserted bit is sampled when the counter is increased from 0 to 1
NB in this circuit Preset and Clear signals are not connected In Xilinx unconnected control signals are inactive
23
POST-ROUTE SIMULATION
Z output is delayed 10 ns from the clock positive edge because of the switch delay
24
Not valid inputEnable=0
Barrel shifter (rotor)A barrel shifter is a shift register able to shift ldquonrdquo positions in a single period its FFs contents A-H inputs are synchronously stored in the FFs when the LDST is activated When LDST is 0 upon each clock positive edge an anticlockwise n-positions rotation takes place where n is the binary value of S0 S1 and S2 signals For instance if rdquo01110000rdquo is rotated 4 positions at the first clock the content becomes ldquo00000111rdquo If then it is rotated 3 positions it becomes ldquo00111000rdquo
It must be noticed that the component is a register with laquonraquo 81 Muxs each one connected to the D inputs of the FFs The Mux control input value n is given by S0 S1 and S2
25
The circuit in figure is one of the eight 81 MUXs which select the values to be stored in the FFs
The last six right signals are the true and inverted selection signals (S1 S1 S2 S2 S3 e S3) for the 81 MUXs
Each 81 MUX is ORed with preset input value which is used together with LOAD (if LOAD=1 the OR preset value is 0) The FF output is ANDed with LOAD this zeroes all MUX outputs allowing the preset values to be stored in the FFs
The first left 8 signals are the values of the FF D inputs in the preceding period
Xilinx schematic
26
MUX
Preset value
27
Si -gt Mux 81 control signal of each FFAH -gt segnals for Preset Load
LDST=LOADWhen LDST signal is 0 all preset ANDs are zero If LDST is 1 the preset signals are enabled and all MUX outputs are zeroed
Preset AND
28
The LOAD (LDST) signal enables the preset inputs of the FFs (see the ANDs of the previous figure) and at the same time zeroes the output of the FFs (see the FFs cascaded ANDs) so as to select the preset value of the OR input
First 4 FFs Preset values
Xilinx schematicS2 S1 S0 selection signals
A B C HInput signals
LDST load signal
Clock
QA QB QC QH Outputs signals
29
Barrel Shifter
LDST=1upont the first clock positive edge the ldquo10010111rdquo value is loaded into the Barrel Shifter
The different values of Si (1 3 5) cause different device rotation Obviously with 8 sigle shifts the value becomes the initial value ldquo10010111rdquo again
A further active LDST loads a new valute into the the Barrel Shifter
This new value can be rotated again according to S signals
30
This is a typical example of how erroneous is not to laquobusraquo signals a-g qa-g and S0-2 It would have been possible to use a compact decomposable binary notation much easier to interpret where all single signals can be however displayed by laquoopeningraquo the bus
EPROM
X0nZ0m
y0kY0k
Clock
D0kQ0k
FFD0k
CK
D0kQ0kCK
EPROM based synchronous networks
Nowadays instead of the EPROMs PLAs (Programmable Logical Arrays) are used that is devices where the combinatorial functions are optimized (combinatorial functions implementations are not necessarily canonical) The basic principle is however the same
31
Design with Xilinx a synchronous logical network using 374 ALU 74181 a counter and other necessary devices which implements in sequence (after a START) signal the sum of two four bits absolute numbers (A and B) then 2rsquos complements the result then exchanges the two MSBits with the two LSBits and eventually divides arythmetically the result by 2
Example
A=1100 B=0101 =gt Sum 0001 Exchange =gt 0100 (410)2rsquos complement =gt 1100 (-410)Arithmetical division (right shift) by two =gt 1110 (-210)
The solution can be decomposed in three subsystems the control and decoding unit the datapath the input and output registersi
This is the basic architecture of the central unit of any computer
The only difference is that for the computers instead of a fixed sequence of elementary operations a new different sequence is generated for each instruction which must be executed
32
Exercise
33
The synchronous network of figure must add modulo 256 the 8 bit data received in parallel on lines D[70] The sum must be updated each clock and presented on the output lines OUT[70] In case the input data is 68H the sum must not be updated and the input data discarded In addition whenever 6 significant data have been received (that is excluding 68H) the output signal F must be set for one clock period during the reception of the sixth data A reset input is also available which zeroes the outputs and resets the data count Direct design
RSS
D[70] OUT[70]
A_RES
F
Exercise
Clock
34
RSSD[70] OUT[70]
A_RES
F
DEC_68 signal synthesis
DEC(68h)D[70] DEC_68
D[70]
A_RES
CLK
OUT[70]
RSS
D[70] OUT[70]
A_RES
F
35
Modulo 256 adder
Full Adder 8 bit
D[70]
A_RES
374
D
A_RES
Q
Q
CLK
0
1
DEC_68
OE
1
OUT[70]
CIN
0
A[70]
B[70]
36
F signal synthesis
8 bit counter
A_RES
A_RES
EN
RES
CLKU2 U1 U0
DEC(5h)
F
DEC_68
F
Synchronous RESET
37
Exercise
A synchronous sequential network must monitor the data received on the 8 lines D[70] the data received are significant only if N=1 The networks must count modulo 256 how many data are divisible by 4 while EN=1 (excluding 0) The network has two more inputs THREE e RESET The signal THREE when asserted indicates that the value for increasing the count (if the data is divisible by 4) must be 3 (on the contrary if THREE is 0 the count must be increased by 1) The synchronous RESET signal overrides all other signals Direct design
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
38
SynchronousSequentialNetwork
EN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70] (Count)
An input data is divisible by 4 of its two Lsbits (I1 and I0) are zero
An 8 integrated bit register is used for the solution
CK
39
Signal DEC(0) is 1 if all input bits are 0
A signal DIV4 decodes whether the input data is divisible by 4 and NOT zero
DIV4 = I1I0DEC(0)
A signal STORE indicates that EN=1 and the input datum is divisible by 4
STORE = ENDIV4
I[70] DEC(0) DEC(0)
40
REG8BIT
ENSTORE + RESET
CK
FA8 bit
A[70]
B[70]
S[70]
CinCout
THREE
lsquo0rsquo
1
0
lsquo3rsquo
lsquo1rsquo
D[70] Z[70] U[70]
RESET
1
0
lsquo0rsquo
8 Mux21
The FA adds 1 or 3 according to signal THREE (provided the input datum is divisble by 4 and is not 0)
41
Exercise
Design a synchronous sequential network which according to two programming bits X1 and X0 generates the following four output sequences of two bits (signals U1 and U0) which end always with 11
10-01-01-10-11 if X1=0 e X0=010-01-10-01-10-10-11 if X1=0 e X0=100-10-00-11 if X1=1 e X0=001-10-10-10-10-11 if X1=1 e X0=1
The programming signals X1 and X0 are significant only when the output is 11 The network has an synchronous RESET Direct synthesis
RSSCK
X1
X0
U1
U0
42
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5rArr10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
The SSN uses a modulo N counter with N coded by the two input signals X1 e X0 (sampled when U1U0=11)
For the solution we can use a module 8 counter with synchronous RES and a combinatorial network with X1 and X0 as inputs Since the signals X1 and X0 are significant only when U1U0 = 1 they must be sampled (X1_C e X0_C) through two flip-flops when the SSN output is U1U0 = 11 The signals U1 and U0 are the decoding of the module 8 counter status according to X1_C and X0_C
The counter must be reset when U1U0 = 11
RSSCK
X1
X0
U1
U0
43
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X1_SX1
X1_S e X0_S synthesis
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X0_SX0
44
U1 and U0 truth table
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5 rArr (0 to 4hellip)
10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
X1_S and X0_S values
Cont | 00 01 11 10000 | 00110 00110 00100 00101001 | 01001 01001 01010 01010010 | 01101 01110 01100 01110011 | 01110 10001 00011 10010 100 | 00011 10110 ------ 10110101 | ------ 11010 ------ 00011 110 | ------ 00011 ------ ------111 | ------ ------ ------ ------
Status U1U0
Is this synthesis of the network safe
No beacuse the donrsquot cares could keep the network stable out of the main cycles
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
- Slide 59
- Slide 60
- Slide 61
- Slide 62
- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
How can a DFF catch a pulse shorter than a clock period
D2 Q2
Q2CKDFF Z
Clock
D1 Q1
Q1CKDFF
D0 Q0
Q0CKDFF
ldquo1rdquo CL
Ths short pulse is laquocapturedraquo by FF 0 (provided it is sufficiently wide for the FF technology) ndash which acts as an integrator ndash whose output is fed to the A type monoimpulsor The output of FF1 resets the FF0 (if CL is ldquopositiverdquotruerdquo)
Type A monoimpulsor ldquorevisitedrdquo
10
NBThis circuits and the previous one underline the fact no network is intrinsically synchronous and that in general it is almost always necessary the use of circuits of different nature This is in any case true because there are always interacting networks which use different clocks and input signals not synchronous
Can a problem arise since the Clear is asynchronous
bull A left (right) shift register is a register made of DFFs which at each clock positive edge copies the value of its right ((left) FF In the last FF on the right (left ) a ldquo0rdquo is copied This type of shift register is called laquologic shift registerraquo
Shift registers
D0kQ0k
CK DnQn
CK
D0kQ0k
CK Dn-1Qn-1
CK
D0kQ0k
CK Dn-2Qn-2
CK
D0kQ0k
CK D0Q0
CK
ldquo0rdquo
Left shift register
bull For the shift registers too there are many versions parallel in serial output serial input parallel output with or without reset load signals etc etc
bull A shift register is also a counter If upon a reset the input of FF0 is kept to 1 the shift register is incrementally filled with laquo1raquo the number of laquo1raquo (or the position of the leftmost 1) indicates the count value
bull Very often the same register can shift either left or right according to an input control signal This is achieved inserting a 2-way Mux before each D input whose inputs are the outputs of either the left or right FF (Qigrave+1 or Qigrave-1) With this configuration the shift register becomes an Updown counter
11
3-bit shift-register
DFFD Q
QR
A_RESET
DFFD Q
QR
A_RESET
DFFD Q
QR
A_RESET
IN
OUT2OUT1OUT0
CK
12
CK
IN
A_RESET
OUT1
OUT2
OUT0
13
3-bit shift-register
Example 74164 (serial IN-parallel OUT)
bull In this shift register for each positive clock edge (CP) data are shifted one position right (Q0 -gt Q1 Q1-gtQ2 etc) The register has a Master Reset (MR ndash negative true) and the bit inserted in Q0 FF is the AND of the two inputs Dsa e Dsb
bull It must be noticed that the shift operation corresponds arithmetically (without sign) to the division and multiplication by 2 Suppose that in Q0 the MSbit is stored and in Q7 the LSbit
011010102 = 10610
Shift left =gt x2 110101002 = 21210
Shift right =gt 2 001101012 = 5310 Weight 64 32 8 2
14
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
LR CK
0 1 1 0 1 0 1 0
bull There are also arithmetic shift registers In these right shift registers instead of inserting a ldquo0rdquo in the most left FF the same logic value is always inserted
Arithmetic Shift
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
D7 D6 D5 D4 D3 D2 D1 D0
ILDCK Example
11001010ArithmeticShift Right 11100101 interpreted as 2rsquos complement
C2 C2
001101102= 5410 000110112= 2710
bull The arithmetic right shift implements a division by 2 maintaining the sign Obviously the same holds for the positive numbers
negative numbers
15
Shifting right
Rotation
In the computers it is often necessary to implement a right or left rotation of a register content This is achieved by a feedback shift register
D0kQ0k
CK DnQn
CK
D0kQ0k
CK Dn-1Qn-1
CK
D0kQ0k
CK Dn-2Qn-2
CK
D0kQ0k
CK D0Q0
CK
Very often the direction must be programmable In this case the input of D0 (through a MUX 21) can be Q1 or Qnand so on
16
Shift register counters Shift register based counter through EX-OR feedback
Q2Q0
3 bit shift rightD
Q1
110 111 011 101 010 001
Disjoint state diagram
A n FF shift register with an EX-OR feedback (with variable inputs selected) is a NON binary counter for 2n-1 (provided it is not preset with all zeros)
000
100
17
Johnson Counter
000-gt100-gt110-gt111-gt011-gt001-gt000-gt
Disjoint state loop 101-gt010-gt101gt1
A Johnson counter with N FFs counts for 2N Since successive Johnson counter configurations differ by a single bit (adjacent configurations) it can be used for generating glitches-free waveforms
FFDD Q
QR
A_RESET
FFDD Q
QR
A_RESET
FFDD Q
QR
A_RESET
OUT2OUT1OUT0
CK
18
Single laquo1raquo ring counter (directly generating a 1 over n code)
FFDD Q
QR
RESET
FFDD Q
QR
RESET
FFDD Q
QPR
RESET
OUT3OUT1OUT0
CK
FFDD Q
QR
RESET
OUT2
0001-gt1000-gt0100-gt0010-gt0010
The ring counter needs N FFs in order to count for N (while with the binary counters the number of FF necessary for a N count is m= |log2N| that is the first integer greater or equal to log2N)
19
bull Synchronous networks exercises presented in the course are based on the state diagram but only for verification Synchronous network synthesis is made WITHOUT the state diagram usinghellip the brain only by decomposing the network in well know blocks (FFs combinatorial networks and ndash see later ndash counters shift registers etcetc)hellip
20
Design a synchronous logical network (SRL) able to detect palindrome 4 bit configurations (that is configurations that are identical when read left to right or viceversa) which are sequentially inserted in a shift register The D input is significant (and therefore valid for the sequence) only when the input Enable is 1 (whichs is not necessarilly the case for four consecutive input bits) The output P is 1 for a single period when a palindrome configuration is detected after a 4 bit sequence is received Then a new 4 bit sequence must be received (by E conditioned) and detected Direct synthesis
RSS
D
VP
D
VP
Exercise 4 synchronous
21
Enable E
To store a 4 bit sequence a Shift Register with Enable (CE) and Clear (CLR) is used A palindrome configuration is detected when the 1st bit is equal to the 4th bit and the 2nd bit is equal to the 3rd bit
22
A by 4 counter is used upon the 4th clock positive edge the network controls whether the configuration is palindrome The DFF after the decoding of 3 (that is when the counter becomes 0 anew) is used because the configuration control must be delayed un period The ENABLE signal is connected to both components (when 0 both the counter and the shift are disabled)
NB The first inserted bit is sampled when the counter is increased from 0 to 1
NB in this circuit Preset and Clear signals are not connected In Xilinx unconnected control signals are inactive
23
POST-ROUTE SIMULATION
Z output is delayed 10 ns from the clock positive edge because of the switch delay
24
Not valid inputEnable=0
Barrel shifter (rotor)A barrel shifter is a shift register able to shift ldquonrdquo positions in a single period its FFs contents A-H inputs are synchronously stored in the FFs when the LDST is activated When LDST is 0 upon each clock positive edge an anticlockwise n-positions rotation takes place where n is the binary value of S0 S1 and S2 signals For instance if rdquo01110000rdquo is rotated 4 positions at the first clock the content becomes ldquo00000111rdquo If then it is rotated 3 positions it becomes ldquo00111000rdquo
It must be noticed that the component is a register with laquonraquo 81 Muxs each one connected to the D inputs of the FFs The Mux control input value n is given by S0 S1 and S2
25
The circuit in figure is one of the eight 81 MUXs which select the values to be stored in the FFs
The last six right signals are the true and inverted selection signals (S1 S1 S2 S2 S3 e S3) for the 81 MUXs
Each 81 MUX is ORed with preset input value which is used together with LOAD (if LOAD=1 the OR preset value is 0) The FF output is ANDed with LOAD this zeroes all MUX outputs allowing the preset values to be stored in the FFs
The first left 8 signals are the values of the FF D inputs in the preceding period
Xilinx schematic
26
MUX
Preset value
27
Si -gt Mux 81 control signal of each FFAH -gt segnals for Preset Load
LDST=LOADWhen LDST signal is 0 all preset ANDs are zero If LDST is 1 the preset signals are enabled and all MUX outputs are zeroed
Preset AND
28
The LOAD (LDST) signal enables the preset inputs of the FFs (see the ANDs of the previous figure) and at the same time zeroes the output of the FFs (see the FFs cascaded ANDs) so as to select the preset value of the OR input
First 4 FFs Preset values
Xilinx schematicS2 S1 S0 selection signals
A B C HInput signals
LDST load signal
Clock
QA QB QC QH Outputs signals
29
Barrel Shifter
LDST=1upont the first clock positive edge the ldquo10010111rdquo value is loaded into the Barrel Shifter
The different values of Si (1 3 5) cause different device rotation Obviously with 8 sigle shifts the value becomes the initial value ldquo10010111rdquo again
A further active LDST loads a new valute into the the Barrel Shifter
This new value can be rotated again according to S signals
30
This is a typical example of how erroneous is not to laquobusraquo signals a-g qa-g and S0-2 It would have been possible to use a compact decomposable binary notation much easier to interpret where all single signals can be however displayed by laquoopeningraquo the bus
EPROM
X0nZ0m
y0kY0k
Clock
D0kQ0k
FFD0k
CK
D0kQ0kCK
EPROM based synchronous networks
Nowadays instead of the EPROMs PLAs (Programmable Logical Arrays) are used that is devices where the combinatorial functions are optimized (combinatorial functions implementations are not necessarily canonical) The basic principle is however the same
31
Design with Xilinx a synchronous logical network using 374 ALU 74181 a counter and other necessary devices which implements in sequence (after a START) signal the sum of two four bits absolute numbers (A and B) then 2rsquos complements the result then exchanges the two MSBits with the two LSBits and eventually divides arythmetically the result by 2
Example
A=1100 B=0101 =gt Sum 0001 Exchange =gt 0100 (410)2rsquos complement =gt 1100 (-410)Arithmetical division (right shift) by two =gt 1110 (-210)
The solution can be decomposed in three subsystems the control and decoding unit the datapath the input and output registersi
This is the basic architecture of the central unit of any computer
The only difference is that for the computers instead of a fixed sequence of elementary operations a new different sequence is generated for each instruction which must be executed
32
Exercise
33
The synchronous network of figure must add modulo 256 the 8 bit data received in parallel on lines D[70] The sum must be updated each clock and presented on the output lines OUT[70] In case the input data is 68H the sum must not be updated and the input data discarded In addition whenever 6 significant data have been received (that is excluding 68H) the output signal F must be set for one clock period during the reception of the sixth data A reset input is also available which zeroes the outputs and resets the data count Direct design
RSS
D[70] OUT[70]
A_RES
F
Exercise
Clock
34
RSSD[70] OUT[70]
A_RES
F
DEC_68 signal synthesis
DEC(68h)D[70] DEC_68
D[70]
A_RES
CLK
OUT[70]
RSS
D[70] OUT[70]
A_RES
F
35
Modulo 256 adder
Full Adder 8 bit
D[70]
A_RES
374
D
A_RES
Q
Q
CLK
0
1
DEC_68
OE
1
OUT[70]
CIN
0
A[70]
B[70]
36
F signal synthesis
8 bit counter
A_RES
A_RES
EN
RES
CLKU2 U1 U0
DEC(5h)
F
DEC_68
F
Synchronous RESET
37
Exercise
A synchronous sequential network must monitor the data received on the 8 lines D[70] the data received are significant only if N=1 The networks must count modulo 256 how many data are divisible by 4 while EN=1 (excluding 0) The network has two more inputs THREE e RESET The signal THREE when asserted indicates that the value for increasing the count (if the data is divisible by 4) must be 3 (on the contrary if THREE is 0 the count must be increased by 1) The synchronous RESET signal overrides all other signals Direct design
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
38
SynchronousSequentialNetwork
EN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70] (Count)
An input data is divisible by 4 of its two Lsbits (I1 and I0) are zero
An 8 integrated bit register is used for the solution
CK
39
Signal DEC(0) is 1 if all input bits are 0
A signal DIV4 decodes whether the input data is divisible by 4 and NOT zero
DIV4 = I1I0DEC(0)
A signal STORE indicates that EN=1 and the input datum is divisible by 4
STORE = ENDIV4
I[70] DEC(0) DEC(0)
40
REG8BIT
ENSTORE + RESET
CK
FA8 bit
A[70]
B[70]
S[70]
CinCout
THREE
lsquo0rsquo
1
0
lsquo3rsquo
lsquo1rsquo
D[70] Z[70] U[70]
RESET
1
0
lsquo0rsquo
8 Mux21
The FA adds 1 or 3 according to signal THREE (provided the input datum is divisble by 4 and is not 0)
41
Exercise
Design a synchronous sequential network which according to two programming bits X1 and X0 generates the following four output sequences of two bits (signals U1 and U0) which end always with 11
10-01-01-10-11 if X1=0 e X0=010-01-10-01-10-10-11 if X1=0 e X0=100-10-00-11 if X1=1 e X0=001-10-10-10-10-11 if X1=1 e X0=1
The programming signals X1 and X0 are significant only when the output is 11 The network has an synchronous RESET Direct synthesis
RSSCK
X1
X0
U1
U0
42
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5rArr10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
The SSN uses a modulo N counter with N coded by the two input signals X1 e X0 (sampled when U1U0=11)
For the solution we can use a module 8 counter with synchronous RES and a combinatorial network with X1 and X0 as inputs Since the signals X1 and X0 are significant only when U1U0 = 1 they must be sampled (X1_C e X0_C) through two flip-flops when the SSN output is U1U0 = 11 The signals U1 and U0 are the decoding of the module 8 counter status according to X1_C and X0_C
The counter must be reset when U1U0 = 11
RSSCK
X1
X0
U1
U0
43
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X1_SX1
X1_S e X0_S synthesis
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X0_SX0
44
U1 and U0 truth table
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5 rArr (0 to 4hellip)
10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
X1_S and X0_S values
Cont | 00 01 11 10000 | 00110 00110 00100 00101001 | 01001 01001 01010 01010010 | 01101 01110 01100 01110011 | 01110 10001 00011 10010 100 | 00011 10110 ------ 10110101 | ------ 11010 ------ 00011 110 | ------ 00011 ------ ------111 | ------ ------ ------ ------
Status U1U0
Is this synthesis of the network safe
No beacuse the donrsquot cares could keep the network stable out of the main cycles
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
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- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
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- Slide 53
- Slide 54
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- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
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- Slide 79
- Slide 80
- Slide 81
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- Slide 83
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- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
bull A left (right) shift register is a register made of DFFs which at each clock positive edge copies the value of its right ((left) FF In the last FF on the right (left ) a ldquo0rdquo is copied This type of shift register is called laquologic shift registerraquo
Shift registers
D0kQ0k
CK DnQn
CK
D0kQ0k
CK Dn-1Qn-1
CK
D0kQ0k
CK Dn-2Qn-2
CK
D0kQ0k
CK D0Q0
CK
ldquo0rdquo
Left shift register
bull For the shift registers too there are many versions parallel in serial output serial input parallel output with or without reset load signals etc etc
bull A shift register is also a counter If upon a reset the input of FF0 is kept to 1 the shift register is incrementally filled with laquo1raquo the number of laquo1raquo (or the position of the leftmost 1) indicates the count value
bull Very often the same register can shift either left or right according to an input control signal This is achieved inserting a 2-way Mux before each D input whose inputs are the outputs of either the left or right FF (Qigrave+1 or Qigrave-1) With this configuration the shift register becomes an Updown counter
11
3-bit shift-register
DFFD Q
QR
A_RESET
DFFD Q
QR
A_RESET
DFFD Q
QR
A_RESET
IN
OUT2OUT1OUT0
CK
12
CK
IN
A_RESET
OUT1
OUT2
OUT0
13
3-bit shift-register
Example 74164 (serial IN-parallel OUT)
bull In this shift register for each positive clock edge (CP) data are shifted one position right (Q0 -gt Q1 Q1-gtQ2 etc) The register has a Master Reset (MR ndash negative true) and the bit inserted in Q0 FF is the AND of the two inputs Dsa e Dsb
bull It must be noticed that the shift operation corresponds arithmetically (without sign) to the division and multiplication by 2 Suppose that in Q0 the MSbit is stored and in Q7 the LSbit
011010102 = 10610
Shift left =gt x2 110101002 = 21210
Shift right =gt 2 001101012 = 5310 Weight 64 32 8 2
14
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
LR CK
0 1 1 0 1 0 1 0
bull There are also arithmetic shift registers In these right shift registers instead of inserting a ldquo0rdquo in the most left FF the same logic value is always inserted
Arithmetic Shift
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
D7 D6 D5 D4 D3 D2 D1 D0
ILDCK Example
11001010ArithmeticShift Right 11100101 interpreted as 2rsquos complement
C2 C2
001101102= 5410 000110112= 2710
bull The arithmetic right shift implements a division by 2 maintaining the sign Obviously the same holds for the positive numbers
negative numbers
15
Shifting right
Rotation
In the computers it is often necessary to implement a right or left rotation of a register content This is achieved by a feedback shift register
D0kQ0k
CK DnQn
CK
D0kQ0k
CK Dn-1Qn-1
CK
D0kQ0k
CK Dn-2Qn-2
CK
D0kQ0k
CK D0Q0
CK
Very often the direction must be programmable In this case the input of D0 (through a MUX 21) can be Q1 or Qnand so on
16
Shift register counters Shift register based counter through EX-OR feedback
Q2Q0
3 bit shift rightD
Q1
110 111 011 101 010 001
Disjoint state diagram
A n FF shift register with an EX-OR feedback (with variable inputs selected) is a NON binary counter for 2n-1 (provided it is not preset with all zeros)
000
100
17
Johnson Counter
000-gt100-gt110-gt111-gt011-gt001-gt000-gt
Disjoint state loop 101-gt010-gt101gt1
A Johnson counter with N FFs counts for 2N Since successive Johnson counter configurations differ by a single bit (adjacent configurations) it can be used for generating glitches-free waveforms
FFDD Q
QR
A_RESET
FFDD Q
QR
A_RESET
FFDD Q
QR
A_RESET
OUT2OUT1OUT0
CK
18
Single laquo1raquo ring counter (directly generating a 1 over n code)
FFDD Q
QR
RESET
FFDD Q
QR
RESET
FFDD Q
QPR
RESET
OUT3OUT1OUT0
CK
FFDD Q
QR
RESET
OUT2
0001-gt1000-gt0100-gt0010-gt0010
The ring counter needs N FFs in order to count for N (while with the binary counters the number of FF necessary for a N count is m= |log2N| that is the first integer greater or equal to log2N)
19
bull Synchronous networks exercises presented in the course are based on the state diagram but only for verification Synchronous network synthesis is made WITHOUT the state diagram usinghellip the brain only by decomposing the network in well know blocks (FFs combinatorial networks and ndash see later ndash counters shift registers etcetc)hellip
20
Design a synchronous logical network (SRL) able to detect palindrome 4 bit configurations (that is configurations that are identical when read left to right or viceversa) which are sequentially inserted in a shift register The D input is significant (and therefore valid for the sequence) only when the input Enable is 1 (whichs is not necessarilly the case for four consecutive input bits) The output P is 1 for a single period when a palindrome configuration is detected after a 4 bit sequence is received Then a new 4 bit sequence must be received (by E conditioned) and detected Direct synthesis
RSS
D
VP
D
VP
Exercise 4 synchronous
21
Enable E
To store a 4 bit sequence a Shift Register with Enable (CE) and Clear (CLR) is used A palindrome configuration is detected when the 1st bit is equal to the 4th bit and the 2nd bit is equal to the 3rd bit
22
A by 4 counter is used upon the 4th clock positive edge the network controls whether the configuration is palindrome The DFF after the decoding of 3 (that is when the counter becomes 0 anew) is used because the configuration control must be delayed un period The ENABLE signal is connected to both components (when 0 both the counter and the shift are disabled)
NB The first inserted bit is sampled when the counter is increased from 0 to 1
NB in this circuit Preset and Clear signals are not connected In Xilinx unconnected control signals are inactive
23
POST-ROUTE SIMULATION
Z output is delayed 10 ns from the clock positive edge because of the switch delay
24
Not valid inputEnable=0
Barrel shifter (rotor)A barrel shifter is a shift register able to shift ldquonrdquo positions in a single period its FFs contents A-H inputs are synchronously stored in the FFs when the LDST is activated When LDST is 0 upon each clock positive edge an anticlockwise n-positions rotation takes place where n is the binary value of S0 S1 and S2 signals For instance if rdquo01110000rdquo is rotated 4 positions at the first clock the content becomes ldquo00000111rdquo If then it is rotated 3 positions it becomes ldquo00111000rdquo
It must be noticed that the component is a register with laquonraquo 81 Muxs each one connected to the D inputs of the FFs The Mux control input value n is given by S0 S1 and S2
25
The circuit in figure is one of the eight 81 MUXs which select the values to be stored in the FFs
The last six right signals are the true and inverted selection signals (S1 S1 S2 S2 S3 e S3) for the 81 MUXs
Each 81 MUX is ORed with preset input value which is used together with LOAD (if LOAD=1 the OR preset value is 0) The FF output is ANDed with LOAD this zeroes all MUX outputs allowing the preset values to be stored in the FFs
The first left 8 signals are the values of the FF D inputs in the preceding period
Xilinx schematic
26
MUX
Preset value
27
Si -gt Mux 81 control signal of each FFAH -gt segnals for Preset Load
LDST=LOADWhen LDST signal is 0 all preset ANDs are zero If LDST is 1 the preset signals are enabled and all MUX outputs are zeroed
Preset AND
28
The LOAD (LDST) signal enables the preset inputs of the FFs (see the ANDs of the previous figure) and at the same time zeroes the output of the FFs (see the FFs cascaded ANDs) so as to select the preset value of the OR input
First 4 FFs Preset values
Xilinx schematicS2 S1 S0 selection signals
A B C HInput signals
LDST load signal
Clock
QA QB QC QH Outputs signals
29
Barrel Shifter
LDST=1upont the first clock positive edge the ldquo10010111rdquo value is loaded into the Barrel Shifter
The different values of Si (1 3 5) cause different device rotation Obviously with 8 sigle shifts the value becomes the initial value ldquo10010111rdquo again
A further active LDST loads a new valute into the the Barrel Shifter
This new value can be rotated again according to S signals
30
This is a typical example of how erroneous is not to laquobusraquo signals a-g qa-g and S0-2 It would have been possible to use a compact decomposable binary notation much easier to interpret where all single signals can be however displayed by laquoopeningraquo the bus
EPROM
X0nZ0m
y0kY0k
Clock
D0kQ0k
FFD0k
CK
D0kQ0kCK
EPROM based synchronous networks
Nowadays instead of the EPROMs PLAs (Programmable Logical Arrays) are used that is devices where the combinatorial functions are optimized (combinatorial functions implementations are not necessarily canonical) The basic principle is however the same
31
Design with Xilinx a synchronous logical network using 374 ALU 74181 a counter and other necessary devices which implements in sequence (after a START) signal the sum of two four bits absolute numbers (A and B) then 2rsquos complements the result then exchanges the two MSBits with the two LSBits and eventually divides arythmetically the result by 2
Example
A=1100 B=0101 =gt Sum 0001 Exchange =gt 0100 (410)2rsquos complement =gt 1100 (-410)Arithmetical division (right shift) by two =gt 1110 (-210)
The solution can be decomposed in three subsystems the control and decoding unit the datapath the input and output registersi
This is the basic architecture of the central unit of any computer
The only difference is that for the computers instead of a fixed sequence of elementary operations a new different sequence is generated for each instruction which must be executed
32
Exercise
33
The synchronous network of figure must add modulo 256 the 8 bit data received in parallel on lines D[70] The sum must be updated each clock and presented on the output lines OUT[70] In case the input data is 68H the sum must not be updated and the input data discarded In addition whenever 6 significant data have been received (that is excluding 68H) the output signal F must be set for one clock period during the reception of the sixth data A reset input is also available which zeroes the outputs and resets the data count Direct design
RSS
D[70] OUT[70]
A_RES
F
Exercise
Clock
34
RSSD[70] OUT[70]
A_RES
F
DEC_68 signal synthesis
DEC(68h)D[70] DEC_68
D[70]
A_RES
CLK
OUT[70]
RSS
D[70] OUT[70]
A_RES
F
35
Modulo 256 adder
Full Adder 8 bit
D[70]
A_RES
374
D
A_RES
Q
Q
CLK
0
1
DEC_68
OE
1
OUT[70]
CIN
0
A[70]
B[70]
36
F signal synthesis
8 bit counter
A_RES
A_RES
EN
RES
CLKU2 U1 U0
DEC(5h)
F
DEC_68
F
Synchronous RESET
37
Exercise
A synchronous sequential network must monitor the data received on the 8 lines D[70] the data received are significant only if N=1 The networks must count modulo 256 how many data are divisible by 4 while EN=1 (excluding 0) The network has two more inputs THREE e RESET The signal THREE when asserted indicates that the value for increasing the count (if the data is divisible by 4) must be 3 (on the contrary if THREE is 0 the count must be increased by 1) The synchronous RESET signal overrides all other signals Direct design
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
38
SynchronousSequentialNetwork
EN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70] (Count)
An input data is divisible by 4 of its two Lsbits (I1 and I0) are zero
An 8 integrated bit register is used for the solution
CK
39
Signal DEC(0) is 1 if all input bits are 0
A signal DIV4 decodes whether the input data is divisible by 4 and NOT zero
DIV4 = I1I0DEC(0)
A signal STORE indicates that EN=1 and the input datum is divisible by 4
STORE = ENDIV4
I[70] DEC(0) DEC(0)
40
REG8BIT
ENSTORE + RESET
CK
FA8 bit
A[70]
B[70]
S[70]
CinCout
THREE
lsquo0rsquo
1
0
lsquo3rsquo
lsquo1rsquo
D[70] Z[70] U[70]
RESET
1
0
lsquo0rsquo
8 Mux21
The FA adds 1 or 3 according to signal THREE (provided the input datum is divisble by 4 and is not 0)
41
Exercise
Design a synchronous sequential network which according to two programming bits X1 and X0 generates the following four output sequences of two bits (signals U1 and U0) which end always with 11
10-01-01-10-11 if X1=0 e X0=010-01-10-01-10-10-11 if X1=0 e X0=100-10-00-11 if X1=1 e X0=001-10-10-10-10-11 if X1=1 e X0=1
The programming signals X1 and X0 are significant only when the output is 11 The network has an synchronous RESET Direct synthesis
RSSCK
X1
X0
U1
U0
42
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5rArr10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
The SSN uses a modulo N counter with N coded by the two input signals X1 e X0 (sampled when U1U0=11)
For the solution we can use a module 8 counter with synchronous RES and a combinatorial network with X1 and X0 as inputs Since the signals X1 and X0 are significant only when U1U0 = 1 they must be sampled (X1_C e X0_C) through two flip-flops when the SSN output is U1U0 = 11 The signals U1 and U0 are the decoding of the module 8 counter status according to X1_C and X0_C
The counter must be reset when U1U0 = 11
RSSCK
X1
X0
U1
U0
43
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X1_SX1
X1_S e X0_S synthesis
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X0_SX0
44
U1 and U0 truth table
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5 rArr (0 to 4hellip)
10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
X1_S and X0_S values
Cont | 00 01 11 10000 | 00110 00110 00100 00101001 | 01001 01001 01010 01010010 | 01101 01110 01100 01110011 | 01110 10001 00011 10010 100 | 00011 10110 ------ 10110101 | ------ 11010 ------ 00011 110 | ------ 00011 ------ ------111 | ------ ------ ------ ------
Status U1U0
Is this synthesis of the network safe
No beacuse the donrsquot cares could keep the network stable out of the main cycles
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
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- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
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-
3-bit shift-register
DFFD Q
QR
A_RESET
DFFD Q
QR
A_RESET
DFFD Q
QR
A_RESET
IN
OUT2OUT1OUT0
CK
12
CK
IN
A_RESET
OUT1
OUT2
OUT0
13
3-bit shift-register
Example 74164 (serial IN-parallel OUT)
bull In this shift register for each positive clock edge (CP) data are shifted one position right (Q0 -gt Q1 Q1-gtQ2 etc) The register has a Master Reset (MR ndash negative true) and the bit inserted in Q0 FF is the AND of the two inputs Dsa e Dsb
bull It must be noticed that the shift operation corresponds arithmetically (without sign) to the division and multiplication by 2 Suppose that in Q0 the MSbit is stored and in Q7 the LSbit
011010102 = 10610
Shift left =gt x2 110101002 = 21210
Shift right =gt 2 001101012 = 5310 Weight 64 32 8 2
14
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
LR CK
0 1 1 0 1 0 1 0
bull There are also arithmetic shift registers In these right shift registers instead of inserting a ldquo0rdquo in the most left FF the same logic value is always inserted
Arithmetic Shift
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
D7 D6 D5 D4 D3 D2 D1 D0
ILDCK Example
11001010ArithmeticShift Right 11100101 interpreted as 2rsquos complement
C2 C2
001101102= 5410 000110112= 2710
bull The arithmetic right shift implements a division by 2 maintaining the sign Obviously the same holds for the positive numbers
negative numbers
15
Shifting right
Rotation
In the computers it is often necessary to implement a right or left rotation of a register content This is achieved by a feedback shift register
D0kQ0k
CK DnQn
CK
D0kQ0k
CK Dn-1Qn-1
CK
D0kQ0k
CK Dn-2Qn-2
CK
D0kQ0k
CK D0Q0
CK
Very often the direction must be programmable In this case the input of D0 (through a MUX 21) can be Q1 or Qnand so on
16
Shift register counters Shift register based counter through EX-OR feedback
Q2Q0
3 bit shift rightD
Q1
110 111 011 101 010 001
Disjoint state diagram
A n FF shift register with an EX-OR feedback (with variable inputs selected) is a NON binary counter for 2n-1 (provided it is not preset with all zeros)
000
100
17
Johnson Counter
000-gt100-gt110-gt111-gt011-gt001-gt000-gt
Disjoint state loop 101-gt010-gt101gt1
A Johnson counter with N FFs counts for 2N Since successive Johnson counter configurations differ by a single bit (adjacent configurations) it can be used for generating glitches-free waveforms
FFDD Q
QR
A_RESET
FFDD Q
QR
A_RESET
FFDD Q
QR
A_RESET
OUT2OUT1OUT0
CK
18
Single laquo1raquo ring counter (directly generating a 1 over n code)
FFDD Q
QR
RESET
FFDD Q
QR
RESET
FFDD Q
QPR
RESET
OUT3OUT1OUT0
CK
FFDD Q
QR
RESET
OUT2
0001-gt1000-gt0100-gt0010-gt0010
The ring counter needs N FFs in order to count for N (while with the binary counters the number of FF necessary for a N count is m= |log2N| that is the first integer greater or equal to log2N)
19
bull Synchronous networks exercises presented in the course are based on the state diagram but only for verification Synchronous network synthesis is made WITHOUT the state diagram usinghellip the brain only by decomposing the network in well know blocks (FFs combinatorial networks and ndash see later ndash counters shift registers etcetc)hellip
20
Design a synchronous logical network (SRL) able to detect palindrome 4 bit configurations (that is configurations that are identical when read left to right or viceversa) which are sequentially inserted in a shift register The D input is significant (and therefore valid for the sequence) only when the input Enable is 1 (whichs is not necessarilly the case for four consecutive input bits) The output P is 1 for a single period when a palindrome configuration is detected after a 4 bit sequence is received Then a new 4 bit sequence must be received (by E conditioned) and detected Direct synthesis
RSS
D
VP
D
VP
Exercise 4 synchronous
21
Enable E
To store a 4 bit sequence a Shift Register with Enable (CE) and Clear (CLR) is used A palindrome configuration is detected when the 1st bit is equal to the 4th bit and the 2nd bit is equal to the 3rd bit
22
A by 4 counter is used upon the 4th clock positive edge the network controls whether the configuration is palindrome The DFF after the decoding of 3 (that is when the counter becomes 0 anew) is used because the configuration control must be delayed un period The ENABLE signal is connected to both components (when 0 both the counter and the shift are disabled)
NB The first inserted bit is sampled when the counter is increased from 0 to 1
NB in this circuit Preset and Clear signals are not connected In Xilinx unconnected control signals are inactive
23
POST-ROUTE SIMULATION
Z output is delayed 10 ns from the clock positive edge because of the switch delay
24
Not valid inputEnable=0
Barrel shifter (rotor)A barrel shifter is a shift register able to shift ldquonrdquo positions in a single period its FFs contents A-H inputs are synchronously stored in the FFs when the LDST is activated When LDST is 0 upon each clock positive edge an anticlockwise n-positions rotation takes place where n is the binary value of S0 S1 and S2 signals For instance if rdquo01110000rdquo is rotated 4 positions at the first clock the content becomes ldquo00000111rdquo If then it is rotated 3 positions it becomes ldquo00111000rdquo
It must be noticed that the component is a register with laquonraquo 81 Muxs each one connected to the D inputs of the FFs The Mux control input value n is given by S0 S1 and S2
25
The circuit in figure is one of the eight 81 MUXs which select the values to be stored in the FFs
The last six right signals are the true and inverted selection signals (S1 S1 S2 S2 S3 e S3) for the 81 MUXs
Each 81 MUX is ORed with preset input value which is used together with LOAD (if LOAD=1 the OR preset value is 0) The FF output is ANDed with LOAD this zeroes all MUX outputs allowing the preset values to be stored in the FFs
The first left 8 signals are the values of the FF D inputs in the preceding period
Xilinx schematic
26
MUX
Preset value
27
Si -gt Mux 81 control signal of each FFAH -gt segnals for Preset Load
LDST=LOADWhen LDST signal is 0 all preset ANDs are zero If LDST is 1 the preset signals are enabled and all MUX outputs are zeroed
Preset AND
28
The LOAD (LDST) signal enables the preset inputs of the FFs (see the ANDs of the previous figure) and at the same time zeroes the output of the FFs (see the FFs cascaded ANDs) so as to select the preset value of the OR input
First 4 FFs Preset values
Xilinx schematicS2 S1 S0 selection signals
A B C HInput signals
LDST load signal
Clock
QA QB QC QH Outputs signals
29
Barrel Shifter
LDST=1upont the first clock positive edge the ldquo10010111rdquo value is loaded into the Barrel Shifter
The different values of Si (1 3 5) cause different device rotation Obviously with 8 sigle shifts the value becomes the initial value ldquo10010111rdquo again
A further active LDST loads a new valute into the the Barrel Shifter
This new value can be rotated again according to S signals
30
This is a typical example of how erroneous is not to laquobusraquo signals a-g qa-g and S0-2 It would have been possible to use a compact decomposable binary notation much easier to interpret where all single signals can be however displayed by laquoopeningraquo the bus
EPROM
X0nZ0m
y0kY0k
Clock
D0kQ0k
FFD0k
CK
D0kQ0kCK
EPROM based synchronous networks
Nowadays instead of the EPROMs PLAs (Programmable Logical Arrays) are used that is devices where the combinatorial functions are optimized (combinatorial functions implementations are not necessarily canonical) The basic principle is however the same
31
Design with Xilinx a synchronous logical network using 374 ALU 74181 a counter and other necessary devices which implements in sequence (after a START) signal the sum of two four bits absolute numbers (A and B) then 2rsquos complements the result then exchanges the two MSBits with the two LSBits and eventually divides arythmetically the result by 2
Example
A=1100 B=0101 =gt Sum 0001 Exchange =gt 0100 (410)2rsquos complement =gt 1100 (-410)Arithmetical division (right shift) by two =gt 1110 (-210)
The solution can be decomposed in three subsystems the control and decoding unit the datapath the input and output registersi
This is the basic architecture of the central unit of any computer
The only difference is that for the computers instead of a fixed sequence of elementary operations a new different sequence is generated for each instruction which must be executed
32
Exercise
33
The synchronous network of figure must add modulo 256 the 8 bit data received in parallel on lines D[70] The sum must be updated each clock and presented on the output lines OUT[70] In case the input data is 68H the sum must not be updated and the input data discarded In addition whenever 6 significant data have been received (that is excluding 68H) the output signal F must be set for one clock period during the reception of the sixth data A reset input is also available which zeroes the outputs and resets the data count Direct design
RSS
D[70] OUT[70]
A_RES
F
Exercise
Clock
34
RSSD[70] OUT[70]
A_RES
F
DEC_68 signal synthesis
DEC(68h)D[70] DEC_68
D[70]
A_RES
CLK
OUT[70]
RSS
D[70] OUT[70]
A_RES
F
35
Modulo 256 adder
Full Adder 8 bit
D[70]
A_RES
374
D
A_RES
Q
Q
CLK
0
1
DEC_68
OE
1
OUT[70]
CIN
0
A[70]
B[70]
36
F signal synthesis
8 bit counter
A_RES
A_RES
EN
RES
CLKU2 U1 U0
DEC(5h)
F
DEC_68
F
Synchronous RESET
37
Exercise
A synchronous sequential network must monitor the data received on the 8 lines D[70] the data received are significant only if N=1 The networks must count modulo 256 how many data are divisible by 4 while EN=1 (excluding 0) The network has two more inputs THREE e RESET The signal THREE when asserted indicates that the value for increasing the count (if the data is divisible by 4) must be 3 (on the contrary if THREE is 0 the count must be increased by 1) The synchronous RESET signal overrides all other signals Direct design
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
38
SynchronousSequentialNetwork
EN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70] (Count)
An input data is divisible by 4 of its two Lsbits (I1 and I0) are zero
An 8 integrated bit register is used for the solution
CK
39
Signal DEC(0) is 1 if all input bits are 0
A signal DIV4 decodes whether the input data is divisible by 4 and NOT zero
DIV4 = I1I0DEC(0)
A signal STORE indicates that EN=1 and the input datum is divisible by 4
STORE = ENDIV4
I[70] DEC(0) DEC(0)
40
REG8BIT
ENSTORE + RESET
CK
FA8 bit
A[70]
B[70]
S[70]
CinCout
THREE
lsquo0rsquo
1
0
lsquo3rsquo
lsquo1rsquo
D[70] Z[70] U[70]
RESET
1
0
lsquo0rsquo
8 Mux21
The FA adds 1 or 3 according to signal THREE (provided the input datum is divisble by 4 and is not 0)
41
Exercise
Design a synchronous sequential network which according to two programming bits X1 and X0 generates the following four output sequences of two bits (signals U1 and U0) which end always with 11
10-01-01-10-11 if X1=0 e X0=010-01-10-01-10-10-11 if X1=0 e X0=100-10-00-11 if X1=1 e X0=001-10-10-10-10-11 if X1=1 e X0=1
The programming signals X1 and X0 are significant only when the output is 11 The network has an synchronous RESET Direct synthesis
RSSCK
X1
X0
U1
U0
42
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5rArr10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
The SSN uses a modulo N counter with N coded by the two input signals X1 e X0 (sampled when U1U0=11)
For the solution we can use a module 8 counter with synchronous RES and a combinatorial network with X1 and X0 as inputs Since the signals X1 and X0 are significant only when U1U0 = 1 they must be sampled (X1_C e X0_C) through two flip-flops when the SSN output is U1U0 = 11 The signals U1 and U0 are the decoding of the module 8 counter status according to X1_C and X0_C
The counter must be reset when U1U0 = 11
RSSCK
X1
X0
U1
U0
43
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X1_SX1
X1_S e X0_S synthesis
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X0_SX0
44
U1 and U0 truth table
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5 rArr (0 to 4hellip)
10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
X1_S and X0_S values
Cont | 00 01 11 10000 | 00110 00110 00100 00101001 | 01001 01001 01010 01010010 | 01101 01110 01100 01110011 | 01110 10001 00011 10010 100 | 00011 10110 ------ 10110101 | ------ 11010 ------ 00011 110 | ------ 00011 ------ ------111 | ------ ------ ------ ------
Status U1U0
Is this synthesis of the network safe
No beacuse the donrsquot cares could keep the network stable out of the main cycles
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
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- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
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- Slide 62
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- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
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- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
CK
IN
A_RESET
OUT1
OUT2
OUT0
13
3-bit shift-register
Example 74164 (serial IN-parallel OUT)
bull In this shift register for each positive clock edge (CP) data are shifted one position right (Q0 -gt Q1 Q1-gtQ2 etc) The register has a Master Reset (MR ndash negative true) and the bit inserted in Q0 FF is the AND of the two inputs Dsa e Dsb
bull It must be noticed that the shift operation corresponds arithmetically (without sign) to the division and multiplication by 2 Suppose that in Q0 the MSbit is stored and in Q7 the LSbit
011010102 = 10610
Shift left =gt x2 110101002 = 21210
Shift right =gt 2 001101012 = 5310 Weight 64 32 8 2
14
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
LR CK
0 1 1 0 1 0 1 0
bull There are also arithmetic shift registers In these right shift registers instead of inserting a ldquo0rdquo in the most left FF the same logic value is always inserted
Arithmetic Shift
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
D7 D6 D5 D4 D3 D2 D1 D0
ILDCK Example
11001010ArithmeticShift Right 11100101 interpreted as 2rsquos complement
C2 C2
001101102= 5410 000110112= 2710
bull The arithmetic right shift implements a division by 2 maintaining the sign Obviously the same holds for the positive numbers
negative numbers
15
Shifting right
Rotation
In the computers it is often necessary to implement a right or left rotation of a register content This is achieved by a feedback shift register
D0kQ0k
CK DnQn
CK
D0kQ0k
CK Dn-1Qn-1
CK
D0kQ0k
CK Dn-2Qn-2
CK
D0kQ0k
CK D0Q0
CK
Very often the direction must be programmable In this case the input of D0 (through a MUX 21) can be Q1 or Qnand so on
16
Shift register counters Shift register based counter through EX-OR feedback
Q2Q0
3 bit shift rightD
Q1
110 111 011 101 010 001
Disjoint state diagram
A n FF shift register with an EX-OR feedback (with variable inputs selected) is a NON binary counter for 2n-1 (provided it is not preset with all zeros)
000
100
17
Johnson Counter
000-gt100-gt110-gt111-gt011-gt001-gt000-gt
Disjoint state loop 101-gt010-gt101gt1
A Johnson counter with N FFs counts for 2N Since successive Johnson counter configurations differ by a single bit (adjacent configurations) it can be used for generating glitches-free waveforms
FFDD Q
QR
A_RESET
FFDD Q
QR
A_RESET
FFDD Q
QR
A_RESET
OUT2OUT1OUT0
CK
18
Single laquo1raquo ring counter (directly generating a 1 over n code)
FFDD Q
QR
RESET
FFDD Q
QR
RESET
FFDD Q
QPR
RESET
OUT3OUT1OUT0
CK
FFDD Q
QR
RESET
OUT2
0001-gt1000-gt0100-gt0010-gt0010
The ring counter needs N FFs in order to count for N (while with the binary counters the number of FF necessary for a N count is m= |log2N| that is the first integer greater or equal to log2N)
19
bull Synchronous networks exercises presented in the course are based on the state diagram but only for verification Synchronous network synthesis is made WITHOUT the state diagram usinghellip the brain only by decomposing the network in well know blocks (FFs combinatorial networks and ndash see later ndash counters shift registers etcetc)hellip
20
Design a synchronous logical network (SRL) able to detect palindrome 4 bit configurations (that is configurations that are identical when read left to right or viceversa) which are sequentially inserted in a shift register The D input is significant (and therefore valid for the sequence) only when the input Enable is 1 (whichs is not necessarilly the case for four consecutive input bits) The output P is 1 for a single period when a palindrome configuration is detected after a 4 bit sequence is received Then a new 4 bit sequence must be received (by E conditioned) and detected Direct synthesis
RSS
D
VP
D
VP
Exercise 4 synchronous
21
Enable E
To store a 4 bit sequence a Shift Register with Enable (CE) and Clear (CLR) is used A palindrome configuration is detected when the 1st bit is equal to the 4th bit and the 2nd bit is equal to the 3rd bit
22
A by 4 counter is used upon the 4th clock positive edge the network controls whether the configuration is palindrome The DFF after the decoding of 3 (that is when the counter becomes 0 anew) is used because the configuration control must be delayed un period The ENABLE signal is connected to both components (when 0 both the counter and the shift are disabled)
NB The first inserted bit is sampled when the counter is increased from 0 to 1
NB in this circuit Preset and Clear signals are not connected In Xilinx unconnected control signals are inactive
23
POST-ROUTE SIMULATION
Z output is delayed 10 ns from the clock positive edge because of the switch delay
24
Not valid inputEnable=0
Barrel shifter (rotor)A barrel shifter is a shift register able to shift ldquonrdquo positions in a single period its FFs contents A-H inputs are synchronously stored in the FFs when the LDST is activated When LDST is 0 upon each clock positive edge an anticlockwise n-positions rotation takes place where n is the binary value of S0 S1 and S2 signals For instance if rdquo01110000rdquo is rotated 4 positions at the first clock the content becomes ldquo00000111rdquo If then it is rotated 3 positions it becomes ldquo00111000rdquo
It must be noticed that the component is a register with laquonraquo 81 Muxs each one connected to the D inputs of the FFs The Mux control input value n is given by S0 S1 and S2
25
The circuit in figure is one of the eight 81 MUXs which select the values to be stored in the FFs
The last six right signals are the true and inverted selection signals (S1 S1 S2 S2 S3 e S3) for the 81 MUXs
Each 81 MUX is ORed with preset input value which is used together with LOAD (if LOAD=1 the OR preset value is 0) The FF output is ANDed with LOAD this zeroes all MUX outputs allowing the preset values to be stored in the FFs
The first left 8 signals are the values of the FF D inputs in the preceding period
Xilinx schematic
26
MUX
Preset value
27
Si -gt Mux 81 control signal of each FFAH -gt segnals for Preset Load
LDST=LOADWhen LDST signal is 0 all preset ANDs are zero If LDST is 1 the preset signals are enabled and all MUX outputs are zeroed
Preset AND
28
The LOAD (LDST) signal enables the preset inputs of the FFs (see the ANDs of the previous figure) and at the same time zeroes the output of the FFs (see the FFs cascaded ANDs) so as to select the preset value of the OR input
First 4 FFs Preset values
Xilinx schematicS2 S1 S0 selection signals
A B C HInput signals
LDST load signal
Clock
QA QB QC QH Outputs signals
29
Barrel Shifter
LDST=1upont the first clock positive edge the ldquo10010111rdquo value is loaded into the Barrel Shifter
The different values of Si (1 3 5) cause different device rotation Obviously with 8 sigle shifts the value becomes the initial value ldquo10010111rdquo again
A further active LDST loads a new valute into the the Barrel Shifter
This new value can be rotated again according to S signals
30
This is a typical example of how erroneous is not to laquobusraquo signals a-g qa-g and S0-2 It would have been possible to use a compact decomposable binary notation much easier to interpret where all single signals can be however displayed by laquoopeningraquo the bus
EPROM
X0nZ0m
y0kY0k
Clock
D0kQ0k
FFD0k
CK
D0kQ0kCK
EPROM based synchronous networks
Nowadays instead of the EPROMs PLAs (Programmable Logical Arrays) are used that is devices where the combinatorial functions are optimized (combinatorial functions implementations are not necessarily canonical) The basic principle is however the same
31
Design with Xilinx a synchronous logical network using 374 ALU 74181 a counter and other necessary devices which implements in sequence (after a START) signal the sum of two four bits absolute numbers (A and B) then 2rsquos complements the result then exchanges the two MSBits with the two LSBits and eventually divides arythmetically the result by 2
Example
A=1100 B=0101 =gt Sum 0001 Exchange =gt 0100 (410)2rsquos complement =gt 1100 (-410)Arithmetical division (right shift) by two =gt 1110 (-210)
The solution can be decomposed in three subsystems the control and decoding unit the datapath the input and output registersi
This is the basic architecture of the central unit of any computer
The only difference is that for the computers instead of a fixed sequence of elementary operations a new different sequence is generated for each instruction which must be executed
32
Exercise
33
The synchronous network of figure must add modulo 256 the 8 bit data received in parallel on lines D[70] The sum must be updated each clock and presented on the output lines OUT[70] In case the input data is 68H the sum must not be updated and the input data discarded In addition whenever 6 significant data have been received (that is excluding 68H) the output signal F must be set for one clock period during the reception of the sixth data A reset input is also available which zeroes the outputs and resets the data count Direct design
RSS
D[70] OUT[70]
A_RES
F
Exercise
Clock
34
RSSD[70] OUT[70]
A_RES
F
DEC_68 signal synthesis
DEC(68h)D[70] DEC_68
D[70]
A_RES
CLK
OUT[70]
RSS
D[70] OUT[70]
A_RES
F
35
Modulo 256 adder
Full Adder 8 bit
D[70]
A_RES
374
D
A_RES
Q
Q
CLK
0
1
DEC_68
OE
1
OUT[70]
CIN
0
A[70]
B[70]
36
F signal synthesis
8 bit counter
A_RES
A_RES
EN
RES
CLKU2 U1 U0
DEC(5h)
F
DEC_68
F
Synchronous RESET
37
Exercise
A synchronous sequential network must monitor the data received on the 8 lines D[70] the data received are significant only if N=1 The networks must count modulo 256 how many data are divisible by 4 while EN=1 (excluding 0) The network has two more inputs THREE e RESET The signal THREE when asserted indicates that the value for increasing the count (if the data is divisible by 4) must be 3 (on the contrary if THREE is 0 the count must be increased by 1) The synchronous RESET signal overrides all other signals Direct design
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
38
SynchronousSequentialNetwork
EN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70] (Count)
An input data is divisible by 4 of its two Lsbits (I1 and I0) are zero
An 8 integrated bit register is used for the solution
CK
39
Signal DEC(0) is 1 if all input bits are 0
A signal DIV4 decodes whether the input data is divisible by 4 and NOT zero
DIV4 = I1I0DEC(0)
A signal STORE indicates that EN=1 and the input datum is divisible by 4
STORE = ENDIV4
I[70] DEC(0) DEC(0)
40
REG8BIT
ENSTORE + RESET
CK
FA8 bit
A[70]
B[70]
S[70]
CinCout
THREE
lsquo0rsquo
1
0
lsquo3rsquo
lsquo1rsquo
D[70] Z[70] U[70]
RESET
1
0
lsquo0rsquo
8 Mux21
The FA adds 1 or 3 according to signal THREE (provided the input datum is divisble by 4 and is not 0)
41
Exercise
Design a synchronous sequential network which according to two programming bits X1 and X0 generates the following four output sequences of two bits (signals U1 and U0) which end always with 11
10-01-01-10-11 if X1=0 e X0=010-01-10-01-10-10-11 if X1=0 e X0=100-10-00-11 if X1=1 e X0=001-10-10-10-10-11 if X1=1 e X0=1
The programming signals X1 and X0 are significant only when the output is 11 The network has an synchronous RESET Direct synthesis
RSSCK
X1
X0
U1
U0
42
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5rArr10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
The SSN uses a modulo N counter with N coded by the two input signals X1 e X0 (sampled when U1U0=11)
For the solution we can use a module 8 counter with synchronous RES and a combinatorial network with X1 and X0 as inputs Since the signals X1 and X0 are significant only when U1U0 = 1 they must be sampled (X1_C e X0_C) through two flip-flops when the SSN output is U1U0 = 11 The signals U1 and U0 are the decoding of the module 8 counter status according to X1_C and X0_C
The counter must be reset when U1U0 = 11
RSSCK
X1
X0
U1
U0
43
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X1_SX1
X1_S e X0_S synthesis
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X0_SX0
44
U1 and U0 truth table
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5 rArr (0 to 4hellip)
10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
X1_S and X0_S values
Cont | 00 01 11 10000 | 00110 00110 00100 00101001 | 01001 01001 01010 01010010 | 01101 01110 01100 01110011 | 01110 10001 00011 10010 100 | 00011 10110 ------ 10110101 | ------ 11010 ------ 00011 110 | ------ 00011 ------ ------111 | ------ ------ ------ ------
Status U1U0
Is this synthesis of the network safe
No beacuse the donrsquot cares could keep the network stable out of the main cycles
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
- Slide 59
- Slide 60
- Slide 61
- Slide 62
- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
Example 74164 (serial IN-parallel OUT)
bull In this shift register for each positive clock edge (CP) data are shifted one position right (Q0 -gt Q1 Q1-gtQ2 etc) The register has a Master Reset (MR ndash negative true) and the bit inserted in Q0 FF is the AND of the two inputs Dsa e Dsb
bull It must be noticed that the shift operation corresponds arithmetically (without sign) to the division and multiplication by 2 Suppose that in Q0 the MSbit is stored and in Q7 the LSbit
011010102 = 10610
Shift left =gt x2 110101002 = 21210
Shift right =gt 2 001101012 = 5310 Weight 64 32 8 2
14
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
LR CK
0 1 1 0 1 0 1 0
bull There are also arithmetic shift registers In these right shift registers instead of inserting a ldquo0rdquo in the most left FF the same logic value is always inserted
Arithmetic Shift
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
D7 D6 D5 D4 D3 D2 D1 D0
ILDCK Example
11001010ArithmeticShift Right 11100101 interpreted as 2rsquos complement
C2 C2
001101102= 5410 000110112= 2710
bull The arithmetic right shift implements a division by 2 maintaining the sign Obviously the same holds for the positive numbers
negative numbers
15
Shifting right
Rotation
In the computers it is often necessary to implement a right or left rotation of a register content This is achieved by a feedback shift register
D0kQ0k
CK DnQn
CK
D0kQ0k
CK Dn-1Qn-1
CK
D0kQ0k
CK Dn-2Qn-2
CK
D0kQ0k
CK D0Q0
CK
Very often the direction must be programmable In this case the input of D0 (through a MUX 21) can be Q1 or Qnand so on
16
Shift register counters Shift register based counter through EX-OR feedback
Q2Q0
3 bit shift rightD
Q1
110 111 011 101 010 001
Disjoint state diagram
A n FF shift register with an EX-OR feedback (with variable inputs selected) is a NON binary counter for 2n-1 (provided it is not preset with all zeros)
000
100
17
Johnson Counter
000-gt100-gt110-gt111-gt011-gt001-gt000-gt
Disjoint state loop 101-gt010-gt101gt1
A Johnson counter with N FFs counts for 2N Since successive Johnson counter configurations differ by a single bit (adjacent configurations) it can be used for generating glitches-free waveforms
FFDD Q
QR
A_RESET
FFDD Q
QR
A_RESET
FFDD Q
QR
A_RESET
OUT2OUT1OUT0
CK
18
Single laquo1raquo ring counter (directly generating a 1 over n code)
FFDD Q
QR
RESET
FFDD Q
QR
RESET
FFDD Q
QPR
RESET
OUT3OUT1OUT0
CK
FFDD Q
QR
RESET
OUT2
0001-gt1000-gt0100-gt0010-gt0010
The ring counter needs N FFs in order to count for N (while with the binary counters the number of FF necessary for a N count is m= |log2N| that is the first integer greater or equal to log2N)
19
bull Synchronous networks exercises presented in the course are based on the state diagram but only for verification Synchronous network synthesis is made WITHOUT the state diagram usinghellip the brain only by decomposing the network in well know blocks (FFs combinatorial networks and ndash see later ndash counters shift registers etcetc)hellip
20
Design a synchronous logical network (SRL) able to detect palindrome 4 bit configurations (that is configurations that are identical when read left to right or viceversa) which are sequentially inserted in a shift register The D input is significant (and therefore valid for the sequence) only when the input Enable is 1 (whichs is not necessarilly the case for four consecutive input bits) The output P is 1 for a single period when a palindrome configuration is detected after a 4 bit sequence is received Then a new 4 bit sequence must be received (by E conditioned) and detected Direct synthesis
RSS
D
VP
D
VP
Exercise 4 synchronous
21
Enable E
To store a 4 bit sequence a Shift Register with Enable (CE) and Clear (CLR) is used A palindrome configuration is detected when the 1st bit is equal to the 4th bit and the 2nd bit is equal to the 3rd bit
22
A by 4 counter is used upon the 4th clock positive edge the network controls whether the configuration is palindrome The DFF after the decoding of 3 (that is when the counter becomes 0 anew) is used because the configuration control must be delayed un period The ENABLE signal is connected to both components (when 0 both the counter and the shift are disabled)
NB The first inserted bit is sampled when the counter is increased from 0 to 1
NB in this circuit Preset and Clear signals are not connected In Xilinx unconnected control signals are inactive
23
POST-ROUTE SIMULATION
Z output is delayed 10 ns from the clock positive edge because of the switch delay
24
Not valid inputEnable=0
Barrel shifter (rotor)A barrel shifter is a shift register able to shift ldquonrdquo positions in a single period its FFs contents A-H inputs are synchronously stored in the FFs when the LDST is activated When LDST is 0 upon each clock positive edge an anticlockwise n-positions rotation takes place where n is the binary value of S0 S1 and S2 signals For instance if rdquo01110000rdquo is rotated 4 positions at the first clock the content becomes ldquo00000111rdquo If then it is rotated 3 positions it becomes ldquo00111000rdquo
It must be noticed that the component is a register with laquonraquo 81 Muxs each one connected to the D inputs of the FFs The Mux control input value n is given by S0 S1 and S2
25
The circuit in figure is one of the eight 81 MUXs which select the values to be stored in the FFs
The last six right signals are the true and inverted selection signals (S1 S1 S2 S2 S3 e S3) for the 81 MUXs
Each 81 MUX is ORed with preset input value which is used together with LOAD (if LOAD=1 the OR preset value is 0) The FF output is ANDed with LOAD this zeroes all MUX outputs allowing the preset values to be stored in the FFs
The first left 8 signals are the values of the FF D inputs in the preceding period
Xilinx schematic
26
MUX
Preset value
27
Si -gt Mux 81 control signal of each FFAH -gt segnals for Preset Load
LDST=LOADWhen LDST signal is 0 all preset ANDs are zero If LDST is 1 the preset signals are enabled and all MUX outputs are zeroed
Preset AND
28
The LOAD (LDST) signal enables the preset inputs of the FFs (see the ANDs of the previous figure) and at the same time zeroes the output of the FFs (see the FFs cascaded ANDs) so as to select the preset value of the OR input
First 4 FFs Preset values
Xilinx schematicS2 S1 S0 selection signals
A B C HInput signals
LDST load signal
Clock
QA QB QC QH Outputs signals
29
Barrel Shifter
LDST=1upont the first clock positive edge the ldquo10010111rdquo value is loaded into the Barrel Shifter
The different values of Si (1 3 5) cause different device rotation Obviously with 8 sigle shifts the value becomes the initial value ldquo10010111rdquo again
A further active LDST loads a new valute into the the Barrel Shifter
This new value can be rotated again according to S signals
30
This is a typical example of how erroneous is not to laquobusraquo signals a-g qa-g and S0-2 It would have been possible to use a compact decomposable binary notation much easier to interpret where all single signals can be however displayed by laquoopeningraquo the bus
EPROM
X0nZ0m
y0kY0k
Clock
D0kQ0k
FFD0k
CK
D0kQ0kCK
EPROM based synchronous networks
Nowadays instead of the EPROMs PLAs (Programmable Logical Arrays) are used that is devices where the combinatorial functions are optimized (combinatorial functions implementations are not necessarily canonical) The basic principle is however the same
31
Design with Xilinx a synchronous logical network using 374 ALU 74181 a counter and other necessary devices which implements in sequence (after a START) signal the sum of two four bits absolute numbers (A and B) then 2rsquos complements the result then exchanges the two MSBits with the two LSBits and eventually divides arythmetically the result by 2
Example
A=1100 B=0101 =gt Sum 0001 Exchange =gt 0100 (410)2rsquos complement =gt 1100 (-410)Arithmetical division (right shift) by two =gt 1110 (-210)
The solution can be decomposed in three subsystems the control and decoding unit the datapath the input and output registersi
This is the basic architecture of the central unit of any computer
The only difference is that for the computers instead of a fixed sequence of elementary operations a new different sequence is generated for each instruction which must be executed
32
Exercise
33
The synchronous network of figure must add modulo 256 the 8 bit data received in parallel on lines D[70] The sum must be updated each clock and presented on the output lines OUT[70] In case the input data is 68H the sum must not be updated and the input data discarded In addition whenever 6 significant data have been received (that is excluding 68H) the output signal F must be set for one clock period during the reception of the sixth data A reset input is also available which zeroes the outputs and resets the data count Direct design
RSS
D[70] OUT[70]
A_RES
F
Exercise
Clock
34
RSSD[70] OUT[70]
A_RES
F
DEC_68 signal synthesis
DEC(68h)D[70] DEC_68
D[70]
A_RES
CLK
OUT[70]
RSS
D[70] OUT[70]
A_RES
F
35
Modulo 256 adder
Full Adder 8 bit
D[70]
A_RES
374
D
A_RES
Q
Q
CLK
0
1
DEC_68
OE
1
OUT[70]
CIN
0
A[70]
B[70]
36
F signal synthesis
8 bit counter
A_RES
A_RES
EN
RES
CLKU2 U1 U0
DEC(5h)
F
DEC_68
F
Synchronous RESET
37
Exercise
A synchronous sequential network must monitor the data received on the 8 lines D[70] the data received are significant only if N=1 The networks must count modulo 256 how many data are divisible by 4 while EN=1 (excluding 0) The network has two more inputs THREE e RESET The signal THREE when asserted indicates that the value for increasing the count (if the data is divisible by 4) must be 3 (on the contrary if THREE is 0 the count must be increased by 1) The synchronous RESET signal overrides all other signals Direct design
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
38
SynchronousSequentialNetwork
EN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70] (Count)
An input data is divisible by 4 of its two Lsbits (I1 and I0) are zero
An 8 integrated bit register is used for the solution
CK
39
Signal DEC(0) is 1 if all input bits are 0
A signal DIV4 decodes whether the input data is divisible by 4 and NOT zero
DIV4 = I1I0DEC(0)
A signal STORE indicates that EN=1 and the input datum is divisible by 4
STORE = ENDIV4
I[70] DEC(0) DEC(0)
40
REG8BIT
ENSTORE + RESET
CK
FA8 bit
A[70]
B[70]
S[70]
CinCout
THREE
lsquo0rsquo
1
0
lsquo3rsquo
lsquo1rsquo
D[70] Z[70] U[70]
RESET
1
0
lsquo0rsquo
8 Mux21
The FA adds 1 or 3 according to signal THREE (provided the input datum is divisble by 4 and is not 0)
41
Exercise
Design a synchronous sequential network which according to two programming bits X1 and X0 generates the following four output sequences of two bits (signals U1 and U0) which end always with 11
10-01-01-10-11 if X1=0 e X0=010-01-10-01-10-10-11 if X1=0 e X0=100-10-00-11 if X1=1 e X0=001-10-10-10-10-11 if X1=1 e X0=1
The programming signals X1 and X0 are significant only when the output is 11 The network has an synchronous RESET Direct synthesis
RSSCK
X1
X0
U1
U0
42
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5rArr10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
The SSN uses a modulo N counter with N coded by the two input signals X1 e X0 (sampled when U1U0=11)
For the solution we can use a module 8 counter with synchronous RES and a combinatorial network with X1 and X0 as inputs Since the signals X1 and X0 are significant only when U1U0 = 1 they must be sampled (X1_C e X0_C) through two flip-flops when the SSN output is U1U0 = 11 The signals U1 and U0 are the decoding of the module 8 counter status according to X1_C and X0_C
The counter must be reset when U1U0 = 11
RSSCK
X1
X0
U1
U0
43
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X1_SX1
X1_S e X0_S synthesis
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X0_SX0
44
U1 and U0 truth table
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5 rArr (0 to 4hellip)
10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
X1_S and X0_S values
Cont | 00 01 11 10000 | 00110 00110 00100 00101001 | 01001 01001 01010 01010010 | 01101 01110 01100 01110011 | 01110 10001 00011 10010 100 | 00011 10110 ------ 10110101 | ------ 11010 ------ 00011 110 | ------ 00011 ------ ------111 | ------ ------ ------ ------
Status U1U0
Is this synthesis of the network safe
No beacuse the donrsquot cares could keep the network stable out of the main cycles
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
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- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
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- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
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- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
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- Slide 88
-
bull There are also arithmetic shift registers In these right shift registers instead of inserting a ldquo0rdquo in the most left FF the same logic value is always inserted
Arithmetic Shift
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
D7 D6 D5 D4 D3 D2 D1 D0
ILDCK Example
11001010ArithmeticShift Right 11100101 interpreted as 2rsquos complement
C2 C2
001101102= 5410 000110112= 2710
bull The arithmetic right shift implements a division by 2 maintaining the sign Obviously the same holds for the positive numbers
negative numbers
15
Shifting right
Rotation
In the computers it is often necessary to implement a right or left rotation of a register content This is achieved by a feedback shift register
D0kQ0k
CK DnQn
CK
D0kQ0k
CK Dn-1Qn-1
CK
D0kQ0k
CK Dn-2Qn-2
CK
D0kQ0k
CK D0Q0
CK
Very often the direction must be programmable In this case the input of D0 (through a MUX 21) can be Q1 or Qnand so on
16
Shift register counters Shift register based counter through EX-OR feedback
Q2Q0
3 bit shift rightD
Q1
110 111 011 101 010 001
Disjoint state diagram
A n FF shift register with an EX-OR feedback (with variable inputs selected) is a NON binary counter for 2n-1 (provided it is not preset with all zeros)
000
100
17
Johnson Counter
000-gt100-gt110-gt111-gt011-gt001-gt000-gt
Disjoint state loop 101-gt010-gt101gt1
A Johnson counter with N FFs counts for 2N Since successive Johnson counter configurations differ by a single bit (adjacent configurations) it can be used for generating glitches-free waveforms
FFDD Q
QR
A_RESET
FFDD Q
QR
A_RESET
FFDD Q
QR
A_RESET
OUT2OUT1OUT0
CK
18
Single laquo1raquo ring counter (directly generating a 1 over n code)
FFDD Q
QR
RESET
FFDD Q
QR
RESET
FFDD Q
QPR
RESET
OUT3OUT1OUT0
CK
FFDD Q
QR
RESET
OUT2
0001-gt1000-gt0100-gt0010-gt0010
The ring counter needs N FFs in order to count for N (while with the binary counters the number of FF necessary for a N count is m= |log2N| that is the first integer greater or equal to log2N)
19
bull Synchronous networks exercises presented in the course are based on the state diagram but only for verification Synchronous network synthesis is made WITHOUT the state diagram usinghellip the brain only by decomposing the network in well know blocks (FFs combinatorial networks and ndash see later ndash counters shift registers etcetc)hellip
20
Design a synchronous logical network (SRL) able to detect palindrome 4 bit configurations (that is configurations that are identical when read left to right or viceversa) which are sequentially inserted in a shift register The D input is significant (and therefore valid for the sequence) only when the input Enable is 1 (whichs is not necessarilly the case for four consecutive input bits) The output P is 1 for a single period when a palindrome configuration is detected after a 4 bit sequence is received Then a new 4 bit sequence must be received (by E conditioned) and detected Direct synthesis
RSS
D
VP
D
VP
Exercise 4 synchronous
21
Enable E
To store a 4 bit sequence a Shift Register with Enable (CE) and Clear (CLR) is used A palindrome configuration is detected when the 1st bit is equal to the 4th bit and the 2nd bit is equal to the 3rd bit
22
A by 4 counter is used upon the 4th clock positive edge the network controls whether the configuration is palindrome The DFF after the decoding of 3 (that is when the counter becomes 0 anew) is used because the configuration control must be delayed un period The ENABLE signal is connected to both components (when 0 both the counter and the shift are disabled)
NB The first inserted bit is sampled when the counter is increased from 0 to 1
NB in this circuit Preset and Clear signals are not connected In Xilinx unconnected control signals are inactive
23
POST-ROUTE SIMULATION
Z output is delayed 10 ns from the clock positive edge because of the switch delay
24
Not valid inputEnable=0
Barrel shifter (rotor)A barrel shifter is a shift register able to shift ldquonrdquo positions in a single period its FFs contents A-H inputs are synchronously stored in the FFs when the LDST is activated When LDST is 0 upon each clock positive edge an anticlockwise n-positions rotation takes place where n is the binary value of S0 S1 and S2 signals For instance if rdquo01110000rdquo is rotated 4 positions at the first clock the content becomes ldquo00000111rdquo If then it is rotated 3 positions it becomes ldquo00111000rdquo
It must be noticed that the component is a register with laquonraquo 81 Muxs each one connected to the D inputs of the FFs The Mux control input value n is given by S0 S1 and S2
25
The circuit in figure is one of the eight 81 MUXs which select the values to be stored in the FFs
The last six right signals are the true and inverted selection signals (S1 S1 S2 S2 S3 e S3) for the 81 MUXs
Each 81 MUX is ORed with preset input value which is used together with LOAD (if LOAD=1 the OR preset value is 0) The FF output is ANDed with LOAD this zeroes all MUX outputs allowing the preset values to be stored in the FFs
The first left 8 signals are the values of the FF D inputs in the preceding period
Xilinx schematic
26
MUX
Preset value
27
Si -gt Mux 81 control signal of each FFAH -gt segnals for Preset Load
LDST=LOADWhen LDST signal is 0 all preset ANDs are zero If LDST is 1 the preset signals are enabled and all MUX outputs are zeroed
Preset AND
28
The LOAD (LDST) signal enables the preset inputs of the FFs (see the ANDs of the previous figure) and at the same time zeroes the output of the FFs (see the FFs cascaded ANDs) so as to select the preset value of the OR input
First 4 FFs Preset values
Xilinx schematicS2 S1 S0 selection signals
A B C HInput signals
LDST load signal
Clock
QA QB QC QH Outputs signals
29
Barrel Shifter
LDST=1upont the first clock positive edge the ldquo10010111rdquo value is loaded into the Barrel Shifter
The different values of Si (1 3 5) cause different device rotation Obviously with 8 sigle shifts the value becomes the initial value ldquo10010111rdquo again
A further active LDST loads a new valute into the the Barrel Shifter
This new value can be rotated again according to S signals
30
This is a typical example of how erroneous is not to laquobusraquo signals a-g qa-g and S0-2 It would have been possible to use a compact decomposable binary notation much easier to interpret where all single signals can be however displayed by laquoopeningraquo the bus
EPROM
X0nZ0m
y0kY0k
Clock
D0kQ0k
FFD0k
CK
D0kQ0kCK
EPROM based synchronous networks
Nowadays instead of the EPROMs PLAs (Programmable Logical Arrays) are used that is devices where the combinatorial functions are optimized (combinatorial functions implementations are not necessarily canonical) The basic principle is however the same
31
Design with Xilinx a synchronous logical network using 374 ALU 74181 a counter and other necessary devices which implements in sequence (after a START) signal the sum of two four bits absolute numbers (A and B) then 2rsquos complements the result then exchanges the two MSBits with the two LSBits and eventually divides arythmetically the result by 2
Example
A=1100 B=0101 =gt Sum 0001 Exchange =gt 0100 (410)2rsquos complement =gt 1100 (-410)Arithmetical division (right shift) by two =gt 1110 (-210)
The solution can be decomposed in three subsystems the control and decoding unit the datapath the input and output registersi
This is the basic architecture of the central unit of any computer
The only difference is that for the computers instead of a fixed sequence of elementary operations a new different sequence is generated for each instruction which must be executed
32
Exercise
33
The synchronous network of figure must add modulo 256 the 8 bit data received in parallel on lines D[70] The sum must be updated each clock and presented on the output lines OUT[70] In case the input data is 68H the sum must not be updated and the input data discarded In addition whenever 6 significant data have been received (that is excluding 68H) the output signal F must be set for one clock period during the reception of the sixth data A reset input is also available which zeroes the outputs and resets the data count Direct design
RSS
D[70] OUT[70]
A_RES
F
Exercise
Clock
34
RSSD[70] OUT[70]
A_RES
F
DEC_68 signal synthesis
DEC(68h)D[70] DEC_68
D[70]
A_RES
CLK
OUT[70]
RSS
D[70] OUT[70]
A_RES
F
35
Modulo 256 adder
Full Adder 8 bit
D[70]
A_RES
374
D
A_RES
Q
Q
CLK
0
1
DEC_68
OE
1
OUT[70]
CIN
0
A[70]
B[70]
36
F signal synthesis
8 bit counter
A_RES
A_RES
EN
RES
CLKU2 U1 U0
DEC(5h)
F
DEC_68
F
Synchronous RESET
37
Exercise
A synchronous sequential network must monitor the data received on the 8 lines D[70] the data received are significant only if N=1 The networks must count modulo 256 how many data are divisible by 4 while EN=1 (excluding 0) The network has two more inputs THREE e RESET The signal THREE when asserted indicates that the value for increasing the count (if the data is divisible by 4) must be 3 (on the contrary if THREE is 0 the count must be increased by 1) The synchronous RESET signal overrides all other signals Direct design
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
38
SynchronousSequentialNetwork
EN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70] (Count)
An input data is divisible by 4 of its two Lsbits (I1 and I0) are zero
An 8 integrated bit register is used for the solution
CK
39
Signal DEC(0) is 1 if all input bits are 0
A signal DIV4 decodes whether the input data is divisible by 4 and NOT zero
DIV4 = I1I0DEC(0)
A signal STORE indicates that EN=1 and the input datum is divisible by 4
STORE = ENDIV4
I[70] DEC(0) DEC(0)
40
REG8BIT
ENSTORE + RESET
CK
FA8 bit
A[70]
B[70]
S[70]
CinCout
THREE
lsquo0rsquo
1
0
lsquo3rsquo
lsquo1rsquo
D[70] Z[70] U[70]
RESET
1
0
lsquo0rsquo
8 Mux21
The FA adds 1 or 3 according to signal THREE (provided the input datum is divisble by 4 and is not 0)
41
Exercise
Design a synchronous sequential network which according to two programming bits X1 and X0 generates the following four output sequences of two bits (signals U1 and U0) which end always with 11
10-01-01-10-11 if X1=0 e X0=010-01-10-01-10-10-11 if X1=0 e X0=100-10-00-11 if X1=1 e X0=001-10-10-10-10-11 if X1=1 e X0=1
The programming signals X1 and X0 are significant only when the output is 11 The network has an synchronous RESET Direct synthesis
RSSCK
X1
X0
U1
U0
42
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5rArr10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
The SSN uses a modulo N counter with N coded by the two input signals X1 e X0 (sampled when U1U0=11)
For the solution we can use a module 8 counter with synchronous RES and a combinatorial network with X1 and X0 as inputs Since the signals X1 and X0 are significant only when U1U0 = 1 they must be sampled (X1_C e X0_C) through two flip-flops when the SSN output is U1U0 = 11 The signals U1 and U0 are the decoding of the module 8 counter status according to X1_C and X0_C
The counter must be reset when U1U0 = 11
RSSCK
X1
X0
U1
U0
43
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X1_SX1
X1_S e X0_S synthesis
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X0_SX0
44
U1 and U0 truth table
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5 rArr (0 to 4hellip)
10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
X1_S and X0_S values
Cont | 00 01 11 10000 | 00110 00110 00100 00101001 | 01001 01001 01010 01010010 | 01101 01110 01100 01110011 | 01110 10001 00011 10010 100 | 00011 10110 ------ 10110101 | ------ 11010 ------ 00011 110 | ------ 00011 ------ ------111 | ------ ------ ------ ------
Status U1U0
Is this synthesis of the network safe
No beacuse the donrsquot cares could keep the network stable out of the main cycles
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
- Slide 59
- Slide 60
- Slide 61
- Slide 62
- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
Rotation
In the computers it is often necessary to implement a right or left rotation of a register content This is achieved by a feedback shift register
D0kQ0k
CK DnQn
CK
D0kQ0k
CK Dn-1Qn-1
CK
D0kQ0k
CK Dn-2Qn-2
CK
D0kQ0k
CK D0Q0
CK
Very often the direction must be programmable In this case the input of D0 (through a MUX 21) can be Q1 or Qnand so on
16
Shift register counters Shift register based counter through EX-OR feedback
Q2Q0
3 bit shift rightD
Q1
110 111 011 101 010 001
Disjoint state diagram
A n FF shift register with an EX-OR feedback (with variable inputs selected) is a NON binary counter for 2n-1 (provided it is not preset with all zeros)
000
100
17
Johnson Counter
000-gt100-gt110-gt111-gt011-gt001-gt000-gt
Disjoint state loop 101-gt010-gt101gt1
A Johnson counter with N FFs counts for 2N Since successive Johnson counter configurations differ by a single bit (adjacent configurations) it can be used for generating glitches-free waveforms
FFDD Q
QR
A_RESET
FFDD Q
QR
A_RESET
FFDD Q
QR
A_RESET
OUT2OUT1OUT0
CK
18
Single laquo1raquo ring counter (directly generating a 1 over n code)
FFDD Q
QR
RESET
FFDD Q
QR
RESET
FFDD Q
QPR
RESET
OUT3OUT1OUT0
CK
FFDD Q
QR
RESET
OUT2
0001-gt1000-gt0100-gt0010-gt0010
The ring counter needs N FFs in order to count for N (while with the binary counters the number of FF necessary for a N count is m= |log2N| that is the first integer greater or equal to log2N)
19
bull Synchronous networks exercises presented in the course are based on the state diagram but only for verification Synchronous network synthesis is made WITHOUT the state diagram usinghellip the brain only by decomposing the network in well know blocks (FFs combinatorial networks and ndash see later ndash counters shift registers etcetc)hellip
20
Design a synchronous logical network (SRL) able to detect palindrome 4 bit configurations (that is configurations that are identical when read left to right or viceversa) which are sequentially inserted in a shift register The D input is significant (and therefore valid for the sequence) only when the input Enable is 1 (whichs is not necessarilly the case for four consecutive input bits) The output P is 1 for a single period when a palindrome configuration is detected after a 4 bit sequence is received Then a new 4 bit sequence must be received (by E conditioned) and detected Direct synthesis
RSS
D
VP
D
VP
Exercise 4 synchronous
21
Enable E
To store a 4 bit sequence a Shift Register with Enable (CE) and Clear (CLR) is used A palindrome configuration is detected when the 1st bit is equal to the 4th bit and the 2nd bit is equal to the 3rd bit
22
A by 4 counter is used upon the 4th clock positive edge the network controls whether the configuration is palindrome The DFF after the decoding of 3 (that is when the counter becomes 0 anew) is used because the configuration control must be delayed un period The ENABLE signal is connected to both components (when 0 both the counter and the shift are disabled)
NB The first inserted bit is sampled when the counter is increased from 0 to 1
NB in this circuit Preset and Clear signals are not connected In Xilinx unconnected control signals are inactive
23
POST-ROUTE SIMULATION
Z output is delayed 10 ns from the clock positive edge because of the switch delay
24
Not valid inputEnable=0
Barrel shifter (rotor)A barrel shifter is a shift register able to shift ldquonrdquo positions in a single period its FFs contents A-H inputs are synchronously stored in the FFs when the LDST is activated When LDST is 0 upon each clock positive edge an anticlockwise n-positions rotation takes place where n is the binary value of S0 S1 and S2 signals For instance if rdquo01110000rdquo is rotated 4 positions at the first clock the content becomes ldquo00000111rdquo If then it is rotated 3 positions it becomes ldquo00111000rdquo
It must be noticed that the component is a register with laquonraquo 81 Muxs each one connected to the D inputs of the FFs The Mux control input value n is given by S0 S1 and S2
25
The circuit in figure is one of the eight 81 MUXs which select the values to be stored in the FFs
The last six right signals are the true and inverted selection signals (S1 S1 S2 S2 S3 e S3) for the 81 MUXs
Each 81 MUX is ORed with preset input value which is used together with LOAD (if LOAD=1 the OR preset value is 0) The FF output is ANDed with LOAD this zeroes all MUX outputs allowing the preset values to be stored in the FFs
The first left 8 signals are the values of the FF D inputs in the preceding period
Xilinx schematic
26
MUX
Preset value
27
Si -gt Mux 81 control signal of each FFAH -gt segnals for Preset Load
LDST=LOADWhen LDST signal is 0 all preset ANDs are zero If LDST is 1 the preset signals are enabled and all MUX outputs are zeroed
Preset AND
28
The LOAD (LDST) signal enables the preset inputs of the FFs (see the ANDs of the previous figure) and at the same time zeroes the output of the FFs (see the FFs cascaded ANDs) so as to select the preset value of the OR input
First 4 FFs Preset values
Xilinx schematicS2 S1 S0 selection signals
A B C HInput signals
LDST load signal
Clock
QA QB QC QH Outputs signals
29
Barrel Shifter
LDST=1upont the first clock positive edge the ldquo10010111rdquo value is loaded into the Barrel Shifter
The different values of Si (1 3 5) cause different device rotation Obviously with 8 sigle shifts the value becomes the initial value ldquo10010111rdquo again
A further active LDST loads a new valute into the the Barrel Shifter
This new value can be rotated again according to S signals
30
This is a typical example of how erroneous is not to laquobusraquo signals a-g qa-g and S0-2 It would have been possible to use a compact decomposable binary notation much easier to interpret where all single signals can be however displayed by laquoopeningraquo the bus
EPROM
X0nZ0m
y0kY0k
Clock
D0kQ0k
FFD0k
CK
D0kQ0kCK
EPROM based synchronous networks
Nowadays instead of the EPROMs PLAs (Programmable Logical Arrays) are used that is devices where the combinatorial functions are optimized (combinatorial functions implementations are not necessarily canonical) The basic principle is however the same
31
Design with Xilinx a synchronous logical network using 374 ALU 74181 a counter and other necessary devices which implements in sequence (after a START) signal the sum of two four bits absolute numbers (A and B) then 2rsquos complements the result then exchanges the two MSBits with the two LSBits and eventually divides arythmetically the result by 2
Example
A=1100 B=0101 =gt Sum 0001 Exchange =gt 0100 (410)2rsquos complement =gt 1100 (-410)Arithmetical division (right shift) by two =gt 1110 (-210)
The solution can be decomposed in three subsystems the control and decoding unit the datapath the input and output registersi
This is the basic architecture of the central unit of any computer
The only difference is that for the computers instead of a fixed sequence of elementary operations a new different sequence is generated for each instruction which must be executed
32
Exercise
33
The synchronous network of figure must add modulo 256 the 8 bit data received in parallel on lines D[70] The sum must be updated each clock and presented on the output lines OUT[70] In case the input data is 68H the sum must not be updated and the input data discarded In addition whenever 6 significant data have been received (that is excluding 68H) the output signal F must be set for one clock period during the reception of the sixth data A reset input is also available which zeroes the outputs and resets the data count Direct design
RSS
D[70] OUT[70]
A_RES
F
Exercise
Clock
34
RSSD[70] OUT[70]
A_RES
F
DEC_68 signal synthesis
DEC(68h)D[70] DEC_68
D[70]
A_RES
CLK
OUT[70]
RSS
D[70] OUT[70]
A_RES
F
35
Modulo 256 adder
Full Adder 8 bit
D[70]
A_RES
374
D
A_RES
Q
Q
CLK
0
1
DEC_68
OE
1
OUT[70]
CIN
0
A[70]
B[70]
36
F signal synthesis
8 bit counter
A_RES
A_RES
EN
RES
CLKU2 U1 U0
DEC(5h)
F
DEC_68
F
Synchronous RESET
37
Exercise
A synchronous sequential network must monitor the data received on the 8 lines D[70] the data received are significant only if N=1 The networks must count modulo 256 how many data are divisible by 4 while EN=1 (excluding 0) The network has two more inputs THREE e RESET The signal THREE when asserted indicates that the value for increasing the count (if the data is divisible by 4) must be 3 (on the contrary if THREE is 0 the count must be increased by 1) The synchronous RESET signal overrides all other signals Direct design
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
38
SynchronousSequentialNetwork
EN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70] (Count)
An input data is divisible by 4 of its two Lsbits (I1 and I0) are zero
An 8 integrated bit register is used for the solution
CK
39
Signal DEC(0) is 1 if all input bits are 0
A signal DIV4 decodes whether the input data is divisible by 4 and NOT zero
DIV4 = I1I0DEC(0)
A signal STORE indicates that EN=1 and the input datum is divisible by 4
STORE = ENDIV4
I[70] DEC(0) DEC(0)
40
REG8BIT
ENSTORE + RESET
CK
FA8 bit
A[70]
B[70]
S[70]
CinCout
THREE
lsquo0rsquo
1
0
lsquo3rsquo
lsquo1rsquo
D[70] Z[70] U[70]
RESET
1
0
lsquo0rsquo
8 Mux21
The FA adds 1 or 3 according to signal THREE (provided the input datum is divisble by 4 and is not 0)
41
Exercise
Design a synchronous sequential network which according to two programming bits X1 and X0 generates the following four output sequences of two bits (signals U1 and U0) which end always with 11
10-01-01-10-11 if X1=0 e X0=010-01-10-01-10-10-11 if X1=0 e X0=100-10-00-11 if X1=1 e X0=001-10-10-10-10-11 if X1=1 e X0=1
The programming signals X1 and X0 are significant only when the output is 11 The network has an synchronous RESET Direct synthesis
RSSCK
X1
X0
U1
U0
42
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5rArr10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
The SSN uses a modulo N counter with N coded by the two input signals X1 e X0 (sampled when U1U0=11)
For the solution we can use a module 8 counter with synchronous RES and a combinatorial network with X1 and X0 as inputs Since the signals X1 and X0 are significant only when U1U0 = 1 they must be sampled (X1_C e X0_C) through two flip-flops when the SSN output is U1U0 = 11 The signals U1 and U0 are the decoding of the module 8 counter status according to X1_C and X0_C
The counter must be reset when U1U0 = 11
RSSCK
X1
X0
U1
U0
43
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X1_SX1
X1_S e X0_S synthesis
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X0_SX0
44
U1 and U0 truth table
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5 rArr (0 to 4hellip)
10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
X1_S and X0_S values
Cont | 00 01 11 10000 | 00110 00110 00100 00101001 | 01001 01001 01010 01010010 | 01101 01110 01100 01110011 | 01110 10001 00011 10010 100 | 00011 10110 ------ 10110101 | ------ 11010 ------ 00011 110 | ------ 00011 ------ ------111 | ------ ------ ------ ------
Status U1U0
Is this synthesis of the network safe
No beacuse the donrsquot cares could keep the network stable out of the main cycles
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
- Slide 59
- Slide 60
- Slide 61
- Slide 62
- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
Shift register counters Shift register based counter through EX-OR feedback
Q2Q0
3 bit shift rightD
Q1
110 111 011 101 010 001
Disjoint state diagram
A n FF shift register with an EX-OR feedback (with variable inputs selected) is a NON binary counter for 2n-1 (provided it is not preset with all zeros)
000
100
17
Johnson Counter
000-gt100-gt110-gt111-gt011-gt001-gt000-gt
Disjoint state loop 101-gt010-gt101gt1
A Johnson counter with N FFs counts for 2N Since successive Johnson counter configurations differ by a single bit (adjacent configurations) it can be used for generating glitches-free waveforms
FFDD Q
QR
A_RESET
FFDD Q
QR
A_RESET
FFDD Q
QR
A_RESET
OUT2OUT1OUT0
CK
18
Single laquo1raquo ring counter (directly generating a 1 over n code)
FFDD Q
QR
RESET
FFDD Q
QR
RESET
FFDD Q
QPR
RESET
OUT3OUT1OUT0
CK
FFDD Q
QR
RESET
OUT2
0001-gt1000-gt0100-gt0010-gt0010
The ring counter needs N FFs in order to count for N (while with the binary counters the number of FF necessary for a N count is m= |log2N| that is the first integer greater or equal to log2N)
19
bull Synchronous networks exercises presented in the course are based on the state diagram but only for verification Synchronous network synthesis is made WITHOUT the state diagram usinghellip the brain only by decomposing the network in well know blocks (FFs combinatorial networks and ndash see later ndash counters shift registers etcetc)hellip
20
Design a synchronous logical network (SRL) able to detect palindrome 4 bit configurations (that is configurations that are identical when read left to right or viceversa) which are sequentially inserted in a shift register The D input is significant (and therefore valid for the sequence) only when the input Enable is 1 (whichs is not necessarilly the case for four consecutive input bits) The output P is 1 for a single period when a palindrome configuration is detected after a 4 bit sequence is received Then a new 4 bit sequence must be received (by E conditioned) and detected Direct synthesis
RSS
D
VP
D
VP
Exercise 4 synchronous
21
Enable E
To store a 4 bit sequence a Shift Register with Enable (CE) and Clear (CLR) is used A palindrome configuration is detected when the 1st bit is equal to the 4th bit and the 2nd bit is equal to the 3rd bit
22
A by 4 counter is used upon the 4th clock positive edge the network controls whether the configuration is palindrome The DFF after the decoding of 3 (that is when the counter becomes 0 anew) is used because the configuration control must be delayed un period The ENABLE signal is connected to both components (when 0 both the counter and the shift are disabled)
NB The first inserted bit is sampled when the counter is increased from 0 to 1
NB in this circuit Preset and Clear signals are not connected In Xilinx unconnected control signals are inactive
23
POST-ROUTE SIMULATION
Z output is delayed 10 ns from the clock positive edge because of the switch delay
24
Not valid inputEnable=0
Barrel shifter (rotor)A barrel shifter is a shift register able to shift ldquonrdquo positions in a single period its FFs contents A-H inputs are synchronously stored in the FFs when the LDST is activated When LDST is 0 upon each clock positive edge an anticlockwise n-positions rotation takes place where n is the binary value of S0 S1 and S2 signals For instance if rdquo01110000rdquo is rotated 4 positions at the first clock the content becomes ldquo00000111rdquo If then it is rotated 3 positions it becomes ldquo00111000rdquo
It must be noticed that the component is a register with laquonraquo 81 Muxs each one connected to the D inputs of the FFs The Mux control input value n is given by S0 S1 and S2
25
The circuit in figure is one of the eight 81 MUXs which select the values to be stored in the FFs
The last six right signals are the true and inverted selection signals (S1 S1 S2 S2 S3 e S3) for the 81 MUXs
Each 81 MUX is ORed with preset input value which is used together with LOAD (if LOAD=1 the OR preset value is 0) The FF output is ANDed with LOAD this zeroes all MUX outputs allowing the preset values to be stored in the FFs
The first left 8 signals are the values of the FF D inputs in the preceding period
Xilinx schematic
26
MUX
Preset value
27
Si -gt Mux 81 control signal of each FFAH -gt segnals for Preset Load
LDST=LOADWhen LDST signal is 0 all preset ANDs are zero If LDST is 1 the preset signals are enabled and all MUX outputs are zeroed
Preset AND
28
The LOAD (LDST) signal enables the preset inputs of the FFs (see the ANDs of the previous figure) and at the same time zeroes the output of the FFs (see the FFs cascaded ANDs) so as to select the preset value of the OR input
First 4 FFs Preset values
Xilinx schematicS2 S1 S0 selection signals
A B C HInput signals
LDST load signal
Clock
QA QB QC QH Outputs signals
29
Barrel Shifter
LDST=1upont the first clock positive edge the ldquo10010111rdquo value is loaded into the Barrel Shifter
The different values of Si (1 3 5) cause different device rotation Obviously with 8 sigle shifts the value becomes the initial value ldquo10010111rdquo again
A further active LDST loads a new valute into the the Barrel Shifter
This new value can be rotated again according to S signals
30
This is a typical example of how erroneous is not to laquobusraquo signals a-g qa-g and S0-2 It would have been possible to use a compact decomposable binary notation much easier to interpret where all single signals can be however displayed by laquoopeningraquo the bus
EPROM
X0nZ0m
y0kY0k
Clock
D0kQ0k
FFD0k
CK
D0kQ0kCK
EPROM based synchronous networks
Nowadays instead of the EPROMs PLAs (Programmable Logical Arrays) are used that is devices where the combinatorial functions are optimized (combinatorial functions implementations are not necessarily canonical) The basic principle is however the same
31
Design with Xilinx a synchronous logical network using 374 ALU 74181 a counter and other necessary devices which implements in sequence (after a START) signal the sum of two four bits absolute numbers (A and B) then 2rsquos complements the result then exchanges the two MSBits with the two LSBits and eventually divides arythmetically the result by 2
Example
A=1100 B=0101 =gt Sum 0001 Exchange =gt 0100 (410)2rsquos complement =gt 1100 (-410)Arithmetical division (right shift) by two =gt 1110 (-210)
The solution can be decomposed in three subsystems the control and decoding unit the datapath the input and output registersi
This is the basic architecture of the central unit of any computer
The only difference is that for the computers instead of a fixed sequence of elementary operations a new different sequence is generated for each instruction which must be executed
32
Exercise
33
The synchronous network of figure must add modulo 256 the 8 bit data received in parallel on lines D[70] The sum must be updated each clock and presented on the output lines OUT[70] In case the input data is 68H the sum must not be updated and the input data discarded In addition whenever 6 significant data have been received (that is excluding 68H) the output signal F must be set for one clock period during the reception of the sixth data A reset input is also available which zeroes the outputs and resets the data count Direct design
RSS
D[70] OUT[70]
A_RES
F
Exercise
Clock
34
RSSD[70] OUT[70]
A_RES
F
DEC_68 signal synthesis
DEC(68h)D[70] DEC_68
D[70]
A_RES
CLK
OUT[70]
RSS
D[70] OUT[70]
A_RES
F
35
Modulo 256 adder
Full Adder 8 bit
D[70]
A_RES
374
D
A_RES
Q
Q
CLK
0
1
DEC_68
OE
1
OUT[70]
CIN
0
A[70]
B[70]
36
F signal synthesis
8 bit counter
A_RES
A_RES
EN
RES
CLKU2 U1 U0
DEC(5h)
F
DEC_68
F
Synchronous RESET
37
Exercise
A synchronous sequential network must monitor the data received on the 8 lines D[70] the data received are significant only if N=1 The networks must count modulo 256 how many data are divisible by 4 while EN=1 (excluding 0) The network has two more inputs THREE e RESET The signal THREE when asserted indicates that the value for increasing the count (if the data is divisible by 4) must be 3 (on the contrary if THREE is 0 the count must be increased by 1) The synchronous RESET signal overrides all other signals Direct design
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
38
SynchronousSequentialNetwork
EN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70] (Count)
An input data is divisible by 4 of its two Lsbits (I1 and I0) are zero
An 8 integrated bit register is used for the solution
CK
39
Signal DEC(0) is 1 if all input bits are 0
A signal DIV4 decodes whether the input data is divisible by 4 and NOT zero
DIV4 = I1I0DEC(0)
A signal STORE indicates that EN=1 and the input datum is divisible by 4
STORE = ENDIV4
I[70] DEC(0) DEC(0)
40
REG8BIT
ENSTORE + RESET
CK
FA8 bit
A[70]
B[70]
S[70]
CinCout
THREE
lsquo0rsquo
1
0
lsquo3rsquo
lsquo1rsquo
D[70] Z[70] U[70]
RESET
1
0
lsquo0rsquo
8 Mux21
The FA adds 1 or 3 according to signal THREE (provided the input datum is divisble by 4 and is not 0)
41
Exercise
Design a synchronous sequential network which according to two programming bits X1 and X0 generates the following four output sequences of two bits (signals U1 and U0) which end always with 11
10-01-01-10-11 if X1=0 e X0=010-01-10-01-10-10-11 if X1=0 e X0=100-10-00-11 if X1=1 e X0=001-10-10-10-10-11 if X1=1 e X0=1
The programming signals X1 and X0 are significant only when the output is 11 The network has an synchronous RESET Direct synthesis
RSSCK
X1
X0
U1
U0
42
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5rArr10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
The SSN uses a modulo N counter with N coded by the two input signals X1 e X0 (sampled when U1U0=11)
For the solution we can use a module 8 counter with synchronous RES and a combinatorial network with X1 and X0 as inputs Since the signals X1 and X0 are significant only when U1U0 = 1 they must be sampled (X1_C e X0_C) through two flip-flops when the SSN output is U1U0 = 11 The signals U1 and U0 are the decoding of the module 8 counter status according to X1_C and X0_C
The counter must be reset when U1U0 = 11
RSSCK
X1
X0
U1
U0
43
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X1_SX1
X1_S e X0_S synthesis
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X0_SX0
44
U1 and U0 truth table
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5 rArr (0 to 4hellip)
10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
X1_S and X0_S values
Cont | 00 01 11 10000 | 00110 00110 00100 00101001 | 01001 01001 01010 01010010 | 01101 01110 01100 01110011 | 01110 10001 00011 10010 100 | 00011 10110 ------ 10110101 | ------ 11010 ------ 00011 110 | ------ 00011 ------ ------111 | ------ ------ ------ ------
Status U1U0
Is this synthesis of the network safe
No beacuse the donrsquot cares could keep the network stable out of the main cycles
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
- Slide 59
- Slide 60
- Slide 61
- Slide 62
- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
Johnson Counter
000-gt100-gt110-gt111-gt011-gt001-gt000-gt
Disjoint state loop 101-gt010-gt101gt1
A Johnson counter with N FFs counts for 2N Since successive Johnson counter configurations differ by a single bit (adjacent configurations) it can be used for generating glitches-free waveforms
FFDD Q
QR
A_RESET
FFDD Q
QR
A_RESET
FFDD Q
QR
A_RESET
OUT2OUT1OUT0
CK
18
Single laquo1raquo ring counter (directly generating a 1 over n code)
FFDD Q
QR
RESET
FFDD Q
QR
RESET
FFDD Q
QPR
RESET
OUT3OUT1OUT0
CK
FFDD Q
QR
RESET
OUT2
0001-gt1000-gt0100-gt0010-gt0010
The ring counter needs N FFs in order to count for N (while with the binary counters the number of FF necessary for a N count is m= |log2N| that is the first integer greater or equal to log2N)
19
bull Synchronous networks exercises presented in the course are based on the state diagram but only for verification Synchronous network synthesis is made WITHOUT the state diagram usinghellip the brain only by decomposing the network in well know blocks (FFs combinatorial networks and ndash see later ndash counters shift registers etcetc)hellip
20
Design a synchronous logical network (SRL) able to detect palindrome 4 bit configurations (that is configurations that are identical when read left to right or viceversa) which are sequentially inserted in a shift register The D input is significant (and therefore valid for the sequence) only when the input Enable is 1 (whichs is not necessarilly the case for four consecutive input bits) The output P is 1 for a single period when a palindrome configuration is detected after a 4 bit sequence is received Then a new 4 bit sequence must be received (by E conditioned) and detected Direct synthesis
RSS
D
VP
D
VP
Exercise 4 synchronous
21
Enable E
To store a 4 bit sequence a Shift Register with Enable (CE) and Clear (CLR) is used A palindrome configuration is detected when the 1st bit is equal to the 4th bit and the 2nd bit is equal to the 3rd bit
22
A by 4 counter is used upon the 4th clock positive edge the network controls whether the configuration is palindrome The DFF after the decoding of 3 (that is when the counter becomes 0 anew) is used because the configuration control must be delayed un period The ENABLE signal is connected to both components (when 0 both the counter and the shift are disabled)
NB The first inserted bit is sampled when the counter is increased from 0 to 1
NB in this circuit Preset and Clear signals are not connected In Xilinx unconnected control signals are inactive
23
POST-ROUTE SIMULATION
Z output is delayed 10 ns from the clock positive edge because of the switch delay
24
Not valid inputEnable=0
Barrel shifter (rotor)A barrel shifter is a shift register able to shift ldquonrdquo positions in a single period its FFs contents A-H inputs are synchronously stored in the FFs when the LDST is activated When LDST is 0 upon each clock positive edge an anticlockwise n-positions rotation takes place where n is the binary value of S0 S1 and S2 signals For instance if rdquo01110000rdquo is rotated 4 positions at the first clock the content becomes ldquo00000111rdquo If then it is rotated 3 positions it becomes ldquo00111000rdquo
It must be noticed that the component is a register with laquonraquo 81 Muxs each one connected to the D inputs of the FFs The Mux control input value n is given by S0 S1 and S2
25
The circuit in figure is one of the eight 81 MUXs which select the values to be stored in the FFs
The last six right signals are the true and inverted selection signals (S1 S1 S2 S2 S3 e S3) for the 81 MUXs
Each 81 MUX is ORed with preset input value which is used together with LOAD (if LOAD=1 the OR preset value is 0) The FF output is ANDed with LOAD this zeroes all MUX outputs allowing the preset values to be stored in the FFs
The first left 8 signals are the values of the FF D inputs in the preceding period
Xilinx schematic
26
MUX
Preset value
27
Si -gt Mux 81 control signal of each FFAH -gt segnals for Preset Load
LDST=LOADWhen LDST signal is 0 all preset ANDs are zero If LDST is 1 the preset signals are enabled and all MUX outputs are zeroed
Preset AND
28
The LOAD (LDST) signal enables the preset inputs of the FFs (see the ANDs of the previous figure) and at the same time zeroes the output of the FFs (see the FFs cascaded ANDs) so as to select the preset value of the OR input
First 4 FFs Preset values
Xilinx schematicS2 S1 S0 selection signals
A B C HInput signals
LDST load signal
Clock
QA QB QC QH Outputs signals
29
Barrel Shifter
LDST=1upont the first clock positive edge the ldquo10010111rdquo value is loaded into the Barrel Shifter
The different values of Si (1 3 5) cause different device rotation Obviously with 8 sigle shifts the value becomes the initial value ldquo10010111rdquo again
A further active LDST loads a new valute into the the Barrel Shifter
This new value can be rotated again according to S signals
30
This is a typical example of how erroneous is not to laquobusraquo signals a-g qa-g and S0-2 It would have been possible to use a compact decomposable binary notation much easier to interpret where all single signals can be however displayed by laquoopeningraquo the bus
EPROM
X0nZ0m
y0kY0k
Clock
D0kQ0k
FFD0k
CK
D0kQ0kCK
EPROM based synchronous networks
Nowadays instead of the EPROMs PLAs (Programmable Logical Arrays) are used that is devices where the combinatorial functions are optimized (combinatorial functions implementations are not necessarily canonical) The basic principle is however the same
31
Design with Xilinx a synchronous logical network using 374 ALU 74181 a counter and other necessary devices which implements in sequence (after a START) signal the sum of two four bits absolute numbers (A and B) then 2rsquos complements the result then exchanges the two MSBits with the two LSBits and eventually divides arythmetically the result by 2
Example
A=1100 B=0101 =gt Sum 0001 Exchange =gt 0100 (410)2rsquos complement =gt 1100 (-410)Arithmetical division (right shift) by two =gt 1110 (-210)
The solution can be decomposed in three subsystems the control and decoding unit the datapath the input and output registersi
This is the basic architecture of the central unit of any computer
The only difference is that for the computers instead of a fixed sequence of elementary operations a new different sequence is generated for each instruction which must be executed
32
Exercise
33
The synchronous network of figure must add modulo 256 the 8 bit data received in parallel on lines D[70] The sum must be updated each clock and presented on the output lines OUT[70] In case the input data is 68H the sum must not be updated and the input data discarded In addition whenever 6 significant data have been received (that is excluding 68H) the output signal F must be set for one clock period during the reception of the sixth data A reset input is also available which zeroes the outputs and resets the data count Direct design
RSS
D[70] OUT[70]
A_RES
F
Exercise
Clock
34
RSSD[70] OUT[70]
A_RES
F
DEC_68 signal synthesis
DEC(68h)D[70] DEC_68
D[70]
A_RES
CLK
OUT[70]
RSS
D[70] OUT[70]
A_RES
F
35
Modulo 256 adder
Full Adder 8 bit
D[70]
A_RES
374
D
A_RES
Q
Q
CLK
0
1
DEC_68
OE
1
OUT[70]
CIN
0
A[70]
B[70]
36
F signal synthesis
8 bit counter
A_RES
A_RES
EN
RES
CLKU2 U1 U0
DEC(5h)
F
DEC_68
F
Synchronous RESET
37
Exercise
A synchronous sequential network must monitor the data received on the 8 lines D[70] the data received are significant only if N=1 The networks must count modulo 256 how many data are divisible by 4 while EN=1 (excluding 0) The network has two more inputs THREE e RESET The signal THREE when asserted indicates that the value for increasing the count (if the data is divisible by 4) must be 3 (on the contrary if THREE is 0 the count must be increased by 1) The synchronous RESET signal overrides all other signals Direct design
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
38
SynchronousSequentialNetwork
EN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70] (Count)
An input data is divisible by 4 of its two Lsbits (I1 and I0) are zero
An 8 integrated bit register is used for the solution
CK
39
Signal DEC(0) is 1 if all input bits are 0
A signal DIV4 decodes whether the input data is divisible by 4 and NOT zero
DIV4 = I1I0DEC(0)
A signal STORE indicates that EN=1 and the input datum is divisible by 4
STORE = ENDIV4
I[70] DEC(0) DEC(0)
40
REG8BIT
ENSTORE + RESET
CK
FA8 bit
A[70]
B[70]
S[70]
CinCout
THREE
lsquo0rsquo
1
0
lsquo3rsquo
lsquo1rsquo
D[70] Z[70] U[70]
RESET
1
0
lsquo0rsquo
8 Mux21
The FA adds 1 or 3 according to signal THREE (provided the input datum is divisble by 4 and is not 0)
41
Exercise
Design a synchronous sequential network which according to two programming bits X1 and X0 generates the following four output sequences of two bits (signals U1 and U0) which end always with 11
10-01-01-10-11 if X1=0 e X0=010-01-10-01-10-10-11 if X1=0 e X0=100-10-00-11 if X1=1 e X0=001-10-10-10-10-11 if X1=1 e X0=1
The programming signals X1 and X0 are significant only when the output is 11 The network has an synchronous RESET Direct synthesis
RSSCK
X1
X0
U1
U0
42
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5rArr10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
The SSN uses a modulo N counter with N coded by the two input signals X1 e X0 (sampled when U1U0=11)
For the solution we can use a module 8 counter with synchronous RES and a combinatorial network with X1 and X0 as inputs Since the signals X1 and X0 are significant only when U1U0 = 1 they must be sampled (X1_C e X0_C) through two flip-flops when the SSN output is U1U0 = 11 The signals U1 and U0 are the decoding of the module 8 counter status according to X1_C and X0_C
The counter must be reset when U1U0 = 11
RSSCK
X1
X0
U1
U0
43
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X1_SX1
X1_S e X0_S synthesis
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X0_SX0
44
U1 and U0 truth table
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5 rArr (0 to 4hellip)
10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
X1_S and X0_S values
Cont | 00 01 11 10000 | 00110 00110 00100 00101001 | 01001 01001 01010 01010010 | 01101 01110 01100 01110011 | 01110 10001 00011 10010 100 | 00011 10110 ------ 10110101 | ------ 11010 ------ 00011 110 | ------ 00011 ------ ------111 | ------ ------ ------ ------
Status U1U0
Is this synthesis of the network safe
No beacuse the donrsquot cares could keep the network stable out of the main cycles
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
- Slide 59
- Slide 60
- Slide 61
- Slide 62
- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
Single laquo1raquo ring counter (directly generating a 1 over n code)
FFDD Q
QR
RESET
FFDD Q
QR
RESET
FFDD Q
QPR
RESET
OUT3OUT1OUT0
CK
FFDD Q
QR
RESET
OUT2
0001-gt1000-gt0100-gt0010-gt0010
The ring counter needs N FFs in order to count for N (while with the binary counters the number of FF necessary for a N count is m= |log2N| that is the first integer greater or equal to log2N)
19
bull Synchronous networks exercises presented in the course are based on the state diagram but only for verification Synchronous network synthesis is made WITHOUT the state diagram usinghellip the brain only by decomposing the network in well know blocks (FFs combinatorial networks and ndash see later ndash counters shift registers etcetc)hellip
20
Design a synchronous logical network (SRL) able to detect palindrome 4 bit configurations (that is configurations that are identical when read left to right or viceversa) which are sequentially inserted in a shift register The D input is significant (and therefore valid for the sequence) only when the input Enable is 1 (whichs is not necessarilly the case for four consecutive input bits) The output P is 1 for a single period when a palindrome configuration is detected after a 4 bit sequence is received Then a new 4 bit sequence must be received (by E conditioned) and detected Direct synthesis
RSS
D
VP
D
VP
Exercise 4 synchronous
21
Enable E
To store a 4 bit sequence a Shift Register with Enable (CE) and Clear (CLR) is used A palindrome configuration is detected when the 1st bit is equal to the 4th bit and the 2nd bit is equal to the 3rd bit
22
A by 4 counter is used upon the 4th clock positive edge the network controls whether the configuration is palindrome The DFF after the decoding of 3 (that is when the counter becomes 0 anew) is used because the configuration control must be delayed un period The ENABLE signal is connected to both components (when 0 both the counter and the shift are disabled)
NB The first inserted bit is sampled when the counter is increased from 0 to 1
NB in this circuit Preset and Clear signals are not connected In Xilinx unconnected control signals are inactive
23
POST-ROUTE SIMULATION
Z output is delayed 10 ns from the clock positive edge because of the switch delay
24
Not valid inputEnable=0
Barrel shifter (rotor)A barrel shifter is a shift register able to shift ldquonrdquo positions in a single period its FFs contents A-H inputs are synchronously stored in the FFs when the LDST is activated When LDST is 0 upon each clock positive edge an anticlockwise n-positions rotation takes place where n is the binary value of S0 S1 and S2 signals For instance if rdquo01110000rdquo is rotated 4 positions at the first clock the content becomes ldquo00000111rdquo If then it is rotated 3 positions it becomes ldquo00111000rdquo
It must be noticed that the component is a register with laquonraquo 81 Muxs each one connected to the D inputs of the FFs The Mux control input value n is given by S0 S1 and S2
25
The circuit in figure is one of the eight 81 MUXs which select the values to be stored in the FFs
The last six right signals are the true and inverted selection signals (S1 S1 S2 S2 S3 e S3) for the 81 MUXs
Each 81 MUX is ORed with preset input value which is used together with LOAD (if LOAD=1 the OR preset value is 0) The FF output is ANDed with LOAD this zeroes all MUX outputs allowing the preset values to be stored in the FFs
The first left 8 signals are the values of the FF D inputs in the preceding period
Xilinx schematic
26
MUX
Preset value
27
Si -gt Mux 81 control signal of each FFAH -gt segnals for Preset Load
LDST=LOADWhen LDST signal is 0 all preset ANDs are zero If LDST is 1 the preset signals are enabled and all MUX outputs are zeroed
Preset AND
28
The LOAD (LDST) signal enables the preset inputs of the FFs (see the ANDs of the previous figure) and at the same time zeroes the output of the FFs (see the FFs cascaded ANDs) so as to select the preset value of the OR input
First 4 FFs Preset values
Xilinx schematicS2 S1 S0 selection signals
A B C HInput signals
LDST load signal
Clock
QA QB QC QH Outputs signals
29
Barrel Shifter
LDST=1upont the first clock positive edge the ldquo10010111rdquo value is loaded into the Barrel Shifter
The different values of Si (1 3 5) cause different device rotation Obviously with 8 sigle shifts the value becomes the initial value ldquo10010111rdquo again
A further active LDST loads a new valute into the the Barrel Shifter
This new value can be rotated again according to S signals
30
This is a typical example of how erroneous is not to laquobusraquo signals a-g qa-g and S0-2 It would have been possible to use a compact decomposable binary notation much easier to interpret where all single signals can be however displayed by laquoopeningraquo the bus
EPROM
X0nZ0m
y0kY0k
Clock
D0kQ0k
FFD0k
CK
D0kQ0kCK
EPROM based synchronous networks
Nowadays instead of the EPROMs PLAs (Programmable Logical Arrays) are used that is devices where the combinatorial functions are optimized (combinatorial functions implementations are not necessarily canonical) The basic principle is however the same
31
Design with Xilinx a synchronous logical network using 374 ALU 74181 a counter and other necessary devices which implements in sequence (after a START) signal the sum of two four bits absolute numbers (A and B) then 2rsquos complements the result then exchanges the two MSBits with the two LSBits and eventually divides arythmetically the result by 2
Example
A=1100 B=0101 =gt Sum 0001 Exchange =gt 0100 (410)2rsquos complement =gt 1100 (-410)Arithmetical division (right shift) by two =gt 1110 (-210)
The solution can be decomposed in three subsystems the control and decoding unit the datapath the input and output registersi
This is the basic architecture of the central unit of any computer
The only difference is that for the computers instead of a fixed sequence of elementary operations a new different sequence is generated for each instruction which must be executed
32
Exercise
33
The synchronous network of figure must add modulo 256 the 8 bit data received in parallel on lines D[70] The sum must be updated each clock and presented on the output lines OUT[70] In case the input data is 68H the sum must not be updated and the input data discarded In addition whenever 6 significant data have been received (that is excluding 68H) the output signal F must be set for one clock period during the reception of the sixth data A reset input is also available which zeroes the outputs and resets the data count Direct design
RSS
D[70] OUT[70]
A_RES
F
Exercise
Clock
34
RSSD[70] OUT[70]
A_RES
F
DEC_68 signal synthesis
DEC(68h)D[70] DEC_68
D[70]
A_RES
CLK
OUT[70]
RSS
D[70] OUT[70]
A_RES
F
35
Modulo 256 adder
Full Adder 8 bit
D[70]
A_RES
374
D
A_RES
Q
Q
CLK
0
1
DEC_68
OE
1
OUT[70]
CIN
0
A[70]
B[70]
36
F signal synthesis
8 bit counter
A_RES
A_RES
EN
RES
CLKU2 U1 U0
DEC(5h)
F
DEC_68
F
Synchronous RESET
37
Exercise
A synchronous sequential network must monitor the data received on the 8 lines D[70] the data received are significant only if N=1 The networks must count modulo 256 how many data are divisible by 4 while EN=1 (excluding 0) The network has two more inputs THREE e RESET The signal THREE when asserted indicates that the value for increasing the count (if the data is divisible by 4) must be 3 (on the contrary if THREE is 0 the count must be increased by 1) The synchronous RESET signal overrides all other signals Direct design
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
38
SynchronousSequentialNetwork
EN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70] (Count)
An input data is divisible by 4 of its two Lsbits (I1 and I0) are zero
An 8 integrated bit register is used for the solution
CK
39
Signal DEC(0) is 1 if all input bits are 0
A signal DIV4 decodes whether the input data is divisible by 4 and NOT zero
DIV4 = I1I0DEC(0)
A signal STORE indicates that EN=1 and the input datum is divisible by 4
STORE = ENDIV4
I[70] DEC(0) DEC(0)
40
REG8BIT
ENSTORE + RESET
CK
FA8 bit
A[70]
B[70]
S[70]
CinCout
THREE
lsquo0rsquo
1
0
lsquo3rsquo
lsquo1rsquo
D[70] Z[70] U[70]
RESET
1
0
lsquo0rsquo
8 Mux21
The FA adds 1 or 3 according to signal THREE (provided the input datum is divisble by 4 and is not 0)
41
Exercise
Design a synchronous sequential network which according to two programming bits X1 and X0 generates the following four output sequences of two bits (signals U1 and U0) which end always with 11
10-01-01-10-11 if X1=0 e X0=010-01-10-01-10-10-11 if X1=0 e X0=100-10-00-11 if X1=1 e X0=001-10-10-10-10-11 if X1=1 e X0=1
The programming signals X1 and X0 are significant only when the output is 11 The network has an synchronous RESET Direct synthesis
RSSCK
X1
X0
U1
U0
42
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5rArr10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
The SSN uses a modulo N counter with N coded by the two input signals X1 e X0 (sampled when U1U0=11)
For the solution we can use a module 8 counter with synchronous RES and a combinatorial network with X1 and X0 as inputs Since the signals X1 and X0 are significant only when U1U0 = 1 they must be sampled (X1_C e X0_C) through two flip-flops when the SSN output is U1U0 = 11 The signals U1 and U0 are the decoding of the module 8 counter status according to X1_C and X0_C
The counter must be reset when U1U0 = 11
RSSCK
X1
X0
U1
U0
43
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X1_SX1
X1_S e X0_S synthesis
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X0_SX0
44
U1 and U0 truth table
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5 rArr (0 to 4hellip)
10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
X1_S and X0_S values
Cont | 00 01 11 10000 | 00110 00110 00100 00101001 | 01001 01001 01010 01010010 | 01101 01110 01100 01110011 | 01110 10001 00011 10010 100 | 00011 10110 ------ 10110101 | ------ 11010 ------ 00011 110 | ------ 00011 ------ ------111 | ------ ------ ------ ------
Status U1U0
Is this synthesis of the network safe
No beacuse the donrsquot cares could keep the network stable out of the main cycles
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
- Slide 59
- Slide 60
- Slide 61
- Slide 62
- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
bull Synchronous networks exercises presented in the course are based on the state diagram but only for verification Synchronous network synthesis is made WITHOUT the state diagram usinghellip the brain only by decomposing the network in well know blocks (FFs combinatorial networks and ndash see later ndash counters shift registers etcetc)hellip
20
Design a synchronous logical network (SRL) able to detect palindrome 4 bit configurations (that is configurations that are identical when read left to right or viceversa) which are sequentially inserted in a shift register The D input is significant (and therefore valid for the sequence) only when the input Enable is 1 (whichs is not necessarilly the case for four consecutive input bits) The output P is 1 for a single period when a palindrome configuration is detected after a 4 bit sequence is received Then a new 4 bit sequence must be received (by E conditioned) and detected Direct synthesis
RSS
D
VP
D
VP
Exercise 4 synchronous
21
Enable E
To store a 4 bit sequence a Shift Register with Enable (CE) and Clear (CLR) is used A palindrome configuration is detected when the 1st bit is equal to the 4th bit and the 2nd bit is equal to the 3rd bit
22
A by 4 counter is used upon the 4th clock positive edge the network controls whether the configuration is palindrome The DFF after the decoding of 3 (that is when the counter becomes 0 anew) is used because the configuration control must be delayed un period The ENABLE signal is connected to both components (when 0 both the counter and the shift are disabled)
NB The first inserted bit is sampled when the counter is increased from 0 to 1
NB in this circuit Preset and Clear signals are not connected In Xilinx unconnected control signals are inactive
23
POST-ROUTE SIMULATION
Z output is delayed 10 ns from the clock positive edge because of the switch delay
24
Not valid inputEnable=0
Barrel shifter (rotor)A barrel shifter is a shift register able to shift ldquonrdquo positions in a single period its FFs contents A-H inputs are synchronously stored in the FFs when the LDST is activated When LDST is 0 upon each clock positive edge an anticlockwise n-positions rotation takes place where n is the binary value of S0 S1 and S2 signals For instance if rdquo01110000rdquo is rotated 4 positions at the first clock the content becomes ldquo00000111rdquo If then it is rotated 3 positions it becomes ldquo00111000rdquo
It must be noticed that the component is a register with laquonraquo 81 Muxs each one connected to the D inputs of the FFs The Mux control input value n is given by S0 S1 and S2
25
The circuit in figure is one of the eight 81 MUXs which select the values to be stored in the FFs
The last six right signals are the true and inverted selection signals (S1 S1 S2 S2 S3 e S3) for the 81 MUXs
Each 81 MUX is ORed with preset input value which is used together with LOAD (if LOAD=1 the OR preset value is 0) The FF output is ANDed with LOAD this zeroes all MUX outputs allowing the preset values to be stored in the FFs
The first left 8 signals are the values of the FF D inputs in the preceding period
Xilinx schematic
26
MUX
Preset value
27
Si -gt Mux 81 control signal of each FFAH -gt segnals for Preset Load
LDST=LOADWhen LDST signal is 0 all preset ANDs are zero If LDST is 1 the preset signals are enabled and all MUX outputs are zeroed
Preset AND
28
The LOAD (LDST) signal enables the preset inputs of the FFs (see the ANDs of the previous figure) and at the same time zeroes the output of the FFs (see the FFs cascaded ANDs) so as to select the preset value of the OR input
First 4 FFs Preset values
Xilinx schematicS2 S1 S0 selection signals
A B C HInput signals
LDST load signal
Clock
QA QB QC QH Outputs signals
29
Barrel Shifter
LDST=1upont the first clock positive edge the ldquo10010111rdquo value is loaded into the Barrel Shifter
The different values of Si (1 3 5) cause different device rotation Obviously with 8 sigle shifts the value becomes the initial value ldquo10010111rdquo again
A further active LDST loads a new valute into the the Barrel Shifter
This new value can be rotated again according to S signals
30
This is a typical example of how erroneous is not to laquobusraquo signals a-g qa-g and S0-2 It would have been possible to use a compact decomposable binary notation much easier to interpret where all single signals can be however displayed by laquoopeningraquo the bus
EPROM
X0nZ0m
y0kY0k
Clock
D0kQ0k
FFD0k
CK
D0kQ0kCK
EPROM based synchronous networks
Nowadays instead of the EPROMs PLAs (Programmable Logical Arrays) are used that is devices where the combinatorial functions are optimized (combinatorial functions implementations are not necessarily canonical) The basic principle is however the same
31
Design with Xilinx a synchronous logical network using 374 ALU 74181 a counter and other necessary devices which implements in sequence (after a START) signal the sum of two four bits absolute numbers (A and B) then 2rsquos complements the result then exchanges the two MSBits with the two LSBits and eventually divides arythmetically the result by 2
Example
A=1100 B=0101 =gt Sum 0001 Exchange =gt 0100 (410)2rsquos complement =gt 1100 (-410)Arithmetical division (right shift) by two =gt 1110 (-210)
The solution can be decomposed in three subsystems the control and decoding unit the datapath the input and output registersi
This is the basic architecture of the central unit of any computer
The only difference is that for the computers instead of a fixed sequence of elementary operations a new different sequence is generated for each instruction which must be executed
32
Exercise
33
The synchronous network of figure must add modulo 256 the 8 bit data received in parallel on lines D[70] The sum must be updated each clock and presented on the output lines OUT[70] In case the input data is 68H the sum must not be updated and the input data discarded In addition whenever 6 significant data have been received (that is excluding 68H) the output signal F must be set for one clock period during the reception of the sixth data A reset input is also available which zeroes the outputs and resets the data count Direct design
RSS
D[70] OUT[70]
A_RES
F
Exercise
Clock
34
RSSD[70] OUT[70]
A_RES
F
DEC_68 signal synthesis
DEC(68h)D[70] DEC_68
D[70]
A_RES
CLK
OUT[70]
RSS
D[70] OUT[70]
A_RES
F
35
Modulo 256 adder
Full Adder 8 bit
D[70]
A_RES
374
D
A_RES
Q
Q
CLK
0
1
DEC_68
OE
1
OUT[70]
CIN
0
A[70]
B[70]
36
F signal synthesis
8 bit counter
A_RES
A_RES
EN
RES
CLKU2 U1 U0
DEC(5h)
F
DEC_68
F
Synchronous RESET
37
Exercise
A synchronous sequential network must monitor the data received on the 8 lines D[70] the data received are significant only if N=1 The networks must count modulo 256 how many data are divisible by 4 while EN=1 (excluding 0) The network has two more inputs THREE e RESET The signal THREE when asserted indicates that the value for increasing the count (if the data is divisible by 4) must be 3 (on the contrary if THREE is 0 the count must be increased by 1) The synchronous RESET signal overrides all other signals Direct design
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
38
SynchronousSequentialNetwork
EN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70] (Count)
An input data is divisible by 4 of its two Lsbits (I1 and I0) are zero
An 8 integrated bit register is used for the solution
CK
39
Signal DEC(0) is 1 if all input bits are 0
A signal DIV4 decodes whether the input data is divisible by 4 and NOT zero
DIV4 = I1I0DEC(0)
A signal STORE indicates that EN=1 and the input datum is divisible by 4
STORE = ENDIV4
I[70] DEC(0) DEC(0)
40
REG8BIT
ENSTORE + RESET
CK
FA8 bit
A[70]
B[70]
S[70]
CinCout
THREE
lsquo0rsquo
1
0
lsquo3rsquo
lsquo1rsquo
D[70] Z[70] U[70]
RESET
1
0
lsquo0rsquo
8 Mux21
The FA adds 1 or 3 according to signal THREE (provided the input datum is divisble by 4 and is not 0)
41
Exercise
Design a synchronous sequential network which according to two programming bits X1 and X0 generates the following four output sequences of two bits (signals U1 and U0) which end always with 11
10-01-01-10-11 if X1=0 e X0=010-01-10-01-10-10-11 if X1=0 e X0=100-10-00-11 if X1=1 e X0=001-10-10-10-10-11 if X1=1 e X0=1
The programming signals X1 and X0 are significant only when the output is 11 The network has an synchronous RESET Direct synthesis
RSSCK
X1
X0
U1
U0
42
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5rArr10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
The SSN uses a modulo N counter with N coded by the two input signals X1 e X0 (sampled when U1U0=11)
For the solution we can use a module 8 counter with synchronous RES and a combinatorial network with X1 and X0 as inputs Since the signals X1 and X0 are significant only when U1U0 = 1 they must be sampled (X1_C e X0_C) through two flip-flops when the SSN output is U1U0 = 11 The signals U1 and U0 are the decoding of the module 8 counter status according to X1_C and X0_C
The counter must be reset when U1U0 = 11
RSSCK
X1
X0
U1
U0
43
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X1_SX1
X1_S e X0_S synthesis
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X0_SX0
44
U1 and U0 truth table
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5 rArr (0 to 4hellip)
10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
X1_S and X0_S values
Cont | 00 01 11 10000 | 00110 00110 00100 00101001 | 01001 01001 01010 01010010 | 01101 01110 01100 01110011 | 01110 10001 00011 10010 100 | 00011 10110 ------ 10110101 | ------ 11010 ------ 00011 110 | ------ 00011 ------ ------111 | ------ ------ ------ ------
Status U1U0
Is this synthesis of the network safe
No beacuse the donrsquot cares could keep the network stable out of the main cycles
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
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- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
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- Slide 44
- Slide 45
- Slide 46
- Slide 47
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- Slide 49
- Slide 50
- Slide 51
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- Slide 53
- Slide 54
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- Slide 68
- Slide 69
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- Slide 71
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- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
Design a synchronous logical network (SRL) able to detect palindrome 4 bit configurations (that is configurations that are identical when read left to right or viceversa) which are sequentially inserted in a shift register The D input is significant (and therefore valid for the sequence) only when the input Enable is 1 (whichs is not necessarilly the case for four consecutive input bits) The output P is 1 for a single period when a palindrome configuration is detected after a 4 bit sequence is received Then a new 4 bit sequence must be received (by E conditioned) and detected Direct synthesis
RSS
D
VP
D
VP
Exercise 4 synchronous
21
Enable E
To store a 4 bit sequence a Shift Register with Enable (CE) and Clear (CLR) is used A palindrome configuration is detected when the 1st bit is equal to the 4th bit and the 2nd bit is equal to the 3rd bit
22
A by 4 counter is used upon the 4th clock positive edge the network controls whether the configuration is palindrome The DFF after the decoding of 3 (that is when the counter becomes 0 anew) is used because the configuration control must be delayed un period The ENABLE signal is connected to both components (when 0 both the counter and the shift are disabled)
NB The first inserted bit is sampled when the counter is increased from 0 to 1
NB in this circuit Preset and Clear signals are not connected In Xilinx unconnected control signals are inactive
23
POST-ROUTE SIMULATION
Z output is delayed 10 ns from the clock positive edge because of the switch delay
24
Not valid inputEnable=0
Barrel shifter (rotor)A barrel shifter is a shift register able to shift ldquonrdquo positions in a single period its FFs contents A-H inputs are synchronously stored in the FFs when the LDST is activated When LDST is 0 upon each clock positive edge an anticlockwise n-positions rotation takes place where n is the binary value of S0 S1 and S2 signals For instance if rdquo01110000rdquo is rotated 4 positions at the first clock the content becomes ldquo00000111rdquo If then it is rotated 3 positions it becomes ldquo00111000rdquo
It must be noticed that the component is a register with laquonraquo 81 Muxs each one connected to the D inputs of the FFs The Mux control input value n is given by S0 S1 and S2
25
The circuit in figure is one of the eight 81 MUXs which select the values to be stored in the FFs
The last six right signals are the true and inverted selection signals (S1 S1 S2 S2 S3 e S3) for the 81 MUXs
Each 81 MUX is ORed with preset input value which is used together with LOAD (if LOAD=1 the OR preset value is 0) The FF output is ANDed with LOAD this zeroes all MUX outputs allowing the preset values to be stored in the FFs
The first left 8 signals are the values of the FF D inputs in the preceding period
Xilinx schematic
26
MUX
Preset value
27
Si -gt Mux 81 control signal of each FFAH -gt segnals for Preset Load
LDST=LOADWhen LDST signal is 0 all preset ANDs are zero If LDST is 1 the preset signals are enabled and all MUX outputs are zeroed
Preset AND
28
The LOAD (LDST) signal enables the preset inputs of the FFs (see the ANDs of the previous figure) and at the same time zeroes the output of the FFs (see the FFs cascaded ANDs) so as to select the preset value of the OR input
First 4 FFs Preset values
Xilinx schematicS2 S1 S0 selection signals
A B C HInput signals
LDST load signal
Clock
QA QB QC QH Outputs signals
29
Barrel Shifter
LDST=1upont the first clock positive edge the ldquo10010111rdquo value is loaded into the Barrel Shifter
The different values of Si (1 3 5) cause different device rotation Obviously with 8 sigle shifts the value becomes the initial value ldquo10010111rdquo again
A further active LDST loads a new valute into the the Barrel Shifter
This new value can be rotated again according to S signals
30
This is a typical example of how erroneous is not to laquobusraquo signals a-g qa-g and S0-2 It would have been possible to use a compact decomposable binary notation much easier to interpret where all single signals can be however displayed by laquoopeningraquo the bus
EPROM
X0nZ0m
y0kY0k
Clock
D0kQ0k
FFD0k
CK
D0kQ0kCK
EPROM based synchronous networks
Nowadays instead of the EPROMs PLAs (Programmable Logical Arrays) are used that is devices where the combinatorial functions are optimized (combinatorial functions implementations are not necessarily canonical) The basic principle is however the same
31
Design with Xilinx a synchronous logical network using 374 ALU 74181 a counter and other necessary devices which implements in sequence (after a START) signal the sum of two four bits absolute numbers (A and B) then 2rsquos complements the result then exchanges the two MSBits with the two LSBits and eventually divides arythmetically the result by 2
Example
A=1100 B=0101 =gt Sum 0001 Exchange =gt 0100 (410)2rsquos complement =gt 1100 (-410)Arithmetical division (right shift) by two =gt 1110 (-210)
The solution can be decomposed in three subsystems the control and decoding unit the datapath the input and output registersi
This is the basic architecture of the central unit of any computer
The only difference is that for the computers instead of a fixed sequence of elementary operations a new different sequence is generated for each instruction which must be executed
32
Exercise
33
The synchronous network of figure must add modulo 256 the 8 bit data received in parallel on lines D[70] The sum must be updated each clock and presented on the output lines OUT[70] In case the input data is 68H the sum must not be updated and the input data discarded In addition whenever 6 significant data have been received (that is excluding 68H) the output signal F must be set for one clock period during the reception of the sixth data A reset input is also available which zeroes the outputs and resets the data count Direct design
RSS
D[70] OUT[70]
A_RES
F
Exercise
Clock
34
RSSD[70] OUT[70]
A_RES
F
DEC_68 signal synthesis
DEC(68h)D[70] DEC_68
D[70]
A_RES
CLK
OUT[70]
RSS
D[70] OUT[70]
A_RES
F
35
Modulo 256 adder
Full Adder 8 bit
D[70]
A_RES
374
D
A_RES
Q
Q
CLK
0
1
DEC_68
OE
1
OUT[70]
CIN
0
A[70]
B[70]
36
F signal synthesis
8 bit counter
A_RES
A_RES
EN
RES
CLKU2 U1 U0
DEC(5h)
F
DEC_68
F
Synchronous RESET
37
Exercise
A synchronous sequential network must monitor the data received on the 8 lines D[70] the data received are significant only if N=1 The networks must count modulo 256 how many data are divisible by 4 while EN=1 (excluding 0) The network has two more inputs THREE e RESET The signal THREE when asserted indicates that the value for increasing the count (if the data is divisible by 4) must be 3 (on the contrary if THREE is 0 the count must be increased by 1) The synchronous RESET signal overrides all other signals Direct design
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
38
SynchronousSequentialNetwork
EN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70] (Count)
An input data is divisible by 4 of its two Lsbits (I1 and I0) are zero
An 8 integrated bit register is used for the solution
CK
39
Signal DEC(0) is 1 if all input bits are 0
A signal DIV4 decodes whether the input data is divisible by 4 and NOT zero
DIV4 = I1I0DEC(0)
A signal STORE indicates that EN=1 and the input datum is divisible by 4
STORE = ENDIV4
I[70] DEC(0) DEC(0)
40
REG8BIT
ENSTORE + RESET
CK
FA8 bit
A[70]
B[70]
S[70]
CinCout
THREE
lsquo0rsquo
1
0
lsquo3rsquo
lsquo1rsquo
D[70] Z[70] U[70]
RESET
1
0
lsquo0rsquo
8 Mux21
The FA adds 1 or 3 according to signal THREE (provided the input datum is divisble by 4 and is not 0)
41
Exercise
Design a synchronous sequential network which according to two programming bits X1 and X0 generates the following four output sequences of two bits (signals U1 and U0) which end always with 11
10-01-01-10-11 if X1=0 e X0=010-01-10-01-10-10-11 if X1=0 e X0=100-10-00-11 if X1=1 e X0=001-10-10-10-10-11 if X1=1 e X0=1
The programming signals X1 and X0 are significant only when the output is 11 The network has an synchronous RESET Direct synthesis
RSSCK
X1
X0
U1
U0
42
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5rArr10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
The SSN uses a modulo N counter with N coded by the two input signals X1 e X0 (sampled when U1U0=11)
For the solution we can use a module 8 counter with synchronous RES and a combinatorial network with X1 and X0 as inputs Since the signals X1 and X0 are significant only when U1U0 = 1 they must be sampled (X1_C e X0_C) through two flip-flops when the SSN output is U1U0 = 11 The signals U1 and U0 are the decoding of the module 8 counter status according to X1_C and X0_C
The counter must be reset when U1U0 = 11
RSSCK
X1
X0
U1
U0
43
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X1_SX1
X1_S e X0_S synthesis
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X0_SX0
44
U1 and U0 truth table
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5 rArr (0 to 4hellip)
10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
X1_S and X0_S values
Cont | 00 01 11 10000 | 00110 00110 00100 00101001 | 01001 01001 01010 01010010 | 01101 01110 01100 01110011 | 01110 10001 00011 10010 100 | 00011 10110 ------ 10110101 | ------ 11010 ------ 00011 110 | ------ 00011 ------ ------111 | ------ ------ ------ ------
Status U1U0
Is this synthesis of the network safe
No beacuse the donrsquot cares could keep the network stable out of the main cycles
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
- Slide 59
- Slide 60
- Slide 61
- Slide 62
- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
To store a 4 bit sequence a Shift Register with Enable (CE) and Clear (CLR) is used A palindrome configuration is detected when the 1st bit is equal to the 4th bit and the 2nd bit is equal to the 3rd bit
22
A by 4 counter is used upon the 4th clock positive edge the network controls whether the configuration is palindrome The DFF after the decoding of 3 (that is when the counter becomes 0 anew) is used because the configuration control must be delayed un period The ENABLE signal is connected to both components (when 0 both the counter and the shift are disabled)
NB The first inserted bit is sampled when the counter is increased from 0 to 1
NB in this circuit Preset and Clear signals are not connected In Xilinx unconnected control signals are inactive
23
POST-ROUTE SIMULATION
Z output is delayed 10 ns from the clock positive edge because of the switch delay
24
Not valid inputEnable=0
Barrel shifter (rotor)A barrel shifter is a shift register able to shift ldquonrdquo positions in a single period its FFs contents A-H inputs are synchronously stored in the FFs when the LDST is activated When LDST is 0 upon each clock positive edge an anticlockwise n-positions rotation takes place where n is the binary value of S0 S1 and S2 signals For instance if rdquo01110000rdquo is rotated 4 positions at the first clock the content becomes ldquo00000111rdquo If then it is rotated 3 positions it becomes ldquo00111000rdquo
It must be noticed that the component is a register with laquonraquo 81 Muxs each one connected to the D inputs of the FFs The Mux control input value n is given by S0 S1 and S2
25
The circuit in figure is one of the eight 81 MUXs which select the values to be stored in the FFs
The last six right signals are the true and inverted selection signals (S1 S1 S2 S2 S3 e S3) for the 81 MUXs
Each 81 MUX is ORed with preset input value which is used together with LOAD (if LOAD=1 the OR preset value is 0) The FF output is ANDed with LOAD this zeroes all MUX outputs allowing the preset values to be stored in the FFs
The first left 8 signals are the values of the FF D inputs in the preceding period
Xilinx schematic
26
MUX
Preset value
27
Si -gt Mux 81 control signal of each FFAH -gt segnals for Preset Load
LDST=LOADWhen LDST signal is 0 all preset ANDs are zero If LDST is 1 the preset signals are enabled and all MUX outputs are zeroed
Preset AND
28
The LOAD (LDST) signal enables the preset inputs of the FFs (see the ANDs of the previous figure) and at the same time zeroes the output of the FFs (see the FFs cascaded ANDs) so as to select the preset value of the OR input
First 4 FFs Preset values
Xilinx schematicS2 S1 S0 selection signals
A B C HInput signals
LDST load signal
Clock
QA QB QC QH Outputs signals
29
Barrel Shifter
LDST=1upont the first clock positive edge the ldquo10010111rdquo value is loaded into the Barrel Shifter
The different values of Si (1 3 5) cause different device rotation Obviously with 8 sigle shifts the value becomes the initial value ldquo10010111rdquo again
A further active LDST loads a new valute into the the Barrel Shifter
This new value can be rotated again according to S signals
30
This is a typical example of how erroneous is not to laquobusraquo signals a-g qa-g and S0-2 It would have been possible to use a compact decomposable binary notation much easier to interpret where all single signals can be however displayed by laquoopeningraquo the bus
EPROM
X0nZ0m
y0kY0k
Clock
D0kQ0k
FFD0k
CK
D0kQ0kCK
EPROM based synchronous networks
Nowadays instead of the EPROMs PLAs (Programmable Logical Arrays) are used that is devices where the combinatorial functions are optimized (combinatorial functions implementations are not necessarily canonical) The basic principle is however the same
31
Design with Xilinx a synchronous logical network using 374 ALU 74181 a counter and other necessary devices which implements in sequence (after a START) signal the sum of two four bits absolute numbers (A and B) then 2rsquos complements the result then exchanges the two MSBits with the two LSBits and eventually divides arythmetically the result by 2
Example
A=1100 B=0101 =gt Sum 0001 Exchange =gt 0100 (410)2rsquos complement =gt 1100 (-410)Arithmetical division (right shift) by two =gt 1110 (-210)
The solution can be decomposed in three subsystems the control and decoding unit the datapath the input and output registersi
This is the basic architecture of the central unit of any computer
The only difference is that for the computers instead of a fixed sequence of elementary operations a new different sequence is generated for each instruction which must be executed
32
Exercise
33
The synchronous network of figure must add modulo 256 the 8 bit data received in parallel on lines D[70] The sum must be updated each clock and presented on the output lines OUT[70] In case the input data is 68H the sum must not be updated and the input data discarded In addition whenever 6 significant data have been received (that is excluding 68H) the output signal F must be set for one clock period during the reception of the sixth data A reset input is also available which zeroes the outputs and resets the data count Direct design
RSS
D[70] OUT[70]
A_RES
F
Exercise
Clock
34
RSSD[70] OUT[70]
A_RES
F
DEC_68 signal synthesis
DEC(68h)D[70] DEC_68
D[70]
A_RES
CLK
OUT[70]
RSS
D[70] OUT[70]
A_RES
F
35
Modulo 256 adder
Full Adder 8 bit
D[70]
A_RES
374
D
A_RES
Q
Q
CLK
0
1
DEC_68
OE
1
OUT[70]
CIN
0
A[70]
B[70]
36
F signal synthesis
8 bit counter
A_RES
A_RES
EN
RES
CLKU2 U1 U0
DEC(5h)
F
DEC_68
F
Synchronous RESET
37
Exercise
A synchronous sequential network must monitor the data received on the 8 lines D[70] the data received are significant only if N=1 The networks must count modulo 256 how many data are divisible by 4 while EN=1 (excluding 0) The network has two more inputs THREE e RESET The signal THREE when asserted indicates that the value for increasing the count (if the data is divisible by 4) must be 3 (on the contrary if THREE is 0 the count must be increased by 1) The synchronous RESET signal overrides all other signals Direct design
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
38
SynchronousSequentialNetwork
EN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70] (Count)
An input data is divisible by 4 of its two Lsbits (I1 and I0) are zero
An 8 integrated bit register is used for the solution
CK
39
Signal DEC(0) is 1 if all input bits are 0
A signal DIV4 decodes whether the input data is divisible by 4 and NOT zero
DIV4 = I1I0DEC(0)
A signal STORE indicates that EN=1 and the input datum is divisible by 4
STORE = ENDIV4
I[70] DEC(0) DEC(0)
40
REG8BIT
ENSTORE + RESET
CK
FA8 bit
A[70]
B[70]
S[70]
CinCout
THREE
lsquo0rsquo
1
0
lsquo3rsquo
lsquo1rsquo
D[70] Z[70] U[70]
RESET
1
0
lsquo0rsquo
8 Mux21
The FA adds 1 or 3 according to signal THREE (provided the input datum is divisble by 4 and is not 0)
41
Exercise
Design a synchronous sequential network which according to two programming bits X1 and X0 generates the following four output sequences of two bits (signals U1 and U0) which end always with 11
10-01-01-10-11 if X1=0 e X0=010-01-10-01-10-10-11 if X1=0 e X0=100-10-00-11 if X1=1 e X0=001-10-10-10-10-11 if X1=1 e X0=1
The programming signals X1 and X0 are significant only when the output is 11 The network has an synchronous RESET Direct synthesis
RSSCK
X1
X0
U1
U0
42
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5rArr10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
The SSN uses a modulo N counter with N coded by the two input signals X1 e X0 (sampled when U1U0=11)
For the solution we can use a module 8 counter with synchronous RES and a combinatorial network with X1 and X0 as inputs Since the signals X1 and X0 are significant only when U1U0 = 1 they must be sampled (X1_C e X0_C) through two flip-flops when the SSN output is U1U0 = 11 The signals U1 and U0 are the decoding of the module 8 counter status according to X1_C and X0_C
The counter must be reset when U1U0 = 11
RSSCK
X1
X0
U1
U0
43
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X1_SX1
X1_S e X0_S synthesis
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X0_SX0
44
U1 and U0 truth table
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5 rArr (0 to 4hellip)
10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
X1_S and X0_S values
Cont | 00 01 11 10000 | 00110 00110 00100 00101001 | 01001 01001 01010 01010010 | 01101 01110 01100 01110011 | 01110 10001 00011 10010 100 | 00011 10110 ------ 10110101 | ------ 11010 ------ 00011 110 | ------ 00011 ------ ------111 | ------ ------ ------ ------
Status U1U0
Is this synthesis of the network safe
No beacuse the donrsquot cares could keep the network stable out of the main cycles
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
- Slide 59
- Slide 60
- Slide 61
- Slide 62
- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
A by 4 counter is used upon the 4th clock positive edge the network controls whether the configuration is palindrome The DFF after the decoding of 3 (that is when the counter becomes 0 anew) is used because the configuration control must be delayed un period The ENABLE signal is connected to both components (when 0 both the counter and the shift are disabled)
NB The first inserted bit is sampled when the counter is increased from 0 to 1
NB in this circuit Preset and Clear signals are not connected In Xilinx unconnected control signals are inactive
23
POST-ROUTE SIMULATION
Z output is delayed 10 ns from the clock positive edge because of the switch delay
24
Not valid inputEnable=0
Barrel shifter (rotor)A barrel shifter is a shift register able to shift ldquonrdquo positions in a single period its FFs contents A-H inputs are synchronously stored in the FFs when the LDST is activated When LDST is 0 upon each clock positive edge an anticlockwise n-positions rotation takes place where n is the binary value of S0 S1 and S2 signals For instance if rdquo01110000rdquo is rotated 4 positions at the first clock the content becomes ldquo00000111rdquo If then it is rotated 3 positions it becomes ldquo00111000rdquo
It must be noticed that the component is a register with laquonraquo 81 Muxs each one connected to the D inputs of the FFs The Mux control input value n is given by S0 S1 and S2
25
The circuit in figure is one of the eight 81 MUXs which select the values to be stored in the FFs
The last six right signals are the true and inverted selection signals (S1 S1 S2 S2 S3 e S3) for the 81 MUXs
Each 81 MUX is ORed with preset input value which is used together with LOAD (if LOAD=1 the OR preset value is 0) The FF output is ANDed with LOAD this zeroes all MUX outputs allowing the preset values to be stored in the FFs
The first left 8 signals are the values of the FF D inputs in the preceding period
Xilinx schematic
26
MUX
Preset value
27
Si -gt Mux 81 control signal of each FFAH -gt segnals for Preset Load
LDST=LOADWhen LDST signal is 0 all preset ANDs are zero If LDST is 1 the preset signals are enabled and all MUX outputs are zeroed
Preset AND
28
The LOAD (LDST) signal enables the preset inputs of the FFs (see the ANDs of the previous figure) and at the same time zeroes the output of the FFs (see the FFs cascaded ANDs) so as to select the preset value of the OR input
First 4 FFs Preset values
Xilinx schematicS2 S1 S0 selection signals
A B C HInput signals
LDST load signal
Clock
QA QB QC QH Outputs signals
29
Barrel Shifter
LDST=1upont the first clock positive edge the ldquo10010111rdquo value is loaded into the Barrel Shifter
The different values of Si (1 3 5) cause different device rotation Obviously with 8 sigle shifts the value becomes the initial value ldquo10010111rdquo again
A further active LDST loads a new valute into the the Barrel Shifter
This new value can be rotated again according to S signals
30
This is a typical example of how erroneous is not to laquobusraquo signals a-g qa-g and S0-2 It would have been possible to use a compact decomposable binary notation much easier to interpret where all single signals can be however displayed by laquoopeningraquo the bus
EPROM
X0nZ0m
y0kY0k
Clock
D0kQ0k
FFD0k
CK
D0kQ0kCK
EPROM based synchronous networks
Nowadays instead of the EPROMs PLAs (Programmable Logical Arrays) are used that is devices where the combinatorial functions are optimized (combinatorial functions implementations are not necessarily canonical) The basic principle is however the same
31
Design with Xilinx a synchronous logical network using 374 ALU 74181 a counter and other necessary devices which implements in sequence (after a START) signal the sum of two four bits absolute numbers (A and B) then 2rsquos complements the result then exchanges the two MSBits with the two LSBits and eventually divides arythmetically the result by 2
Example
A=1100 B=0101 =gt Sum 0001 Exchange =gt 0100 (410)2rsquos complement =gt 1100 (-410)Arithmetical division (right shift) by two =gt 1110 (-210)
The solution can be decomposed in three subsystems the control and decoding unit the datapath the input and output registersi
This is the basic architecture of the central unit of any computer
The only difference is that for the computers instead of a fixed sequence of elementary operations a new different sequence is generated for each instruction which must be executed
32
Exercise
33
The synchronous network of figure must add modulo 256 the 8 bit data received in parallel on lines D[70] The sum must be updated each clock and presented on the output lines OUT[70] In case the input data is 68H the sum must not be updated and the input data discarded In addition whenever 6 significant data have been received (that is excluding 68H) the output signal F must be set for one clock period during the reception of the sixth data A reset input is also available which zeroes the outputs and resets the data count Direct design
RSS
D[70] OUT[70]
A_RES
F
Exercise
Clock
34
RSSD[70] OUT[70]
A_RES
F
DEC_68 signal synthesis
DEC(68h)D[70] DEC_68
D[70]
A_RES
CLK
OUT[70]
RSS
D[70] OUT[70]
A_RES
F
35
Modulo 256 adder
Full Adder 8 bit
D[70]
A_RES
374
D
A_RES
Q
Q
CLK
0
1
DEC_68
OE
1
OUT[70]
CIN
0
A[70]
B[70]
36
F signal synthesis
8 bit counter
A_RES
A_RES
EN
RES
CLKU2 U1 U0
DEC(5h)
F
DEC_68
F
Synchronous RESET
37
Exercise
A synchronous sequential network must monitor the data received on the 8 lines D[70] the data received are significant only if N=1 The networks must count modulo 256 how many data are divisible by 4 while EN=1 (excluding 0) The network has two more inputs THREE e RESET The signal THREE when asserted indicates that the value for increasing the count (if the data is divisible by 4) must be 3 (on the contrary if THREE is 0 the count must be increased by 1) The synchronous RESET signal overrides all other signals Direct design
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
38
SynchronousSequentialNetwork
EN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70] (Count)
An input data is divisible by 4 of its two Lsbits (I1 and I0) are zero
An 8 integrated bit register is used for the solution
CK
39
Signal DEC(0) is 1 if all input bits are 0
A signal DIV4 decodes whether the input data is divisible by 4 and NOT zero
DIV4 = I1I0DEC(0)
A signal STORE indicates that EN=1 and the input datum is divisible by 4
STORE = ENDIV4
I[70] DEC(0) DEC(0)
40
REG8BIT
ENSTORE + RESET
CK
FA8 bit
A[70]
B[70]
S[70]
CinCout
THREE
lsquo0rsquo
1
0
lsquo3rsquo
lsquo1rsquo
D[70] Z[70] U[70]
RESET
1
0
lsquo0rsquo
8 Mux21
The FA adds 1 or 3 according to signal THREE (provided the input datum is divisble by 4 and is not 0)
41
Exercise
Design a synchronous sequential network which according to two programming bits X1 and X0 generates the following four output sequences of two bits (signals U1 and U0) which end always with 11
10-01-01-10-11 if X1=0 e X0=010-01-10-01-10-10-11 if X1=0 e X0=100-10-00-11 if X1=1 e X0=001-10-10-10-10-11 if X1=1 e X0=1
The programming signals X1 and X0 are significant only when the output is 11 The network has an synchronous RESET Direct synthesis
RSSCK
X1
X0
U1
U0
42
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5rArr10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
The SSN uses a modulo N counter with N coded by the two input signals X1 e X0 (sampled when U1U0=11)
For the solution we can use a module 8 counter with synchronous RES and a combinatorial network with X1 and X0 as inputs Since the signals X1 and X0 are significant only when U1U0 = 1 they must be sampled (X1_C e X0_C) through two flip-flops when the SSN output is U1U0 = 11 The signals U1 and U0 are the decoding of the module 8 counter status according to X1_C and X0_C
The counter must be reset when U1U0 = 11
RSSCK
X1
X0
U1
U0
43
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X1_SX1
X1_S e X0_S synthesis
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X0_SX0
44
U1 and U0 truth table
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5 rArr (0 to 4hellip)
10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
X1_S and X0_S values
Cont | 00 01 11 10000 | 00110 00110 00100 00101001 | 01001 01001 01010 01010010 | 01101 01110 01100 01110011 | 01110 10001 00011 10010 100 | 00011 10110 ------ 10110101 | ------ 11010 ------ 00011 110 | ------ 00011 ------ ------111 | ------ ------ ------ ------
Status U1U0
Is this synthesis of the network safe
No beacuse the donrsquot cares could keep the network stable out of the main cycles
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
- Slide 59
- Slide 60
- Slide 61
- Slide 62
- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
POST-ROUTE SIMULATION
Z output is delayed 10 ns from the clock positive edge because of the switch delay
24
Not valid inputEnable=0
Barrel shifter (rotor)A barrel shifter is a shift register able to shift ldquonrdquo positions in a single period its FFs contents A-H inputs are synchronously stored in the FFs when the LDST is activated When LDST is 0 upon each clock positive edge an anticlockwise n-positions rotation takes place where n is the binary value of S0 S1 and S2 signals For instance if rdquo01110000rdquo is rotated 4 positions at the first clock the content becomes ldquo00000111rdquo If then it is rotated 3 positions it becomes ldquo00111000rdquo
It must be noticed that the component is a register with laquonraquo 81 Muxs each one connected to the D inputs of the FFs The Mux control input value n is given by S0 S1 and S2
25
The circuit in figure is one of the eight 81 MUXs which select the values to be stored in the FFs
The last six right signals are the true and inverted selection signals (S1 S1 S2 S2 S3 e S3) for the 81 MUXs
Each 81 MUX is ORed with preset input value which is used together with LOAD (if LOAD=1 the OR preset value is 0) The FF output is ANDed with LOAD this zeroes all MUX outputs allowing the preset values to be stored in the FFs
The first left 8 signals are the values of the FF D inputs in the preceding period
Xilinx schematic
26
MUX
Preset value
27
Si -gt Mux 81 control signal of each FFAH -gt segnals for Preset Load
LDST=LOADWhen LDST signal is 0 all preset ANDs are zero If LDST is 1 the preset signals are enabled and all MUX outputs are zeroed
Preset AND
28
The LOAD (LDST) signal enables the preset inputs of the FFs (see the ANDs of the previous figure) and at the same time zeroes the output of the FFs (see the FFs cascaded ANDs) so as to select the preset value of the OR input
First 4 FFs Preset values
Xilinx schematicS2 S1 S0 selection signals
A B C HInput signals
LDST load signal
Clock
QA QB QC QH Outputs signals
29
Barrel Shifter
LDST=1upont the first clock positive edge the ldquo10010111rdquo value is loaded into the Barrel Shifter
The different values of Si (1 3 5) cause different device rotation Obviously with 8 sigle shifts the value becomes the initial value ldquo10010111rdquo again
A further active LDST loads a new valute into the the Barrel Shifter
This new value can be rotated again according to S signals
30
This is a typical example of how erroneous is not to laquobusraquo signals a-g qa-g and S0-2 It would have been possible to use a compact decomposable binary notation much easier to interpret where all single signals can be however displayed by laquoopeningraquo the bus
EPROM
X0nZ0m
y0kY0k
Clock
D0kQ0k
FFD0k
CK
D0kQ0kCK
EPROM based synchronous networks
Nowadays instead of the EPROMs PLAs (Programmable Logical Arrays) are used that is devices where the combinatorial functions are optimized (combinatorial functions implementations are not necessarily canonical) The basic principle is however the same
31
Design with Xilinx a synchronous logical network using 374 ALU 74181 a counter and other necessary devices which implements in sequence (after a START) signal the sum of two four bits absolute numbers (A and B) then 2rsquos complements the result then exchanges the two MSBits with the two LSBits and eventually divides arythmetically the result by 2
Example
A=1100 B=0101 =gt Sum 0001 Exchange =gt 0100 (410)2rsquos complement =gt 1100 (-410)Arithmetical division (right shift) by two =gt 1110 (-210)
The solution can be decomposed in three subsystems the control and decoding unit the datapath the input and output registersi
This is the basic architecture of the central unit of any computer
The only difference is that for the computers instead of a fixed sequence of elementary operations a new different sequence is generated for each instruction which must be executed
32
Exercise
33
The synchronous network of figure must add modulo 256 the 8 bit data received in parallel on lines D[70] The sum must be updated each clock and presented on the output lines OUT[70] In case the input data is 68H the sum must not be updated and the input data discarded In addition whenever 6 significant data have been received (that is excluding 68H) the output signal F must be set for one clock period during the reception of the sixth data A reset input is also available which zeroes the outputs and resets the data count Direct design
RSS
D[70] OUT[70]
A_RES
F
Exercise
Clock
34
RSSD[70] OUT[70]
A_RES
F
DEC_68 signal synthesis
DEC(68h)D[70] DEC_68
D[70]
A_RES
CLK
OUT[70]
RSS
D[70] OUT[70]
A_RES
F
35
Modulo 256 adder
Full Adder 8 bit
D[70]
A_RES
374
D
A_RES
Q
Q
CLK
0
1
DEC_68
OE
1
OUT[70]
CIN
0
A[70]
B[70]
36
F signal synthesis
8 bit counter
A_RES
A_RES
EN
RES
CLKU2 U1 U0
DEC(5h)
F
DEC_68
F
Synchronous RESET
37
Exercise
A synchronous sequential network must monitor the data received on the 8 lines D[70] the data received are significant only if N=1 The networks must count modulo 256 how many data are divisible by 4 while EN=1 (excluding 0) The network has two more inputs THREE e RESET The signal THREE when asserted indicates that the value for increasing the count (if the data is divisible by 4) must be 3 (on the contrary if THREE is 0 the count must be increased by 1) The synchronous RESET signal overrides all other signals Direct design
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
38
SynchronousSequentialNetwork
EN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70] (Count)
An input data is divisible by 4 of its two Lsbits (I1 and I0) are zero
An 8 integrated bit register is used for the solution
CK
39
Signal DEC(0) is 1 if all input bits are 0
A signal DIV4 decodes whether the input data is divisible by 4 and NOT zero
DIV4 = I1I0DEC(0)
A signal STORE indicates that EN=1 and the input datum is divisible by 4
STORE = ENDIV4
I[70] DEC(0) DEC(0)
40
REG8BIT
ENSTORE + RESET
CK
FA8 bit
A[70]
B[70]
S[70]
CinCout
THREE
lsquo0rsquo
1
0
lsquo3rsquo
lsquo1rsquo
D[70] Z[70] U[70]
RESET
1
0
lsquo0rsquo
8 Mux21
The FA adds 1 or 3 according to signal THREE (provided the input datum is divisble by 4 and is not 0)
41
Exercise
Design a synchronous sequential network which according to two programming bits X1 and X0 generates the following four output sequences of two bits (signals U1 and U0) which end always with 11
10-01-01-10-11 if X1=0 e X0=010-01-10-01-10-10-11 if X1=0 e X0=100-10-00-11 if X1=1 e X0=001-10-10-10-10-11 if X1=1 e X0=1
The programming signals X1 and X0 are significant only when the output is 11 The network has an synchronous RESET Direct synthesis
RSSCK
X1
X0
U1
U0
42
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5rArr10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
The SSN uses a modulo N counter with N coded by the two input signals X1 e X0 (sampled when U1U0=11)
For the solution we can use a module 8 counter with synchronous RES and a combinatorial network with X1 and X0 as inputs Since the signals X1 and X0 are significant only when U1U0 = 1 they must be sampled (X1_C e X0_C) through two flip-flops when the SSN output is U1U0 = 11 The signals U1 and U0 are the decoding of the module 8 counter status according to X1_C and X0_C
The counter must be reset when U1U0 = 11
RSSCK
X1
X0
U1
U0
43
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X1_SX1
X1_S e X0_S synthesis
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X0_SX0
44
U1 and U0 truth table
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5 rArr (0 to 4hellip)
10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
X1_S and X0_S values
Cont | 00 01 11 10000 | 00110 00110 00100 00101001 | 01001 01001 01010 01010010 | 01101 01110 01100 01110011 | 01110 10001 00011 10010 100 | 00011 10110 ------ 10110101 | ------ 11010 ------ 00011 110 | ------ 00011 ------ ------111 | ------ ------ ------ ------
Status U1U0
Is this synthesis of the network safe
No beacuse the donrsquot cares could keep the network stable out of the main cycles
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
- Slide 59
- Slide 60
- Slide 61
- Slide 62
- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
Barrel shifter (rotor)A barrel shifter is a shift register able to shift ldquonrdquo positions in a single period its FFs contents A-H inputs are synchronously stored in the FFs when the LDST is activated When LDST is 0 upon each clock positive edge an anticlockwise n-positions rotation takes place where n is the binary value of S0 S1 and S2 signals For instance if rdquo01110000rdquo is rotated 4 positions at the first clock the content becomes ldquo00000111rdquo If then it is rotated 3 positions it becomes ldquo00111000rdquo
It must be noticed that the component is a register with laquonraquo 81 Muxs each one connected to the D inputs of the FFs The Mux control input value n is given by S0 S1 and S2
25
The circuit in figure is one of the eight 81 MUXs which select the values to be stored in the FFs
The last six right signals are the true and inverted selection signals (S1 S1 S2 S2 S3 e S3) for the 81 MUXs
Each 81 MUX is ORed with preset input value which is used together with LOAD (if LOAD=1 the OR preset value is 0) The FF output is ANDed with LOAD this zeroes all MUX outputs allowing the preset values to be stored in the FFs
The first left 8 signals are the values of the FF D inputs in the preceding period
Xilinx schematic
26
MUX
Preset value
27
Si -gt Mux 81 control signal of each FFAH -gt segnals for Preset Load
LDST=LOADWhen LDST signal is 0 all preset ANDs are zero If LDST is 1 the preset signals are enabled and all MUX outputs are zeroed
Preset AND
28
The LOAD (LDST) signal enables the preset inputs of the FFs (see the ANDs of the previous figure) and at the same time zeroes the output of the FFs (see the FFs cascaded ANDs) so as to select the preset value of the OR input
First 4 FFs Preset values
Xilinx schematicS2 S1 S0 selection signals
A B C HInput signals
LDST load signal
Clock
QA QB QC QH Outputs signals
29
Barrel Shifter
LDST=1upont the first clock positive edge the ldquo10010111rdquo value is loaded into the Barrel Shifter
The different values of Si (1 3 5) cause different device rotation Obviously with 8 sigle shifts the value becomes the initial value ldquo10010111rdquo again
A further active LDST loads a new valute into the the Barrel Shifter
This new value can be rotated again according to S signals
30
This is a typical example of how erroneous is not to laquobusraquo signals a-g qa-g and S0-2 It would have been possible to use a compact decomposable binary notation much easier to interpret where all single signals can be however displayed by laquoopeningraquo the bus
EPROM
X0nZ0m
y0kY0k
Clock
D0kQ0k
FFD0k
CK
D0kQ0kCK
EPROM based synchronous networks
Nowadays instead of the EPROMs PLAs (Programmable Logical Arrays) are used that is devices where the combinatorial functions are optimized (combinatorial functions implementations are not necessarily canonical) The basic principle is however the same
31
Design with Xilinx a synchronous logical network using 374 ALU 74181 a counter and other necessary devices which implements in sequence (after a START) signal the sum of two four bits absolute numbers (A and B) then 2rsquos complements the result then exchanges the two MSBits with the two LSBits and eventually divides arythmetically the result by 2
Example
A=1100 B=0101 =gt Sum 0001 Exchange =gt 0100 (410)2rsquos complement =gt 1100 (-410)Arithmetical division (right shift) by two =gt 1110 (-210)
The solution can be decomposed in three subsystems the control and decoding unit the datapath the input and output registersi
This is the basic architecture of the central unit of any computer
The only difference is that for the computers instead of a fixed sequence of elementary operations a new different sequence is generated for each instruction which must be executed
32
Exercise
33
The synchronous network of figure must add modulo 256 the 8 bit data received in parallel on lines D[70] The sum must be updated each clock and presented on the output lines OUT[70] In case the input data is 68H the sum must not be updated and the input data discarded In addition whenever 6 significant data have been received (that is excluding 68H) the output signal F must be set for one clock period during the reception of the sixth data A reset input is also available which zeroes the outputs and resets the data count Direct design
RSS
D[70] OUT[70]
A_RES
F
Exercise
Clock
34
RSSD[70] OUT[70]
A_RES
F
DEC_68 signal synthesis
DEC(68h)D[70] DEC_68
D[70]
A_RES
CLK
OUT[70]
RSS
D[70] OUT[70]
A_RES
F
35
Modulo 256 adder
Full Adder 8 bit
D[70]
A_RES
374
D
A_RES
Q
Q
CLK
0
1
DEC_68
OE
1
OUT[70]
CIN
0
A[70]
B[70]
36
F signal synthesis
8 bit counter
A_RES
A_RES
EN
RES
CLKU2 U1 U0
DEC(5h)
F
DEC_68
F
Synchronous RESET
37
Exercise
A synchronous sequential network must monitor the data received on the 8 lines D[70] the data received are significant only if N=1 The networks must count modulo 256 how many data are divisible by 4 while EN=1 (excluding 0) The network has two more inputs THREE e RESET The signal THREE when asserted indicates that the value for increasing the count (if the data is divisible by 4) must be 3 (on the contrary if THREE is 0 the count must be increased by 1) The synchronous RESET signal overrides all other signals Direct design
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
38
SynchronousSequentialNetwork
EN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70] (Count)
An input data is divisible by 4 of its two Lsbits (I1 and I0) are zero
An 8 integrated bit register is used for the solution
CK
39
Signal DEC(0) is 1 if all input bits are 0
A signal DIV4 decodes whether the input data is divisible by 4 and NOT zero
DIV4 = I1I0DEC(0)
A signal STORE indicates that EN=1 and the input datum is divisible by 4
STORE = ENDIV4
I[70] DEC(0) DEC(0)
40
REG8BIT
ENSTORE + RESET
CK
FA8 bit
A[70]
B[70]
S[70]
CinCout
THREE
lsquo0rsquo
1
0
lsquo3rsquo
lsquo1rsquo
D[70] Z[70] U[70]
RESET
1
0
lsquo0rsquo
8 Mux21
The FA adds 1 or 3 according to signal THREE (provided the input datum is divisble by 4 and is not 0)
41
Exercise
Design a synchronous sequential network which according to two programming bits X1 and X0 generates the following four output sequences of two bits (signals U1 and U0) which end always with 11
10-01-01-10-11 if X1=0 e X0=010-01-10-01-10-10-11 if X1=0 e X0=100-10-00-11 if X1=1 e X0=001-10-10-10-10-11 if X1=1 e X0=1
The programming signals X1 and X0 are significant only when the output is 11 The network has an synchronous RESET Direct synthesis
RSSCK
X1
X0
U1
U0
42
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5rArr10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
The SSN uses a modulo N counter with N coded by the two input signals X1 e X0 (sampled when U1U0=11)
For the solution we can use a module 8 counter with synchronous RES and a combinatorial network with X1 and X0 as inputs Since the signals X1 and X0 are significant only when U1U0 = 1 they must be sampled (X1_C e X0_C) through two flip-flops when the SSN output is U1U0 = 11 The signals U1 and U0 are the decoding of the module 8 counter status according to X1_C and X0_C
The counter must be reset when U1U0 = 11
RSSCK
X1
X0
U1
U0
43
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X1_SX1
X1_S e X0_S synthesis
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X0_SX0
44
U1 and U0 truth table
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5 rArr (0 to 4hellip)
10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
X1_S and X0_S values
Cont | 00 01 11 10000 | 00110 00110 00100 00101001 | 01001 01001 01010 01010010 | 01101 01110 01100 01110011 | 01110 10001 00011 10010 100 | 00011 10110 ------ 10110101 | ------ 11010 ------ 00011 110 | ------ 00011 ------ ------111 | ------ ------ ------ ------
Status U1U0
Is this synthesis of the network safe
No beacuse the donrsquot cares could keep the network stable out of the main cycles
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
- Slide 59
- Slide 60
- Slide 61
- Slide 62
- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
The circuit in figure is one of the eight 81 MUXs which select the values to be stored in the FFs
The last six right signals are the true and inverted selection signals (S1 S1 S2 S2 S3 e S3) for the 81 MUXs
Each 81 MUX is ORed with preset input value which is used together with LOAD (if LOAD=1 the OR preset value is 0) The FF output is ANDed with LOAD this zeroes all MUX outputs allowing the preset values to be stored in the FFs
The first left 8 signals are the values of the FF D inputs in the preceding period
Xilinx schematic
26
MUX
Preset value
27
Si -gt Mux 81 control signal of each FFAH -gt segnals for Preset Load
LDST=LOADWhen LDST signal is 0 all preset ANDs are zero If LDST is 1 the preset signals are enabled and all MUX outputs are zeroed
Preset AND
28
The LOAD (LDST) signal enables the preset inputs of the FFs (see the ANDs of the previous figure) and at the same time zeroes the output of the FFs (see the FFs cascaded ANDs) so as to select the preset value of the OR input
First 4 FFs Preset values
Xilinx schematicS2 S1 S0 selection signals
A B C HInput signals
LDST load signal
Clock
QA QB QC QH Outputs signals
29
Barrel Shifter
LDST=1upont the first clock positive edge the ldquo10010111rdquo value is loaded into the Barrel Shifter
The different values of Si (1 3 5) cause different device rotation Obviously with 8 sigle shifts the value becomes the initial value ldquo10010111rdquo again
A further active LDST loads a new valute into the the Barrel Shifter
This new value can be rotated again according to S signals
30
This is a typical example of how erroneous is not to laquobusraquo signals a-g qa-g and S0-2 It would have been possible to use a compact decomposable binary notation much easier to interpret where all single signals can be however displayed by laquoopeningraquo the bus
EPROM
X0nZ0m
y0kY0k
Clock
D0kQ0k
FFD0k
CK
D0kQ0kCK
EPROM based synchronous networks
Nowadays instead of the EPROMs PLAs (Programmable Logical Arrays) are used that is devices where the combinatorial functions are optimized (combinatorial functions implementations are not necessarily canonical) The basic principle is however the same
31
Design with Xilinx a synchronous logical network using 374 ALU 74181 a counter and other necessary devices which implements in sequence (after a START) signal the sum of two four bits absolute numbers (A and B) then 2rsquos complements the result then exchanges the two MSBits with the two LSBits and eventually divides arythmetically the result by 2
Example
A=1100 B=0101 =gt Sum 0001 Exchange =gt 0100 (410)2rsquos complement =gt 1100 (-410)Arithmetical division (right shift) by two =gt 1110 (-210)
The solution can be decomposed in three subsystems the control and decoding unit the datapath the input and output registersi
This is the basic architecture of the central unit of any computer
The only difference is that for the computers instead of a fixed sequence of elementary operations a new different sequence is generated for each instruction which must be executed
32
Exercise
33
The synchronous network of figure must add modulo 256 the 8 bit data received in parallel on lines D[70] The sum must be updated each clock and presented on the output lines OUT[70] In case the input data is 68H the sum must not be updated and the input data discarded In addition whenever 6 significant data have been received (that is excluding 68H) the output signal F must be set for one clock period during the reception of the sixth data A reset input is also available which zeroes the outputs and resets the data count Direct design
RSS
D[70] OUT[70]
A_RES
F
Exercise
Clock
34
RSSD[70] OUT[70]
A_RES
F
DEC_68 signal synthesis
DEC(68h)D[70] DEC_68
D[70]
A_RES
CLK
OUT[70]
RSS
D[70] OUT[70]
A_RES
F
35
Modulo 256 adder
Full Adder 8 bit
D[70]
A_RES
374
D
A_RES
Q
Q
CLK
0
1
DEC_68
OE
1
OUT[70]
CIN
0
A[70]
B[70]
36
F signal synthesis
8 bit counter
A_RES
A_RES
EN
RES
CLKU2 U1 U0
DEC(5h)
F
DEC_68
F
Synchronous RESET
37
Exercise
A synchronous sequential network must monitor the data received on the 8 lines D[70] the data received are significant only if N=1 The networks must count modulo 256 how many data are divisible by 4 while EN=1 (excluding 0) The network has two more inputs THREE e RESET The signal THREE when asserted indicates that the value for increasing the count (if the data is divisible by 4) must be 3 (on the contrary if THREE is 0 the count must be increased by 1) The synchronous RESET signal overrides all other signals Direct design
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
38
SynchronousSequentialNetwork
EN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70] (Count)
An input data is divisible by 4 of its two Lsbits (I1 and I0) are zero
An 8 integrated bit register is used for the solution
CK
39
Signal DEC(0) is 1 if all input bits are 0
A signal DIV4 decodes whether the input data is divisible by 4 and NOT zero
DIV4 = I1I0DEC(0)
A signal STORE indicates that EN=1 and the input datum is divisible by 4
STORE = ENDIV4
I[70] DEC(0) DEC(0)
40
REG8BIT
ENSTORE + RESET
CK
FA8 bit
A[70]
B[70]
S[70]
CinCout
THREE
lsquo0rsquo
1
0
lsquo3rsquo
lsquo1rsquo
D[70] Z[70] U[70]
RESET
1
0
lsquo0rsquo
8 Mux21
The FA adds 1 or 3 according to signal THREE (provided the input datum is divisble by 4 and is not 0)
41
Exercise
Design a synchronous sequential network which according to two programming bits X1 and X0 generates the following four output sequences of two bits (signals U1 and U0) which end always with 11
10-01-01-10-11 if X1=0 e X0=010-01-10-01-10-10-11 if X1=0 e X0=100-10-00-11 if X1=1 e X0=001-10-10-10-10-11 if X1=1 e X0=1
The programming signals X1 and X0 are significant only when the output is 11 The network has an synchronous RESET Direct synthesis
RSSCK
X1
X0
U1
U0
42
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5rArr10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
The SSN uses a modulo N counter with N coded by the two input signals X1 e X0 (sampled when U1U0=11)
For the solution we can use a module 8 counter with synchronous RES and a combinatorial network with X1 and X0 as inputs Since the signals X1 and X0 are significant only when U1U0 = 1 they must be sampled (X1_C e X0_C) through two flip-flops when the SSN output is U1U0 = 11 The signals U1 and U0 are the decoding of the module 8 counter status according to X1_C and X0_C
The counter must be reset when U1U0 = 11
RSSCK
X1
X0
U1
U0
43
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X1_SX1
X1_S e X0_S synthesis
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X0_SX0
44
U1 and U0 truth table
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5 rArr (0 to 4hellip)
10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
X1_S and X0_S values
Cont | 00 01 11 10000 | 00110 00110 00100 00101001 | 01001 01001 01010 01010010 | 01101 01110 01100 01110011 | 01110 10001 00011 10010 100 | 00011 10110 ------ 10110101 | ------ 11010 ------ 00011 110 | ------ 00011 ------ ------111 | ------ ------ ------ ------
Status U1U0
Is this synthesis of the network safe
No beacuse the donrsquot cares could keep the network stable out of the main cycles
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
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- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
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- Slide 60
- Slide 61
- Slide 62
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- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
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- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
27
Si -gt Mux 81 control signal of each FFAH -gt segnals for Preset Load
LDST=LOADWhen LDST signal is 0 all preset ANDs are zero If LDST is 1 the preset signals are enabled and all MUX outputs are zeroed
Preset AND
28
The LOAD (LDST) signal enables the preset inputs of the FFs (see the ANDs of the previous figure) and at the same time zeroes the output of the FFs (see the FFs cascaded ANDs) so as to select the preset value of the OR input
First 4 FFs Preset values
Xilinx schematicS2 S1 S0 selection signals
A B C HInput signals
LDST load signal
Clock
QA QB QC QH Outputs signals
29
Barrel Shifter
LDST=1upont the first clock positive edge the ldquo10010111rdquo value is loaded into the Barrel Shifter
The different values of Si (1 3 5) cause different device rotation Obviously with 8 sigle shifts the value becomes the initial value ldquo10010111rdquo again
A further active LDST loads a new valute into the the Barrel Shifter
This new value can be rotated again according to S signals
30
This is a typical example of how erroneous is not to laquobusraquo signals a-g qa-g and S0-2 It would have been possible to use a compact decomposable binary notation much easier to interpret where all single signals can be however displayed by laquoopeningraquo the bus
EPROM
X0nZ0m
y0kY0k
Clock
D0kQ0k
FFD0k
CK
D0kQ0kCK
EPROM based synchronous networks
Nowadays instead of the EPROMs PLAs (Programmable Logical Arrays) are used that is devices where the combinatorial functions are optimized (combinatorial functions implementations are not necessarily canonical) The basic principle is however the same
31
Design with Xilinx a synchronous logical network using 374 ALU 74181 a counter and other necessary devices which implements in sequence (after a START) signal the sum of two four bits absolute numbers (A and B) then 2rsquos complements the result then exchanges the two MSBits with the two LSBits and eventually divides arythmetically the result by 2
Example
A=1100 B=0101 =gt Sum 0001 Exchange =gt 0100 (410)2rsquos complement =gt 1100 (-410)Arithmetical division (right shift) by two =gt 1110 (-210)
The solution can be decomposed in three subsystems the control and decoding unit the datapath the input and output registersi
This is the basic architecture of the central unit of any computer
The only difference is that for the computers instead of a fixed sequence of elementary operations a new different sequence is generated for each instruction which must be executed
32
Exercise
33
The synchronous network of figure must add modulo 256 the 8 bit data received in parallel on lines D[70] The sum must be updated each clock and presented on the output lines OUT[70] In case the input data is 68H the sum must not be updated and the input data discarded In addition whenever 6 significant data have been received (that is excluding 68H) the output signal F must be set for one clock period during the reception of the sixth data A reset input is also available which zeroes the outputs and resets the data count Direct design
RSS
D[70] OUT[70]
A_RES
F
Exercise
Clock
34
RSSD[70] OUT[70]
A_RES
F
DEC_68 signal synthesis
DEC(68h)D[70] DEC_68
D[70]
A_RES
CLK
OUT[70]
RSS
D[70] OUT[70]
A_RES
F
35
Modulo 256 adder
Full Adder 8 bit
D[70]
A_RES
374
D
A_RES
Q
Q
CLK
0
1
DEC_68
OE
1
OUT[70]
CIN
0
A[70]
B[70]
36
F signal synthesis
8 bit counter
A_RES
A_RES
EN
RES
CLKU2 U1 U0
DEC(5h)
F
DEC_68
F
Synchronous RESET
37
Exercise
A synchronous sequential network must monitor the data received on the 8 lines D[70] the data received are significant only if N=1 The networks must count modulo 256 how many data are divisible by 4 while EN=1 (excluding 0) The network has two more inputs THREE e RESET The signal THREE when asserted indicates that the value for increasing the count (if the data is divisible by 4) must be 3 (on the contrary if THREE is 0 the count must be increased by 1) The synchronous RESET signal overrides all other signals Direct design
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
38
SynchronousSequentialNetwork
EN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70] (Count)
An input data is divisible by 4 of its two Lsbits (I1 and I0) are zero
An 8 integrated bit register is used for the solution
CK
39
Signal DEC(0) is 1 if all input bits are 0
A signal DIV4 decodes whether the input data is divisible by 4 and NOT zero
DIV4 = I1I0DEC(0)
A signal STORE indicates that EN=1 and the input datum is divisible by 4
STORE = ENDIV4
I[70] DEC(0) DEC(0)
40
REG8BIT
ENSTORE + RESET
CK
FA8 bit
A[70]
B[70]
S[70]
CinCout
THREE
lsquo0rsquo
1
0
lsquo3rsquo
lsquo1rsquo
D[70] Z[70] U[70]
RESET
1
0
lsquo0rsquo
8 Mux21
The FA adds 1 or 3 according to signal THREE (provided the input datum is divisble by 4 and is not 0)
41
Exercise
Design a synchronous sequential network which according to two programming bits X1 and X0 generates the following four output sequences of two bits (signals U1 and U0) which end always with 11
10-01-01-10-11 if X1=0 e X0=010-01-10-01-10-10-11 if X1=0 e X0=100-10-00-11 if X1=1 e X0=001-10-10-10-10-11 if X1=1 e X0=1
The programming signals X1 and X0 are significant only when the output is 11 The network has an synchronous RESET Direct synthesis
RSSCK
X1
X0
U1
U0
42
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5rArr10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
The SSN uses a modulo N counter with N coded by the two input signals X1 e X0 (sampled when U1U0=11)
For the solution we can use a module 8 counter with synchronous RES and a combinatorial network with X1 and X0 as inputs Since the signals X1 and X0 are significant only when U1U0 = 1 they must be sampled (X1_C e X0_C) through two flip-flops when the SSN output is U1U0 = 11 The signals U1 and U0 are the decoding of the module 8 counter status according to X1_C and X0_C
The counter must be reset when U1U0 = 11
RSSCK
X1
X0
U1
U0
43
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X1_SX1
X1_S e X0_S synthesis
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X0_SX0
44
U1 and U0 truth table
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5 rArr (0 to 4hellip)
10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
X1_S and X0_S values
Cont | 00 01 11 10000 | 00110 00110 00100 00101001 | 01001 01001 01010 01010010 | 01101 01110 01100 01110011 | 01110 10001 00011 10010 100 | 00011 10110 ------ 10110101 | ------ 11010 ------ 00011 110 | ------ 00011 ------ ------111 | ------ ------ ------ ------
Status U1U0
Is this synthesis of the network safe
No beacuse the donrsquot cares could keep the network stable out of the main cycles
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
- Slide 59
- Slide 60
- Slide 61
- Slide 62
- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
28
The LOAD (LDST) signal enables the preset inputs of the FFs (see the ANDs of the previous figure) and at the same time zeroes the output of the FFs (see the FFs cascaded ANDs) so as to select the preset value of the OR input
First 4 FFs Preset values
Xilinx schematicS2 S1 S0 selection signals
A B C HInput signals
LDST load signal
Clock
QA QB QC QH Outputs signals
29
Barrel Shifter
LDST=1upont the first clock positive edge the ldquo10010111rdquo value is loaded into the Barrel Shifter
The different values of Si (1 3 5) cause different device rotation Obviously with 8 sigle shifts the value becomes the initial value ldquo10010111rdquo again
A further active LDST loads a new valute into the the Barrel Shifter
This new value can be rotated again according to S signals
30
This is a typical example of how erroneous is not to laquobusraquo signals a-g qa-g and S0-2 It would have been possible to use a compact decomposable binary notation much easier to interpret where all single signals can be however displayed by laquoopeningraquo the bus
EPROM
X0nZ0m
y0kY0k
Clock
D0kQ0k
FFD0k
CK
D0kQ0kCK
EPROM based synchronous networks
Nowadays instead of the EPROMs PLAs (Programmable Logical Arrays) are used that is devices where the combinatorial functions are optimized (combinatorial functions implementations are not necessarily canonical) The basic principle is however the same
31
Design with Xilinx a synchronous logical network using 374 ALU 74181 a counter and other necessary devices which implements in sequence (after a START) signal the sum of two four bits absolute numbers (A and B) then 2rsquos complements the result then exchanges the two MSBits with the two LSBits and eventually divides arythmetically the result by 2
Example
A=1100 B=0101 =gt Sum 0001 Exchange =gt 0100 (410)2rsquos complement =gt 1100 (-410)Arithmetical division (right shift) by two =gt 1110 (-210)
The solution can be decomposed in three subsystems the control and decoding unit the datapath the input and output registersi
This is the basic architecture of the central unit of any computer
The only difference is that for the computers instead of a fixed sequence of elementary operations a new different sequence is generated for each instruction which must be executed
32
Exercise
33
The synchronous network of figure must add modulo 256 the 8 bit data received in parallel on lines D[70] The sum must be updated each clock and presented on the output lines OUT[70] In case the input data is 68H the sum must not be updated and the input data discarded In addition whenever 6 significant data have been received (that is excluding 68H) the output signal F must be set for one clock period during the reception of the sixth data A reset input is also available which zeroes the outputs and resets the data count Direct design
RSS
D[70] OUT[70]
A_RES
F
Exercise
Clock
34
RSSD[70] OUT[70]
A_RES
F
DEC_68 signal synthesis
DEC(68h)D[70] DEC_68
D[70]
A_RES
CLK
OUT[70]
RSS
D[70] OUT[70]
A_RES
F
35
Modulo 256 adder
Full Adder 8 bit
D[70]
A_RES
374
D
A_RES
Q
Q
CLK
0
1
DEC_68
OE
1
OUT[70]
CIN
0
A[70]
B[70]
36
F signal synthesis
8 bit counter
A_RES
A_RES
EN
RES
CLKU2 U1 U0
DEC(5h)
F
DEC_68
F
Synchronous RESET
37
Exercise
A synchronous sequential network must monitor the data received on the 8 lines D[70] the data received are significant only if N=1 The networks must count modulo 256 how many data are divisible by 4 while EN=1 (excluding 0) The network has two more inputs THREE e RESET The signal THREE when asserted indicates that the value for increasing the count (if the data is divisible by 4) must be 3 (on the contrary if THREE is 0 the count must be increased by 1) The synchronous RESET signal overrides all other signals Direct design
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
38
SynchronousSequentialNetwork
EN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70] (Count)
An input data is divisible by 4 of its two Lsbits (I1 and I0) are zero
An 8 integrated bit register is used for the solution
CK
39
Signal DEC(0) is 1 if all input bits are 0
A signal DIV4 decodes whether the input data is divisible by 4 and NOT zero
DIV4 = I1I0DEC(0)
A signal STORE indicates that EN=1 and the input datum is divisible by 4
STORE = ENDIV4
I[70] DEC(0) DEC(0)
40
REG8BIT
ENSTORE + RESET
CK
FA8 bit
A[70]
B[70]
S[70]
CinCout
THREE
lsquo0rsquo
1
0
lsquo3rsquo
lsquo1rsquo
D[70] Z[70] U[70]
RESET
1
0
lsquo0rsquo
8 Mux21
The FA adds 1 or 3 according to signal THREE (provided the input datum is divisble by 4 and is not 0)
41
Exercise
Design a synchronous sequential network which according to two programming bits X1 and X0 generates the following four output sequences of two bits (signals U1 and U0) which end always with 11
10-01-01-10-11 if X1=0 e X0=010-01-10-01-10-10-11 if X1=0 e X0=100-10-00-11 if X1=1 e X0=001-10-10-10-10-11 if X1=1 e X0=1
The programming signals X1 and X0 are significant only when the output is 11 The network has an synchronous RESET Direct synthesis
RSSCK
X1
X0
U1
U0
42
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5rArr10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
The SSN uses a modulo N counter with N coded by the two input signals X1 e X0 (sampled when U1U0=11)
For the solution we can use a module 8 counter with synchronous RES and a combinatorial network with X1 and X0 as inputs Since the signals X1 and X0 are significant only when U1U0 = 1 they must be sampled (X1_C e X0_C) through two flip-flops when the SSN output is U1U0 = 11 The signals U1 and U0 are the decoding of the module 8 counter status according to X1_C and X0_C
The counter must be reset when U1U0 = 11
RSSCK
X1
X0
U1
U0
43
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X1_SX1
X1_S e X0_S synthesis
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X0_SX0
44
U1 and U0 truth table
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5 rArr (0 to 4hellip)
10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
X1_S and X0_S values
Cont | 00 01 11 10000 | 00110 00110 00100 00101001 | 01001 01001 01010 01010010 | 01101 01110 01100 01110011 | 01110 10001 00011 10010 100 | 00011 10110 ------ 10110101 | ------ 11010 ------ 00011 110 | ------ 00011 ------ ------111 | ------ ------ ------ ------
Status U1U0
Is this synthesis of the network safe
No beacuse the donrsquot cares could keep the network stable out of the main cycles
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
- Slide 59
- Slide 60
- Slide 61
- Slide 62
- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
Xilinx schematicS2 S1 S0 selection signals
A B C HInput signals
LDST load signal
Clock
QA QB QC QH Outputs signals
29
Barrel Shifter
LDST=1upont the first clock positive edge the ldquo10010111rdquo value is loaded into the Barrel Shifter
The different values of Si (1 3 5) cause different device rotation Obviously with 8 sigle shifts the value becomes the initial value ldquo10010111rdquo again
A further active LDST loads a new valute into the the Barrel Shifter
This new value can be rotated again according to S signals
30
This is a typical example of how erroneous is not to laquobusraquo signals a-g qa-g and S0-2 It would have been possible to use a compact decomposable binary notation much easier to interpret where all single signals can be however displayed by laquoopeningraquo the bus
EPROM
X0nZ0m
y0kY0k
Clock
D0kQ0k
FFD0k
CK
D0kQ0kCK
EPROM based synchronous networks
Nowadays instead of the EPROMs PLAs (Programmable Logical Arrays) are used that is devices where the combinatorial functions are optimized (combinatorial functions implementations are not necessarily canonical) The basic principle is however the same
31
Design with Xilinx a synchronous logical network using 374 ALU 74181 a counter and other necessary devices which implements in sequence (after a START) signal the sum of two four bits absolute numbers (A and B) then 2rsquos complements the result then exchanges the two MSBits with the two LSBits and eventually divides arythmetically the result by 2
Example
A=1100 B=0101 =gt Sum 0001 Exchange =gt 0100 (410)2rsquos complement =gt 1100 (-410)Arithmetical division (right shift) by two =gt 1110 (-210)
The solution can be decomposed in three subsystems the control and decoding unit the datapath the input and output registersi
This is the basic architecture of the central unit of any computer
The only difference is that for the computers instead of a fixed sequence of elementary operations a new different sequence is generated for each instruction which must be executed
32
Exercise
33
The synchronous network of figure must add modulo 256 the 8 bit data received in parallel on lines D[70] The sum must be updated each clock and presented on the output lines OUT[70] In case the input data is 68H the sum must not be updated and the input data discarded In addition whenever 6 significant data have been received (that is excluding 68H) the output signal F must be set for one clock period during the reception of the sixth data A reset input is also available which zeroes the outputs and resets the data count Direct design
RSS
D[70] OUT[70]
A_RES
F
Exercise
Clock
34
RSSD[70] OUT[70]
A_RES
F
DEC_68 signal synthesis
DEC(68h)D[70] DEC_68
D[70]
A_RES
CLK
OUT[70]
RSS
D[70] OUT[70]
A_RES
F
35
Modulo 256 adder
Full Adder 8 bit
D[70]
A_RES
374
D
A_RES
Q
Q
CLK
0
1
DEC_68
OE
1
OUT[70]
CIN
0
A[70]
B[70]
36
F signal synthesis
8 bit counter
A_RES
A_RES
EN
RES
CLKU2 U1 U0
DEC(5h)
F
DEC_68
F
Synchronous RESET
37
Exercise
A synchronous sequential network must monitor the data received on the 8 lines D[70] the data received are significant only if N=1 The networks must count modulo 256 how many data are divisible by 4 while EN=1 (excluding 0) The network has two more inputs THREE e RESET The signal THREE when asserted indicates that the value for increasing the count (if the data is divisible by 4) must be 3 (on the contrary if THREE is 0 the count must be increased by 1) The synchronous RESET signal overrides all other signals Direct design
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
38
SynchronousSequentialNetwork
EN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70] (Count)
An input data is divisible by 4 of its two Lsbits (I1 and I0) are zero
An 8 integrated bit register is used for the solution
CK
39
Signal DEC(0) is 1 if all input bits are 0
A signal DIV4 decodes whether the input data is divisible by 4 and NOT zero
DIV4 = I1I0DEC(0)
A signal STORE indicates that EN=1 and the input datum is divisible by 4
STORE = ENDIV4
I[70] DEC(0) DEC(0)
40
REG8BIT
ENSTORE + RESET
CK
FA8 bit
A[70]
B[70]
S[70]
CinCout
THREE
lsquo0rsquo
1
0
lsquo3rsquo
lsquo1rsquo
D[70] Z[70] U[70]
RESET
1
0
lsquo0rsquo
8 Mux21
The FA adds 1 or 3 according to signal THREE (provided the input datum is divisble by 4 and is not 0)
41
Exercise
Design a synchronous sequential network which according to two programming bits X1 and X0 generates the following four output sequences of two bits (signals U1 and U0) which end always with 11
10-01-01-10-11 if X1=0 e X0=010-01-10-01-10-10-11 if X1=0 e X0=100-10-00-11 if X1=1 e X0=001-10-10-10-10-11 if X1=1 e X0=1
The programming signals X1 and X0 are significant only when the output is 11 The network has an synchronous RESET Direct synthesis
RSSCK
X1
X0
U1
U0
42
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5rArr10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
The SSN uses a modulo N counter with N coded by the two input signals X1 e X0 (sampled when U1U0=11)
For the solution we can use a module 8 counter with synchronous RES and a combinatorial network with X1 and X0 as inputs Since the signals X1 and X0 are significant only when U1U0 = 1 they must be sampled (X1_C e X0_C) through two flip-flops when the SSN output is U1U0 = 11 The signals U1 and U0 are the decoding of the module 8 counter status according to X1_C and X0_C
The counter must be reset when U1U0 = 11
RSSCK
X1
X0
U1
U0
43
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X1_SX1
X1_S e X0_S synthesis
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X0_SX0
44
U1 and U0 truth table
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5 rArr (0 to 4hellip)
10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
X1_S and X0_S values
Cont | 00 01 11 10000 | 00110 00110 00100 00101001 | 01001 01001 01010 01010010 | 01101 01110 01100 01110011 | 01110 10001 00011 10010 100 | 00011 10110 ------ 10110101 | ------ 11010 ------ 00011 110 | ------ 00011 ------ ------111 | ------ ------ ------ ------
Status U1U0
Is this synthesis of the network safe
No beacuse the donrsquot cares could keep the network stable out of the main cycles
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
- Slide 59
- Slide 60
- Slide 61
- Slide 62
- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
Barrel Shifter
LDST=1upont the first clock positive edge the ldquo10010111rdquo value is loaded into the Barrel Shifter
The different values of Si (1 3 5) cause different device rotation Obviously with 8 sigle shifts the value becomes the initial value ldquo10010111rdquo again
A further active LDST loads a new valute into the the Barrel Shifter
This new value can be rotated again according to S signals
30
This is a typical example of how erroneous is not to laquobusraquo signals a-g qa-g and S0-2 It would have been possible to use a compact decomposable binary notation much easier to interpret where all single signals can be however displayed by laquoopeningraquo the bus
EPROM
X0nZ0m
y0kY0k
Clock
D0kQ0k
FFD0k
CK
D0kQ0kCK
EPROM based synchronous networks
Nowadays instead of the EPROMs PLAs (Programmable Logical Arrays) are used that is devices where the combinatorial functions are optimized (combinatorial functions implementations are not necessarily canonical) The basic principle is however the same
31
Design with Xilinx a synchronous logical network using 374 ALU 74181 a counter and other necessary devices which implements in sequence (after a START) signal the sum of two four bits absolute numbers (A and B) then 2rsquos complements the result then exchanges the two MSBits with the two LSBits and eventually divides arythmetically the result by 2
Example
A=1100 B=0101 =gt Sum 0001 Exchange =gt 0100 (410)2rsquos complement =gt 1100 (-410)Arithmetical division (right shift) by two =gt 1110 (-210)
The solution can be decomposed in three subsystems the control and decoding unit the datapath the input and output registersi
This is the basic architecture of the central unit of any computer
The only difference is that for the computers instead of a fixed sequence of elementary operations a new different sequence is generated for each instruction which must be executed
32
Exercise
33
The synchronous network of figure must add modulo 256 the 8 bit data received in parallel on lines D[70] The sum must be updated each clock and presented on the output lines OUT[70] In case the input data is 68H the sum must not be updated and the input data discarded In addition whenever 6 significant data have been received (that is excluding 68H) the output signal F must be set for one clock period during the reception of the sixth data A reset input is also available which zeroes the outputs and resets the data count Direct design
RSS
D[70] OUT[70]
A_RES
F
Exercise
Clock
34
RSSD[70] OUT[70]
A_RES
F
DEC_68 signal synthesis
DEC(68h)D[70] DEC_68
D[70]
A_RES
CLK
OUT[70]
RSS
D[70] OUT[70]
A_RES
F
35
Modulo 256 adder
Full Adder 8 bit
D[70]
A_RES
374
D
A_RES
Q
Q
CLK
0
1
DEC_68
OE
1
OUT[70]
CIN
0
A[70]
B[70]
36
F signal synthesis
8 bit counter
A_RES
A_RES
EN
RES
CLKU2 U1 U0
DEC(5h)
F
DEC_68
F
Synchronous RESET
37
Exercise
A synchronous sequential network must monitor the data received on the 8 lines D[70] the data received are significant only if N=1 The networks must count modulo 256 how many data are divisible by 4 while EN=1 (excluding 0) The network has two more inputs THREE e RESET The signal THREE when asserted indicates that the value for increasing the count (if the data is divisible by 4) must be 3 (on the contrary if THREE is 0 the count must be increased by 1) The synchronous RESET signal overrides all other signals Direct design
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
38
SynchronousSequentialNetwork
EN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70] (Count)
An input data is divisible by 4 of its two Lsbits (I1 and I0) are zero
An 8 integrated bit register is used for the solution
CK
39
Signal DEC(0) is 1 if all input bits are 0
A signal DIV4 decodes whether the input data is divisible by 4 and NOT zero
DIV4 = I1I0DEC(0)
A signal STORE indicates that EN=1 and the input datum is divisible by 4
STORE = ENDIV4
I[70] DEC(0) DEC(0)
40
REG8BIT
ENSTORE + RESET
CK
FA8 bit
A[70]
B[70]
S[70]
CinCout
THREE
lsquo0rsquo
1
0
lsquo3rsquo
lsquo1rsquo
D[70] Z[70] U[70]
RESET
1
0
lsquo0rsquo
8 Mux21
The FA adds 1 or 3 according to signal THREE (provided the input datum is divisble by 4 and is not 0)
41
Exercise
Design a synchronous sequential network which according to two programming bits X1 and X0 generates the following four output sequences of two bits (signals U1 and U0) which end always with 11
10-01-01-10-11 if X1=0 e X0=010-01-10-01-10-10-11 if X1=0 e X0=100-10-00-11 if X1=1 e X0=001-10-10-10-10-11 if X1=1 e X0=1
The programming signals X1 and X0 are significant only when the output is 11 The network has an synchronous RESET Direct synthesis
RSSCK
X1
X0
U1
U0
42
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5rArr10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
The SSN uses a modulo N counter with N coded by the two input signals X1 e X0 (sampled when U1U0=11)
For the solution we can use a module 8 counter with synchronous RES and a combinatorial network with X1 and X0 as inputs Since the signals X1 and X0 are significant only when U1U0 = 1 they must be sampled (X1_C e X0_C) through two flip-flops when the SSN output is U1U0 = 11 The signals U1 and U0 are the decoding of the module 8 counter status according to X1_C and X0_C
The counter must be reset when U1U0 = 11
RSSCK
X1
X0
U1
U0
43
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X1_SX1
X1_S e X0_S synthesis
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X0_SX0
44
U1 and U0 truth table
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5 rArr (0 to 4hellip)
10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
X1_S and X0_S values
Cont | 00 01 11 10000 | 00110 00110 00100 00101001 | 01001 01001 01010 01010010 | 01101 01110 01100 01110011 | 01110 10001 00011 10010 100 | 00011 10110 ------ 10110101 | ------ 11010 ------ 00011 110 | ------ 00011 ------ ------111 | ------ ------ ------ ------
Status U1U0
Is this synthesis of the network safe
No beacuse the donrsquot cares could keep the network stable out of the main cycles
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
- Slide 59
- Slide 60
- Slide 61
- Slide 62
- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
EPROM
X0nZ0m
y0kY0k
Clock
D0kQ0k
FFD0k
CK
D0kQ0kCK
EPROM based synchronous networks
Nowadays instead of the EPROMs PLAs (Programmable Logical Arrays) are used that is devices where the combinatorial functions are optimized (combinatorial functions implementations are not necessarily canonical) The basic principle is however the same
31
Design with Xilinx a synchronous logical network using 374 ALU 74181 a counter and other necessary devices which implements in sequence (after a START) signal the sum of two four bits absolute numbers (A and B) then 2rsquos complements the result then exchanges the two MSBits with the two LSBits and eventually divides arythmetically the result by 2
Example
A=1100 B=0101 =gt Sum 0001 Exchange =gt 0100 (410)2rsquos complement =gt 1100 (-410)Arithmetical division (right shift) by two =gt 1110 (-210)
The solution can be decomposed in three subsystems the control and decoding unit the datapath the input and output registersi
This is the basic architecture of the central unit of any computer
The only difference is that for the computers instead of a fixed sequence of elementary operations a new different sequence is generated for each instruction which must be executed
32
Exercise
33
The synchronous network of figure must add modulo 256 the 8 bit data received in parallel on lines D[70] The sum must be updated each clock and presented on the output lines OUT[70] In case the input data is 68H the sum must not be updated and the input data discarded In addition whenever 6 significant data have been received (that is excluding 68H) the output signal F must be set for one clock period during the reception of the sixth data A reset input is also available which zeroes the outputs and resets the data count Direct design
RSS
D[70] OUT[70]
A_RES
F
Exercise
Clock
34
RSSD[70] OUT[70]
A_RES
F
DEC_68 signal synthesis
DEC(68h)D[70] DEC_68
D[70]
A_RES
CLK
OUT[70]
RSS
D[70] OUT[70]
A_RES
F
35
Modulo 256 adder
Full Adder 8 bit
D[70]
A_RES
374
D
A_RES
Q
Q
CLK
0
1
DEC_68
OE
1
OUT[70]
CIN
0
A[70]
B[70]
36
F signal synthesis
8 bit counter
A_RES
A_RES
EN
RES
CLKU2 U1 U0
DEC(5h)
F
DEC_68
F
Synchronous RESET
37
Exercise
A synchronous sequential network must monitor the data received on the 8 lines D[70] the data received are significant only if N=1 The networks must count modulo 256 how many data are divisible by 4 while EN=1 (excluding 0) The network has two more inputs THREE e RESET The signal THREE when asserted indicates that the value for increasing the count (if the data is divisible by 4) must be 3 (on the contrary if THREE is 0 the count must be increased by 1) The synchronous RESET signal overrides all other signals Direct design
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
38
SynchronousSequentialNetwork
EN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70] (Count)
An input data is divisible by 4 of its two Lsbits (I1 and I0) are zero
An 8 integrated bit register is used for the solution
CK
39
Signal DEC(0) is 1 if all input bits are 0
A signal DIV4 decodes whether the input data is divisible by 4 and NOT zero
DIV4 = I1I0DEC(0)
A signal STORE indicates that EN=1 and the input datum is divisible by 4
STORE = ENDIV4
I[70] DEC(0) DEC(0)
40
REG8BIT
ENSTORE + RESET
CK
FA8 bit
A[70]
B[70]
S[70]
CinCout
THREE
lsquo0rsquo
1
0
lsquo3rsquo
lsquo1rsquo
D[70] Z[70] U[70]
RESET
1
0
lsquo0rsquo
8 Mux21
The FA adds 1 or 3 according to signal THREE (provided the input datum is divisble by 4 and is not 0)
41
Exercise
Design a synchronous sequential network which according to two programming bits X1 and X0 generates the following four output sequences of two bits (signals U1 and U0) which end always with 11
10-01-01-10-11 if X1=0 e X0=010-01-10-01-10-10-11 if X1=0 e X0=100-10-00-11 if X1=1 e X0=001-10-10-10-10-11 if X1=1 e X0=1
The programming signals X1 and X0 are significant only when the output is 11 The network has an synchronous RESET Direct synthesis
RSSCK
X1
X0
U1
U0
42
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5rArr10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
The SSN uses a modulo N counter with N coded by the two input signals X1 e X0 (sampled when U1U0=11)
For the solution we can use a module 8 counter with synchronous RES and a combinatorial network with X1 and X0 as inputs Since the signals X1 and X0 are significant only when U1U0 = 1 they must be sampled (X1_C e X0_C) through two flip-flops when the SSN output is U1U0 = 11 The signals U1 and U0 are the decoding of the module 8 counter status according to X1_C and X0_C
The counter must be reset when U1U0 = 11
RSSCK
X1
X0
U1
U0
43
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X1_SX1
X1_S e X0_S synthesis
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X0_SX0
44
U1 and U0 truth table
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5 rArr (0 to 4hellip)
10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
X1_S and X0_S values
Cont | 00 01 11 10000 | 00110 00110 00100 00101001 | 01001 01001 01010 01010010 | 01101 01110 01100 01110011 | 01110 10001 00011 10010 100 | 00011 10110 ------ 10110101 | ------ 11010 ------ 00011 110 | ------ 00011 ------ ------111 | ------ ------ ------ ------
Status U1U0
Is this synthesis of the network safe
No beacuse the donrsquot cares could keep the network stable out of the main cycles
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
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- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
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- Slide 44
- Slide 45
- Slide 46
- Slide 47
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- Slide 49
- Slide 50
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- Slide 60
- Slide 61
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- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
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- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
Design with Xilinx a synchronous logical network using 374 ALU 74181 a counter and other necessary devices which implements in sequence (after a START) signal the sum of two four bits absolute numbers (A and B) then 2rsquos complements the result then exchanges the two MSBits with the two LSBits and eventually divides arythmetically the result by 2
Example
A=1100 B=0101 =gt Sum 0001 Exchange =gt 0100 (410)2rsquos complement =gt 1100 (-410)Arithmetical division (right shift) by two =gt 1110 (-210)
The solution can be decomposed in three subsystems the control and decoding unit the datapath the input and output registersi
This is the basic architecture of the central unit of any computer
The only difference is that for the computers instead of a fixed sequence of elementary operations a new different sequence is generated for each instruction which must be executed
32
Exercise
33
The synchronous network of figure must add modulo 256 the 8 bit data received in parallel on lines D[70] The sum must be updated each clock and presented on the output lines OUT[70] In case the input data is 68H the sum must not be updated and the input data discarded In addition whenever 6 significant data have been received (that is excluding 68H) the output signal F must be set for one clock period during the reception of the sixth data A reset input is also available which zeroes the outputs and resets the data count Direct design
RSS
D[70] OUT[70]
A_RES
F
Exercise
Clock
34
RSSD[70] OUT[70]
A_RES
F
DEC_68 signal synthesis
DEC(68h)D[70] DEC_68
D[70]
A_RES
CLK
OUT[70]
RSS
D[70] OUT[70]
A_RES
F
35
Modulo 256 adder
Full Adder 8 bit
D[70]
A_RES
374
D
A_RES
Q
Q
CLK
0
1
DEC_68
OE
1
OUT[70]
CIN
0
A[70]
B[70]
36
F signal synthesis
8 bit counter
A_RES
A_RES
EN
RES
CLKU2 U1 U0
DEC(5h)
F
DEC_68
F
Synchronous RESET
37
Exercise
A synchronous sequential network must monitor the data received on the 8 lines D[70] the data received are significant only if N=1 The networks must count modulo 256 how many data are divisible by 4 while EN=1 (excluding 0) The network has two more inputs THREE e RESET The signal THREE when asserted indicates that the value for increasing the count (if the data is divisible by 4) must be 3 (on the contrary if THREE is 0 the count must be increased by 1) The synchronous RESET signal overrides all other signals Direct design
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
38
SynchronousSequentialNetwork
EN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70] (Count)
An input data is divisible by 4 of its two Lsbits (I1 and I0) are zero
An 8 integrated bit register is used for the solution
CK
39
Signal DEC(0) is 1 if all input bits are 0
A signal DIV4 decodes whether the input data is divisible by 4 and NOT zero
DIV4 = I1I0DEC(0)
A signal STORE indicates that EN=1 and the input datum is divisible by 4
STORE = ENDIV4
I[70] DEC(0) DEC(0)
40
REG8BIT
ENSTORE + RESET
CK
FA8 bit
A[70]
B[70]
S[70]
CinCout
THREE
lsquo0rsquo
1
0
lsquo3rsquo
lsquo1rsquo
D[70] Z[70] U[70]
RESET
1
0
lsquo0rsquo
8 Mux21
The FA adds 1 or 3 according to signal THREE (provided the input datum is divisble by 4 and is not 0)
41
Exercise
Design a synchronous sequential network which according to two programming bits X1 and X0 generates the following four output sequences of two bits (signals U1 and U0) which end always with 11
10-01-01-10-11 if X1=0 e X0=010-01-10-01-10-10-11 if X1=0 e X0=100-10-00-11 if X1=1 e X0=001-10-10-10-10-11 if X1=1 e X0=1
The programming signals X1 and X0 are significant only when the output is 11 The network has an synchronous RESET Direct synthesis
RSSCK
X1
X0
U1
U0
42
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5rArr10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
The SSN uses a modulo N counter with N coded by the two input signals X1 e X0 (sampled when U1U0=11)
For the solution we can use a module 8 counter with synchronous RES and a combinatorial network with X1 and X0 as inputs Since the signals X1 and X0 are significant only when U1U0 = 1 they must be sampled (X1_C e X0_C) through two flip-flops when the SSN output is U1U0 = 11 The signals U1 and U0 are the decoding of the module 8 counter status according to X1_C and X0_C
The counter must be reset when U1U0 = 11
RSSCK
X1
X0
U1
U0
43
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X1_SX1
X1_S e X0_S synthesis
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X0_SX0
44
U1 and U0 truth table
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5 rArr (0 to 4hellip)
10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
X1_S and X0_S values
Cont | 00 01 11 10000 | 00110 00110 00100 00101001 | 01001 01001 01010 01010010 | 01101 01110 01100 01110011 | 01110 10001 00011 10010 100 | 00011 10110 ------ 10110101 | ------ 11010 ------ 00011 110 | ------ 00011 ------ ------111 | ------ ------ ------ ------
Status U1U0
Is this synthesis of the network safe
No beacuse the donrsquot cares could keep the network stable out of the main cycles
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
- Slide 59
- Slide 60
- Slide 61
- Slide 62
- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
33
The synchronous network of figure must add modulo 256 the 8 bit data received in parallel on lines D[70] The sum must be updated each clock and presented on the output lines OUT[70] In case the input data is 68H the sum must not be updated and the input data discarded In addition whenever 6 significant data have been received (that is excluding 68H) the output signal F must be set for one clock period during the reception of the sixth data A reset input is also available which zeroes the outputs and resets the data count Direct design
RSS
D[70] OUT[70]
A_RES
F
Exercise
Clock
34
RSSD[70] OUT[70]
A_RES
F
DEC_68 signal synthesis
DEC(68h)D[70] DEC_68
D[70]
A_RES
CLK
OUT[70]
RSS
D[70] OUT[70]
A_RES
F
35
Modulo 256 adder
Full Adder 8 bit
D[70]
A_RES
374
D
A_RES
Q
Q
CLK
0
1
DEC_68
OE
1
OUT[70]
CIN
0
A[70]
B[70]
36
F signal synthesis
8 bit counter
A_RES
A_RES
EN
RES
CLKU2 U1 U0
DEC(5h)
F
DEC_68
F
Synchronous RESET
37
Exercise
A synchronous sequential network must monitor the data received on the 8 lines D[70] the data received are significant only if N=1 The networks must count modulo 256 how many data are divisible by 4 while EN=1 (excluding 0) The network has two more inputs THREE e RESET The signal THREE when asserted indicates that the value for increasing the count (if the data is divisible by 4) must be 3 (on the contrary if THREE is 0 the count must be increased by 1) The synchronous RESET signal overrides all other signals Direct design
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
38
SynchronousSequentialNetwork
EN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70] (Count)
An input data is divisible by 4 of its two Lsbits (I1 and I0) are zero
An 8 integrated bit register is used for the solution
CK
39
Signal DEC(0) is 1 if all input bits are 0
A signal DIV4 decodes whether the input data is divisible by 4 and NOT zero
DIV4 = I1I0DEC(0)
A signal STORE indicates that EN=1 and the input datum is divisible by 4
STORE = ENDIV4
I[70] DEC(0) DEC(0)
40
REG8BIT
ENSTORE + RESET
CK
FA8 bit
A[70]
B[70]
S[70]
CinCout
THREE
lsquo0rsquo
1
0
lsquo3rsquo
lsquo1rsquo
D[70] Z[70] U[70]
RESET
1
0
lsquo0rsquo
8 Mux21
The FA adds 1 or 3 according to signal THREE (provided the input datum is divisble by 4 and is not 0)
41
Exercise
Design a synchronous sequential network which according to two programming bits X1 and X0 generates the following four output sequences of two bits (signals U1 and U0) which end always with 11
10-01-01-10-11 if X1=0 e X0=010-01-10-01-10-10-11 if X1=0 e X0=100-10-00-11 if X1=1 e X0=001-10-10-10-10-11 if X1=1 e X0=1
The programming signals X1 and X0 are significant only when the output is 11 The network has an synchronous RESET Direct synthesis
RSSCK
X1
X0
U1
U0
42
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5rArr10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
The SSN uses a modulo N counter with N coded by the two input signals X1 e X0 (sampled when U1U0=11)
For the solution we can use a module 8 counter with synchronous RES and a combinatorial network with X1 and X0 as inputs Since the signals X1 and X0 are significant only when U1U0 = 1 they must be sampled (X1_C e X0_C) through two flip-flops when the SSN output is U1U0 = 11 The signals U1 and U0 are the decoding of the module 8 counter status according to X1_C and X0_C
The counter must be reset when U1U0 = 11
RSSCK
X1
X0
U1
U0
43
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X1_SX1
X1_S e X0_S synthesis
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X0_SX0
44
U1 and U0 truth table
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5 rArr (0 to 4hellip)
10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
X1_S and X0_S values
Cont | 00 01 11 10000 | 00110 00110 00100 00101001 | 01001 01001 01010 01010010 | 01101 01110 01100 01110011 | 01110 10001 00011 10010 100 | 00011 10110 ------ 10110101 | ------ 11010 ------ 00011 110 | ------ 00011 ------ ------111 | ------ ------ ------ ------
Status U1U0
Is this synthesis of the network safe
No beacuse the donrsquot cares could keep the network stable out of the main cycles
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
- Slide 59
- Slide 60
- Slide 61
- Slide 62
- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
34
RSSD[70] OUT[70]
A_RES
F
DEC_68 signal synthesis
DEC(68h)D[70] DEC_68
D[70]
A_RES
CLK
OUT[70]
RSS
D[70] OUT[70]
A_RES
F
35
Modulo 256 adder
Full Adder 8 bit
D[70]
A_RES
374
D
A_RES
Q
Q
CLK
0
1
DEC_68
OE
1
OUT[70]
CIN
0
A[70]
B[70]
36
F signal synthesis
8 bit counter
A_RES
A_RES
EN
RES
CLKU2 U1 U0
DEC(5h)
F
DEC_68
F
Synchronous RESET
37
Exercise
A synchronous sequential network must monitor the data received on the 8 lines D[70] the data received are significant only if N=1 The networks must count modulo 256 how many data are divisible by 4 while EN=1 (excluding 0) The network has two more inputs THREE e RESET The signal THREE when asserted indicates that the value for increasing the count (if the data is divisible by 4) must be 3 (on the contrary if THREE is 0 the count must be increased by 1) The synchronous RESET signal overrides all other signals Direct design
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
38
SynchronousSequentialNetwork
EN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70] (Count)
An input data is divisible by 4 of its two Lsbits (I1 and I0) are zero
An 8 integrated bit register is used for the solution
CK
39
Signal DEC(0) is 1 if all input bits are 0
A signal DIV4 decodes whether the input data is divisible by 4 and NOT zero
DIV4 = I1I0DEC(0)
A signal STORE indicates that EN=1 and the input datum is divisible by 4
STORE = ENDIV4
I[70] DEC(0) DEC(0)
40
REG8BIT
ENSTORE + RESET
CK
FA8 bit
A[70]
B[70]
S[70]
CinCout
THREE
lsquo0rsquo
1
0
lsquo3rsquo
lsquo1rsquo
D[70] Z[70] U[70]
RESET
1
0
lsquo0rsquo
8 Mux21
The FA adds 1 or 3 according to signal THREE (provided the input datum is divisble by 4 and is not 0)
41
Exercise
Design a synchronous sequential network which according to two programming bits X1 and X0 generates the following four output sequences of two bits (signals U1 and U0) which end always with 11
10-01-01-10-11 if X1=0 e X0=010-01-10-01-10-10-11 if X1=0 e X0=100-10-00-11 if X1=1 e X0=001-10-10-10-10-11 if X1=1 e X0=1
The programming signals X1 and X0 are significant only when the output is 11 The network has an synchronous RESET Direct synthesis
RSSCK
X1
X0
U1
U0
42
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5rArr10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
The SSN uses a modulo N counter with N coded by the two input signals X1 e X0 (sampled when U1U0=11)
For the solution we can use a module 8 counter with synchronous RES and a combinatorial network with X1 and X0 as inputs Since the signals X1 and X0 are significant only when U1U0 = 1 they must be sampled (X1_C e X0_C) through two flip-flops when the SSN output is U1U0 = 11 The signals U1 and U0 are the decoding of the module 8 counter status according to X1_C and X0_C
The counter must be reset when U1U0 = 11
RSSCK
X1
X0
U1
U0
43
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X1_SX1
X1_S e X0_S synthesis
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X0_SX0
44
U1 and U0 truth table
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5 rArr (0 to 4hellip)
10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
X1_S and X0_S values
Cont | 00 01 11 10000 | 00110 00110 00100 00101001 | 01001 01001 01010 01010010 | 01101 01110 01100 01110011 | 01110 10001 00011 10010 100 | 00011 10110 ------ 10110101 | ------ 11010 ------ 00011 110 | ------ 00011 ------ ------111 | ------ ------ ------ ------
Status U1U0
Is this synthesis of the network safe
No beacuse the donrsquot cares could keep the network stable out of the main cycles
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
- Slide 59
- Slide 60
- Slide 61
- Slide 62
- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
35
Modulo 256 adder
Full Adder 8 bit
D[70]
A_RES
374
D
A_RES
Q
Q
CLK
0
1
DEC_68
OE
1
OUT[70]
CIN
0
A[70]
B[70]
36
F signal synthesis
8 bit counter
A_RES
A_RES
EN
RES
CLKU2 U1 U0
DEC(5h)
F
DEC_68
F
Synchronous RESET
37
Exercise
A synchronous sequential network must monitor the data received on the 8 lines D[70] the data received are significant only if N=1 The networks must count modulo 256 how many data are divisible by 4 while EN=1 (excluding 0) The network has two more inputs THREE e RESET The signal THREE when asserted indicates that the value for increasing the count (if the data is divisible by 4) must be 3 (on the contrary if THREE is 0 the count must be increased by 1) The synchronous RESET signal overrides all other signals Direct design
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
38
SynchronousSequentialNetwork
EN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70] (Count)
An input data is divisible by 4 of its two Lsbits (I1 and I0) are zero
An 8 integrated bit register is used for the solution
CK
39
Signal DEC(0) is 1 if all input bits are 0
A signal DIV4 decodes whether the input data is divisible by 4 and NOT zero
DIV4 = I1I0DEC(0)
A signal STORE indicates that EN=1 and the input datum is divisible by 4
STORE = ENDIV4
I[70] DEC(0) DEC(0)
40
REG8BIT
ENSTORE + RESET
CK
FA8 bit
A[70]
B[70]
S[70]
CinCout
THREE
lsquo0rsquo
1
0
lsquo3rsquo
lsquo1rsquo
D[70] Z[70] U[70]
RESET
1
0
lsquo0rsquo
8 Mux21
The FA adds 1 or 3 according to signal THREE (provided the input datum is divisble by 4 and is not 0)
41
Exercise
Design a synchronous sequential network which according to two programming bits X1 and X0 generates the following four output sequences of two bits (signals U1 and U0) which end always with 11
10-01-01-10-11 if X1=0 e X0=010-01-10-01-10-10-11 if X1=0 e X0=100-10-00-11 if X1=1 e X0=001-10-10-10-10-11 if X1=1 e X0=1
The programming signals X1 and X0 are significant only when the output is 11 The network has an synchronous RESET Direct synthesis
RSSCK
X1
X0
U1
U0
42
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5rArr10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
The SSN uses a modulo N counter with N coded by the two input signals X1 e X0 (sampled when U1U0=11)
For the solution we can use a module 8 counter with synchronous RES and a combinatorial network with X1 and X0 as inputs Since the signals X1 and X0 are significant only when U1U0 = 1 they must be sampled (X1_C e X0_C) through two flip-flops when the SSN output is U1U0 = 11 The signals U1 and U0 are the decoding of the module 8 counter status according to X1_C and X0_C
The counter must be reset when U1U0 = 11
RSSCK
X1
X0
U1
U0
43
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X1_SX1
X1_S e X0_S synthesis
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X0_SX0
44
U1 and U0 truth table
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5 rArr (0 to 4hellip)
10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
X1_S and X0_S values
Cont | 00 01 11 10000 | 00110 00110 00100 00101001 | 01001 01001 01010 01010010 | 01101 01110 01100 01110011 | 01110 10001 00011 10010 100 | 00011 10110 ------ 10110101 | ------ 11010 ------ 00011 110 | ------ 00011 ------ ------111 | ------ ------ ------ ------
Status U1U0
Is this synthesis of the network safe
No beacuse the donrsquot cares could keep the network stable out of the main cycles
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
- Slide 59
- Slide 60
- Slide 61
- Slide 62
- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
36
F signal synthesis
8 bit counter
A_RES
A_RES
EN
RES
CLKU2 U1 U0
DEC(5h)
F
DEC_68
F
Synchronous RESET
37
Exercise
A synchronous sequential network must monitor the data received on the 8 lines D[70] the data received are significant only if N=1 The networks must count modulo 256 how many data are divisible by 4 while EN=1 (excluding 0) The network has two more inputs THREE e RESET The signal THREE when asserted indicates that the value for increasing the count (if the data is divisible by 4) must be 3 (on the contrary if THREE is 0 the count must be increased by 1) The synchronous RESET signal overrides all other signals Direct design
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
38
SynchronousSequentialNetwork
EN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70] (Count)
An input data is divisible by 4 of its two Lsbits (I1 and I0) are zero
An 8 integrated bit register is used for the solution
CK
39
Signal DEC(0) is 1 if all input bits are 0
A signal DIV4 decodes whether the input data is divisible by 4 and NOT zero
DIV4 = I1I0DEC(0)
A signal STORE indicates that EN=1 and the input datum is divisible by 4
STORE = ENDIV4
I[70] DEC(0) DEC(0)
40
REG8BIT
ENSTORE + RESET
CK
FA8 bit
A[70]
B[70]
S[70]
CinCout
THREE
lsquo0rsquo
1
0
lsquo3rsquo
lsquo1rsquo
D[70] Z[70] U[70]
RESET
1
0
lsquo0rsquo
8 Mux21
The FA adds 1 or 3 according to signal THREE (provided the input datum is divisble by 4 and is not 0)
41
Exercise
Design a synchronous sequential network which according to two programming bits X1 and X0 generates the following four output sequences of two bits (signals U1 and U0) which end always with 11
10-01-01-10-11 if X1=0 e X0=010-01-10-01-10-10-11 if X1=0 e X0=100-10-00-11 if X1=1 e X0=001-10-10-10-10-11 if X1=1 e X0=1
The programming signals X1 and X0 are significant only when the output is 11 The network has an synchronous RESET Direct synthesis
RSSCK
X1
X0
U1
U0
42
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5rArr10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
The SSN uses a modulo N counter with N coded by the two input signals X1 e X0 (sampled when U1U0=11)
For the solution we can use a module 8 counter with synchronous RES and a combinatorial network with X1 and X0 as inputs Since the signals X1 and X0 are significant only when U1U0 = 1 they must be sampled (X1_C e X0_C) through two flip-flops when the SSN output is U1U0 = 11 The signals U1 and U0 are the decoding of the module 8 counter status according to X1_C and X0_C
The counter must be reset when U1U0 = 11
RSSCK
X1
X0
U1
U0
43
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X1_SX1
X1_S e X0_S synthesis
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X0_SX0
44
U1 and U0 truth table
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5 rArr (0 to 4hellip)
10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
X1_S and X0_S values
Cont | 00 01 11 10000 | 00110 00110 00100 00101001 | 01001 01001 01010 01010010 | 01101 01110 01100 01110011 | 01110 10001 00011 10010 100 | 00011 10110 ------ 10110101 | ------ 11010 ------ 00011 110 | ------ 00011 ------ ------111 | ------ ------ ------ ------
Status U1U0
Is this synthesis of the network safe
No beacuse the donrsquot cares could keep the network stable out of the main cycles
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
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- Slide 10
- Slide 11
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- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
- Slide 59
- Slide 60
- Slide 61
- Slide 62
- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
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- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
37
Exercise
A synchronous sequential network must monitor the data received on the 8 lines D[70] the data received are significant only if N=1 The networks must count modulo 256 how many data are divisible by 4 while EN=1 (excluding 0) The network has two more inputs THREE e RESET The signal THREE when asserted indicates that the value for increasing the count (if the data is divisible by 4) must be 3 (on the contrary if THREE is 0 the count must be increased by 1) The synchronous RESET signal overrides all other signals Direct design
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
RSSEN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70]
38
SynchronousSequentialNetwork
EN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70] (Count)
An input data is divisible by 4 of its two Lsbits (I1 and I0) are zero
An 8 integrated bit register is used for the solution
CK
39
Signal DEC(0) is 1 if all input bits are 0
A signal DIV4 decodes whether the input data is divisible by 4 and NOT zero
DIV4 = I1I0DEC(0)
A signal STORE indicates that EN=1 and the input datum is divisible by 4
STORE = ENDIV4
I[70] DEC(0) DEC(0)
40
REG8BIT
ENSTORE + RESET
CK
FA8 bit
A[70]
B[70]
S[70]
CinCout
THREE
lsquo0rsquo
1
0
lsquo3rsquo
lsquo1rsquo
D[70] Z[70] U[70]
RESET
1
0
lsquo0rsquo
8 Mux21
The FA adds 1 or 3 according to signal THREE (provided the input datum is divisble by 4 and is not 0)
41
Exercise
Design a synchronous sequential network which according to two programming bits X1 and X0 generates the following four output sequences of two bits (signals U1 and U0) which end always with 11
10-01-01-10-11 if X1=0 e X0=010-01-10-01-10-10-11 if X1=0 e X0=100-10-00-11 if X1=1 e X0=001-10-10-10-10-11 if X1=1 e X0=1
The programming signals X1 and X0 are significant only when the output is 11 The network has an synchronous RESET Direct synthesis
RSSCK
X1
X0
U1
U0
42
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5rArr10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
The SSN uses a modulo N counter with N coded by the two input signals X1 e X0 (sampled when U1U0=11)
For the solution we can use a module 8 counter with synchronous RES and a combinatorial network with X1 and X0 as inputs Since the signals X1 and X0 are significant only when U1U0 = 1 they must be sampled (X1_C e X0_C) through two flip-flops when the SSN output is U1U0 = 11 The signals U1 and U0 are the decoding of the module 8 counter status according to X1_C and X0_C
The counter must be reset when U1U0 = 11
RSSCK
X1
X0
U1
U0
43
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X1_SX1
X1_S e X0_S synthesis
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X0_SX0
44
U1 and U0 truth table
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5 rArr (0 to 4hellip)
10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
X1_S and X0_S values
Cont | 00 01 11 10000 | 00110 00110 00100 00101001 | 01001 01001 01010 01010010 | 01101 01110 01100 01110011 | 01110 10001 00011 10010 100 | 00011 10110 ------ 10110101 | ------ 11010 ------ 00011 110 | ------ 00011 ------ ------111 | ------ ------ ------ ------
Status U1U0
Is this synthesis of the network safe
No beacuse the donrsquot cares could keep the network stable out of the main cycles
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
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- Slide 10
- Slide 11
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- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
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- Slide 39
- Slide 40
- Slide 41
- Slide 42
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- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
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- Slide 53
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- Slide 56
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- Slide 61
- Slide 62
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- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
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- Slide 75
- Slide 76
- Slide 77
- Slide 78
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- Slide 85
- Slide 86
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- Slide 88
-
38
SynchronousSequentialNetwork
EN
U[70]
RESET
THREE
I[70]
EN
RESET
THREE
I[70] U[70] (Count)
An input data is divisible by 4 of its two Lsbits (I1 and I0) are zero
An 8 integrated bit register is used for the solution
CK
39
Signal DEC(0) is 1 if all input bits are 0
A signal DIV4 decodes whether the input data is divisible by 4 and NOT zero
DIV4 = I1I0DEC(0)
A signal STORE indicates that EN=1 and the input datum is divisible by 4
STORE = ENDIV4
I[70] DEC(0) DEC(0)
40
REG8BIT
ENSTORE + RESET
CK
FA8 bit
A[70]
B[70]
S[70]
CinCout
THREE
lsquo0rsquo
1
0
lsquo3rsquo
lsquo1rsquo
D[70] Z[70] U[70]
RESET
1
0
lsquo0rsquo
8 Mux21
The FA adds 1 or 3 according to signal THREE (provided the input datum is divisble by 4 and is not 0)
41
Exercise
Design a synchronous sequential network which according to two programming bits X1 and X0 generates the following four output sequences of two bits (signals U1 and U0) which end always with 11
10-01-01-10-11 if X1=0 e X0=010-01-10-01-10-10-11 if X1=0 e X0=100-10-00-11 if X1=1 e X0=001-10-10-10-10-11 if X1=1 e X0=1
The programming signals X1 and X0 are significant only when the output is 11 The network has an synchronous RESET Direct synthesis
RSSCK
X1
X0
U1
U0
42
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5rArr10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
The SSN uses a modulo N counter with N coded by the two input signals X1 e X0 (sampled when U1U0=11)
For the solution we can use a module 8 counter with synchronous RES and a combinatorial network with X1 and X0 as inputs Since the signals X1 and X0 are significant only when U1U0 = 1 they must be sampled (X1_C e X0_C) through two flip-flops when the SSN output is U1U0 = 11 The signals U1 and U0 are the decoding of the module 8 counter status according to X1_C and X0_C
The counter must be reset when U1U0 = 11
RSSCK
X1
X0
U1
U0
43
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X1_SX1
X1_S e X0_S synthesis
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X0_SX0
44
U1 and U0 truth table
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5 rArr (0 to 4hellip)
10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
X1_S and X0_S values
Cont | 00 01 11 10000 | 00110 00110 00100 00101001 | 01001 01001 01010 01010010 | 01101 01110 01100 01110011 | 01110 10001 00011 10010 100 | 00011 10110 ------ 10110101 | ------ 11010 ------ 00011 110 | ------ 00011 ------ ------111 | ------ ------ ------ ------
Status U1U0
Is this synthesis of the network safe
No beacuse the donrsquot cares could keep the network stable out of the main cycles
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
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- Slide 14
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- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
- Slide 59
- Slide 60
- Slide 61
- Slide 62
- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
39
Signal DEC(0) is 1 if all input bits are 0
A signal DIV4 decodes whether the input data is divisible by 4 and NOT zero
DIV4 = I1I0DEC(0)
A signal STORE indicates that EN=1 and the input datum is divisible by 4
STORE = ENDIV4
I[70] DEC(0) DEC(0)
40
REG8BIT
ENSTORE + RESET
CK
FA8 bit
A[70]
B[70]
S[70]
CinCout
THREE
lsquo0rsquo
1
0
lsquo3rsquo
lsquo1rsquo
D[70] Z[70] U[70]
RESET
1
0
lsquo0rsquo
8 Mux21
The FA adds 1 or 3 according to signal THREE (provided the input datum is divisble by 4 and is not 0)
41
Exercise
Design a synchronous sequential network which according to two programming bits X1 and X0 generates the following four output sequences of two bits (signals U1 and U0) which end always with 11
10-01-01-10-11 if X1=0 e X0=010-01-10-01-10-10-11 if X1=0 e X0=100-10-00-11 if X1=1 e X0=001-10-10-10-10-11 if X1=1 e X0=1
The programming signals X1 and X0 are significant only when the output is 11 The network has an synchronous RESET Direct synthesis
RSSCK
X1
X0
U1
U0
42
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5rArr10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
The SSN uses a modulo N counter with N coded by the two input signals X1 e X0 (sampled when U1U0=11)
For the solution we can use a module 8 counter with synchronous RES and a combinatorial network with X1 and X0 as inputs Since the signals X1 and X0 are significant only when U1U0 = 1 they must be sampled (X1_C e X0_C) through two flip-flops when the SSN output is U1U0 = 11 The signals U1 and U0 are the decoding of the module 8 counter status according to X1_C and X0_C
The counter must be reset when U1U0 = 11
RSSCK
X1
X0
U1
U0
43
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X1_SX1
X1_S e X0_S synthesis
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X0_SX0
44
U1 and U0 truth table
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5 rArr (0 to 4hellip)
10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
X1_S and X0_S values
Cont | 00 01 11 10000 | 00110 00110 00100 00101001 | 01001 01001 01010 01010010 | 01101 01110 01100 01110011 | 01110 10001 00011 10010 100 | 00011 10110 ------ 10110101 | ------ 11010 ------ 00011 110 | ------ 00011 ------ ------111 | ------ ------ ------ ------
Status U1U0
Is this synthesis of the network safe
No beacuse the donrsquot cares could keep the network stable out of the main cycles
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
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- Slide 7
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- Slide 10
- Slide 11
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- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
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- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
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- Slide 42
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- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
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- Slide 53
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- Slide 55
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- Slide 61
- Slide 62
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- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
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- Slide 73
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- Slide 75
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- Slide 78
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- Slide 84
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- Slide 86
- Slide 87
- Slide 88
-
40
REG8BIT
ENSTORE + RESET
CK
FA8 bit
A[70]
B[70]
S[70]
CinCout
THREE
lsquo0rsquo
1
0
lsquo3rsquo
lsquo1rsquo
D[70] Z[70] U[70]
RESET
1
0
lsquo0rsquo
8 Mux21
The FA adds 1 or 3 according to signal THREE (provided the input datum is divisble by 4 and is not 0)
41
Exercise
Design a synchronous sequential network which according to two programming bits X1 and X0 generates the following four output sequences of two bits (signals U1 and U0) which end always with 11
10-01-01-10-11 if X1=0 e X0=010-01-10-01-10-10-11 if X1=0 e X0=100-10-00-11 if X1=1 e X0=001-10-10-10-10-11 if X1=1 e X0=1
The programming signals X1 and X0 are significant only when the output is 11 The network has an synchronous RESET Direct synthesis
RSSCK
X1
X0
U1
U0
42
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5rArr10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
The SSN uses a modulo N counter with N coded by the two input signals X1 e X0 (sampled when U1U0=11)
For the solution we can use a module 8 counter with synchronous RES and a combinatorial network with X1 and X0 as inputs Since the signals X1 and X0 are significant only when U1U0 = 1 they must be sampled (X1_C e X0_C) through two flip-flops when the SSN output is U1U0 = 11 The signals U1 and U0 are the decoding of the module 8 counter status according to X1_C and X0_C
The counter must be reset when U1U0 = 11
RSSCK
X1
X0
U1
U0
43
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X1_SX1
X1_S e X0_S synthesis
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X0_SX0
44
U1 and U0 truth table
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5 rArr (0 to 4hellip)
10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
X1_S and X0_S values
Cont | 00 01 11 10000 | 00110 00110 00100 00101001 | 01001 01001 01010 01010010 | 01101 01110 01100 01110011 | 01110 10001 00011 10010 100 | 00011 10110 ------ 10110101 | ------ 11010 ------ 00011 110 | ------ 00011 ------ ------111 | ------ ------ ------ ------
Status U1U0
Is this synthesis of the network safe
No beacuse the donrsquot cares could keep the network stable out of the main cycles
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
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- Slide 11
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- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
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- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
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- Slide 53
- Slide 54
- Slide 55
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- Slide 65
- Slide 66
- Slide 67
- Slide 68
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- Slide 70
- Slide 71
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- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
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- Slide 80
- Slide 81
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- Slide 83
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- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
41
Exercise
Design a synchronous sequential network which according to two programming bits X1 and X0 generates the following four output sequences of two bits (signals U1 and U0) which end always with 11
10-01-01-10-11 if X1=0 e X0=010-01-10-01-10-10-11 if X1=0 e X0=100-10-00-11 if X1=1 e X0=001-10-10-10-10-11 if X1=1 e X0=1
The programming signals X1 and X0 are significant only when the output is 11 The network has an synchronous RESET Direct synthesis
RSSCK
X1
X0
U1
U0
42
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5rArr10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
The SSN uses a modulo N counter with N coded by the two input signals X1 e X0 (sampled when U1U0=11)
For the solution we can use a module 8 counter with synchronous RES and a combinatorial network with X1 and X0 as inputs Since the signals X1 and X0 are significant only when U1U0 = 1 they must be sampled (X1_C e X0_C) through two flip-flops when the SSN output is U1U0 = 11 The signals U1 and U0 are the decoding of the module 8 counter status according to X1_C and X0_C
The counter must be reset when U1U0 = 11
RSSCK
X1
X0
U1
U0
43
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X1_SX1
X1_S e X0_S synthesis
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X0_SX0
44
U1 and U0 truth table
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5 rArr (0 to 4hellip)
10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
X1_S and X0_S values
Cont | 00 01 11 10000 | 00110 00110 00100 00101001 | 01001 01001 01010 01010010 | 01101 01110 01100 01110011 | 01110 10001 00011 10010 100 | 00011 10110 ------ 10110101 | ------ 11010 ------ 00011 110 | ------ 00011 ------ ------111 | ------ ------ ------ ------
Status U1U0
Is this synthesis of the network safe
No beacuse the donrsquot cares could keep the network stable out of the main cycles
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
- Slide 59
- Slide 60
- Slide 61
- Slide 62
- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
42
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5rArr10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
The SSN uses a modulo N counter with N coded by the two input signals X1 e X0 (sampled when U1U0=11)
For the solution we can use a module 8 counter with synchronous RES and a combinatorial network with X1 and X0 as inputs Since the signals X1 and X0 are significant only when U1U0 = 1 they must be sampled (X1_C e X0_C) through two flip-flops when the SSN output is U1U0 = 11 The signals U1 and U0 are the decoding of the module 8 counter status according to X1_C and X0_C
The counter must be reset when U1U0 = 11
RSSCK
X1
X0
U1
U0
43
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X1_SX1
X1_S e X0_S synthesis
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X0_SX0
44
U1 and U0 truth table
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5 rArr (0 to 4hellip)
10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
X1_S and X0_S values
Cont | 00 01 11 10000 | 00110 00110 00100 00101001 | 01001 01001 01010 01010010 | 01101 01110 01100 01110011 | 01110 10001 00011 10010 100 | 00011 10110 ------ 10110101 | ------ 11010 ------ 00011 110 | ------ 00011 ------ ------111 | ------ ------ ------ ------
Status U1U0
Is this synthesis of the network safe
No beacuse the donrsquot cares could keep the network stable out of the main cycles
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
- Slide 59
- Slide 60
- Slide 61
- Slide 62
- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
43
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X1_SX1
X1_S e X0_S synthesis
A_RES
D
D
A_RES
Q
Q
CK
OE
1
DEC(U1=1U0=1)
1
0
X0_SX0
44
U1 and U0 truth table
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5 rArr (0 to 4hellip)
10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
X1_S and X0_S values
Cont | 00 01 11 10000 | 00110 00110 00100 00101001 | 01001 01001 01010 01010010 | 01101 01110 01100 01110011 | 01110 10001 00011 10010 100 | 00011 10110 ------ 10110101 | ------ 11010 ------ 00011 110 | ------ 00011 ------ ------111 | ------ ------ ------ ------
Status U1U0
Is this synthesis of the network safe
No beacuse the donrsquot cares could keep the network stable out of the main cycles
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
- Slide 59
- Slide 60
- Slide 61
- Slide 62
- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
44
U1 and U0 truth table
10-01-01 -10 -11 if X1=0 and X0=0 modulo 5 rArr (0 to 4hellip)
10 -01-10-01-10-10-11 if X1=0 and X0=1 modulo 7rArr00-10-00-11 if X1=1 and X0=0 modulo 4rArr01-10-10-10-10-11 if X1=1 and X0=1 modulo 6rArr
X1_S and X0_S values
Cont | 00 01 11 10000 | 00110 00110 00100 00101001 | 01001 01001 01010 01010010 | 01101 01110 01100 01110011 | 01110 10001 00011 10010 100 | 00011 10110 ------ 10110101 | ------ 11010 ------ 00011 110 | ------ 00011 ------ ------111 | ------ ------ ------ ------
Status U1U0
Is this synthesis of the network safe
No beacuse the donrsquot cares could keep the network stable out of the main cycles
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
- Slide 59
- Slide 60
- Slide 61
- Slide 62
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- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
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- Slide 80
- Slide 81
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- Slide 83
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- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
45
Exercise
Design (direct design) a SSN which ininterruptedly checks and counts according to the subsequently explained rules whether the last 4 bits received on a serial input IN are either ldquo1001rdquo or ldquo0110rdquo Whenever the ldquo1001rdquo is received a module 16 counter must be incremented by 1 on the contrary if the sequence ldquo0110rdquois received the counter must be decreased by 1 Upon all other sequences the counter status doesnrsquot change If the counter status is 0000 no decrement in any case can take place If the counter status is 1111 it must be incremented if the right sequence (ldquo1001rdquo) is received 1) Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4
received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo 2) Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown
counters with UD and EN3) The system must have an output Z signalling the overflow or the attempted underflow of the
counter
RC1
B3
B2
B1
B0
RC2
B3
B2
B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
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- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
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- Slide 53
- Slide 54
- Slide 55
- Slide 56
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- Slide 58
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- Slide 60
- Slide 61
- Slide 62
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- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
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- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
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- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
Z1 = B3 B2 B1 B0 (1001)Z2 = B3 B2 B1 B0 (0110)
UD
CounterX4
EN
U0U1
TC
UD
CounterX4EN
U0U1
TC
UD
EN
CK
ZU3U2U0U1
46NB TC=1 when U1=U0=1 if UP or when U1=U0=0 if Down
Question 1Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3 B2 B1 B) are ldquo1001rdquo or ldquo0110rdquo
Question 2Design a module 16 counter (up-down) with UD and EN inputs using module 4 updown counters with UD and EN
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
- Slide 59
- Slide 60
- Slide 61
- Slide 62
- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
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- Slide 75
- Slide 76
- Slide 77
- Slide 78
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- Slide 80
- Slide 81
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- Slide 84
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- Slide 86
- Slide 87
- Slide 88
-
47
Question 3
RC1
IN
B2B1
B0
RC2
IN
B2B1
B0
Z1=1 if ldquo1001rdquo
Z2=1 if ldquo0110rdquo
4 bit SHIFT
REGISTER
IN
S0S1S2
IN
CK
B1B2
S3
B0B3
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
- Slide 59
- Slide 60
- Slide 61
- Slide 62
- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
48
Z = DEC(ldquo1111rdquo)(UD)+ DEC(ldquo0000rdquo)(UD)
The counter is always enabled if the received sequence is ldquo1001rdquo (Z1=1)and disabled when the sequence ldquo0110rdquo (Z2=1) is received AND at the same time the counter status 0000 with DOWN enabled (Z=1)
CounterX16
EN
U0U1
Z
U2U3
UDZ1
CK
S0S1S2S3
ENABLE Z
Z1 = B3B2B1 B0 (1001) (command Up -gt UD=1)Z2 = (B3 B2 B1B0) (0110) (command Down ndashgt UD=0)
ENABLE = Z1 + Z2Z0 (Z0 is laquo0000raquo decoded) NB if ENABLE=0 UD has no meaning
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
- Slide 59
- Slide 60
- Slide 61
- Slide 62
- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
49
Exercise
I1 Z
CK
SET
I0
10
30
50
80
Design a periodic rectangular waveform generator (T=5ns ndash frequency ) with programmable duty-cycle (the percentage of a period where the signal is 11) The duty cycle is coded by two input signals I1 e I0 as
follows
I1I0 = 00 duty-cycle 10
I1I0 = 01 duty-cycle 30
I1I0 = 10 duty-cycle 50
I1I0 = 11 duty-cycle 80
I1 and I0 are meaningful only if the input signal SET is 1 in this case a new duty cycle is set starting from
the next clock The clock period is 500ps (frequency ) The system is based on a modulo 16 counter with ENABLE and synchronous RESET
Synchronousnetwork
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
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- Slide 10
- Slide 11
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- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
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- Slide 42
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- Slide 49
- Slide 50
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- Slide 53
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- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
- Slide 74
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- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
50
CK
I1
FFDD Q I1_S
1
0
SET
CK
I0
FFDD Q I0_S
1
0
SET
I1_c and I0_c synthesis
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
- Slide 59
- Slide 60
- Slide 61
- Slide 62
- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
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- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
51
CounterX16
EN
U0U1U2
CK
RES
U3
1
SET + U3U0
DEC 416
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
The AND U3U0 decodes the binary 9
(counts by 10)
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
- Slide 59
- Slide 60
- Slide 61
- Slide 62
- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
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- Slide 71
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- Slide 73
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- Slide 76
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- Slide 78
- Slide 79
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- Slide 81
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- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
52
I1_S I0_S
10
0
1
2
3
Z
DO
DO + D1 + D2
DO + D1 + D2 + D3 + D4
DO + D1 + D2 + D3 + D4 + D5 + D6 + D7
Z output synthesis
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
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- Slide 7
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- Slide 17
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- Slide 20
- Slide 21
- Slide 22
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- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
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-
53
10
30
50
80
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
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- Slide 53
- Slide 54
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- Slide 57
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- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
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- Slide 73
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- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
Exercise
54
Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5 The groups do not overlap and the bit are received starting from the MSbit Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it in all other periods the Z output is donrsquot care Direct synthesis
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
- Slide 59
- Slide 60
- Slide 61
- Slide 62
- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
Shitft Reg
Decoder
Counter
55
Counter x3 with synchronous reset
The output 1 if the value is 0-1-6-7
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
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- Slide 17
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- Slide 20
- Slide 21
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- Slide 24
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- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
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- Slide 33
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- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
A synchronous network must be designed which controls the but tickets emission The network has two synchronous inputs X2 and X1 which encode the value of the inserted coins The input enconding is the following
X2X1=00 no coin
X2X1=01 10cent coin
X2X1=10 20cent coin
X2X1=11 50cent coin
The configurations X2X1 lasts one clock period only The network has an output Z which is 1 when the sum of the inserted coins is 50cent or more and lasts three clock periods during which the ticket is printed During the printing the input is automatically inhibited (granted not to be designed) The machine does not provide change if more than 50cent are inserted
Exercise
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
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- Slide 10
- Slide 11
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- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
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- Slide 68
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- Slide 79
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- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
The system can be decomposed in two subsystems one detects the coin sum and the other controls the ticket print A 4 bit full-adder is needed plus a register which stores the already inserted credit whose input is a 24 decoder Considering the values 12 and 5 (representing 10 20 and 50) 1 and 2 can be directly fed into the decoder while if 5 is represented by 11 (decimal 3) a network must be inserted The output of the so obtained network is fed into the FA whose second input is the output of the adding register
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
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- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
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- Slide 45
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- Slide 49
- Slide 50
- Slide 51
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- Slide 53
- Slide 54
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- Slide 58
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- Slide 71
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- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
FA values A2 A1 A0X2X1=00 no coin 0 0 0X2X1=01 10cent coin 0 0 1X2X1=10 20cent coin 0 1 0X2X1=11 50cent coin 1 0 1
SUM
This OR is needed because the FA A0 must be 1 when the decoder input is 1 or 5 (in this last case together with A2)
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
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- Slide 20
- Slide 21
- Slide 22
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- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
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- Slide 33
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- Slide 88
-
Counter x4 When 3 is reached it is reset and then stops The count restarts when the enable is activated again by the decoder
The count is enabled either by the decoder or by a counter value different from 0
The counter enable resets the partial sum register
The coin sum can have a value beween 50 and 90 cents (decoder 5-9)
Counterenable
Letrsquos now analyze the circuit which enables the ticket print for 3 clock periods when 50cent or more have been inserted We can use a counter with an enable input which is activated
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
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- Xilinx schematic
- Slide 27
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- Xilinx schematic
- Slide 30
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-
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light A synchronous network with two inputs T and X must be designed T is the traffic light status T=1 if the traffic light is red X is a synchronous signal which samples the presence of a vehicle over the traffic light line The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods Formal synthesis
Exercise
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
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- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
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- Slide 51
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- Slide 53
- Slide 54
- Slide 55
- Slide 56
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- Slide 58
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- Slide 60
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- Slide 62
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- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
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- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
B Auto
detected
EEND
DEnd
XTS
A initial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto still
under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks longwith red light
0-1 Shutteractive
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
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- Slide 46
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- Slide 49
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- Slide 61
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- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
0001 0001 - -
- - - -
- - - -
- - - -
A 000B 001C 011D 010E 110F 111G 101H 100
00 01 11 10
XTy1y2y3
The green cells correspond to donrsquot care since the distance between two consecutive vehicles is at least three clock periods
BAuto
detected
EFine
DFine
XTS
Ainitial
0-0
0-0
1-0 Auto
detected
000
Auto one clock long leaves with the green ligth
1-0 Auto
Under the sensor
000
Auto two clocks long leaves with the green ligth
CAuto
detected
1-0
Auto gt=2 clocks long
010 Auto
1 clock longexits with red light
010 Auto
2 clocks long with red light
0-1 Shutteractive
X -gt auto detectedT -gt traffic light status (Red ndash Green)S -gt Shutter
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
- Slide 59
- Slide 60
- Slide 61
- Slide 62
- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
0000 0000 0010 0010
0000 1100 0110 0110
0000 0100 0110 0110
1100 1100 - -
- - - -
- - - -
- - - -
000001011010100101111110
00 01 11 10
XTy1y2y3
0001 0011 - -
D1 = y1y2y3 + XTy2y3
D2 = y1y2y3 + Ty3 + Xy3
D3 = X
S = y1
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
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- Slide 10
- Slide 11
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- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
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- Slide 33
- Slide 34
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-
64
Buffer
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
- Slide 59
- Slide 60
- Slide 61
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- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period A ist valid only if E is at the same time 1 The network output must be 1 for one clock when A is 1 for five times (non consecutive too) Whenever A is 0 the number of ones must be decremented by 1 When the value 0 is reached and A=0 (with E=1) the count in not decremented any more After U=1 the network the count is reset Direct synthesis
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
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- Slide 10
- Slide 11
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- Slide 17
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- Slide 19
- Slide 20
- Slide 21
- Slide 22
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- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
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- Slide 33
- Slide 34
- Slide 35
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-
66
Dec 38Cx8
L
EN
UD
Y 5 U
A
En
Count up if EN=A=1
0
Count down if EN=1 and A=0 if the count is not zero
D0 D1 D2
laquo0raquo
After U=1 the count is reset unless EN=A=1 in the same period (in this case D0=1 e therefore the counter is loaded with 1 through the signal LOAD)
Preset inputs
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
- Slide 59
- Slide 60
- Slide 61
- Slide 62
- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
The following network must be analysed
LOAD active only if EN=1
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
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- Xilinx schematic
- Slide 27
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- Xilinx schematic
- Slide 30
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-
68
0 1X
00
01
11
10
QB QA
ENLD(truth table)
00
10 01
01
10
11
11 01
0000
1000 0101
1001
0100
1110
0000 1100
0 1X
00
01
11
10
QB QA
Future QBQA Z1Z2
EN=LD=1 -gt Load
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
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- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
- Slide 59
- Slide 60
- Slide 61
- Slide 62
- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
69
A given (not to be designed) logical network sends not continuously 4 bit data to network B When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F Direct design
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
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- Slide 9
- Slide 10
- Slide 11
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- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
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- Slide 88
-
70
READy=0 prevents the counter RESET
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
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- Slide 14
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- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
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- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
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- Slide 40
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- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
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- Slide 88
-
71
Behavioural simulation
STORE asynchronous
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
- Slide 59
- Slide 60
- Slide 61
- Slide 62
- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
Design with VHDL a synchronous logical network which periodically after three clock periods sets to 1 for one clock period its output The network is provided with a reset signal (a_res)
a_resCK
OUT
CK
OUT (0) (1) (2) (0) (1) (2)(3) (3)
OUT
72
Exercise
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
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- Slide 21
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- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
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- Slide 33
- Slide 34
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- Slide 86
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- Slide 88
-
Letrsquos analyse some possible implementations where the internal state too must be analysed
library ieeeuse ieeestd_logic_1164alluse ieeestd_logic_1164alluse ieeestd_logic_arithalluse ieeestd_logic_unsignedalluse ieeenumeric_stdalllibrary unisimuse unisimvcomponentsall
------------------------------------------------------------------------------------ Careful for a vector sum all the previous laquouseraquo must be used----------------------------------------------------------------------------------Entity Exercise is Port ( ck in std_logic a_res in std_logic------------------------------------------------------------------------------- As output the internal state too is analysed-- Very useful temporarily for the system check-----------------------------------------------------------------------------
internal_status_counter out std_logic_vector(1 downto 0) signal_out out std_logic )end Esercise
As an example in the first two cases the network will be based on two processes a process which controls the counter update
process_counter process(cka_res)
and a process which generates the network output
process_output process(internal_state_signal) 73
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
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- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
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- Slide 42
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- Slide 44
- Slide 45
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- Slide 51
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- Slide 57
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- Slide 60
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- Slide 69
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- Slide 71
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- Slide 73
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- Slide 75
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- Slide 80
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- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
Solution 1
architecture Behavioral of Exercise is
-- an internal status signal -- (an output signal ndash internal_state_counter - CANNOT be read - INOUT insted of OUT could have been used)
signal internal_status_signal std_logic_vector(1 downto 0)begin process_counter process(cka_res) -- begin
if (a_res=1) then -- immediate upon resetinternal_status_signal lt= 00
elsif (ckevent) and (ck=1) then -- upon positive clock edge internal_status_signal lt= internal_status_signal + 1
end if -- otherwise unchanged
-- export status internal_state_counter lt= internal_status_signal -- changes with the change of a sensitivity list signal
-- ie clock end process process_counter
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
process_output process(internal_status_signal) -- NB IT doesnrsquot depend on the clock -- immediate effect upon internal_status_signal change begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral
Exe
cute
d in
par
alle
l
74
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
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- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
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- Slide 33
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- Slide 36
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- Slide 87
- Slide 88
-
For the internal status STD_LOGIC vector are used But the status is initialized only when the first reset is active (in this case clock independent) A solution can be to initialize the status in the vector definition (equivalent to presetreset)
The simulation underlines a first problem
architecture Behavioral_1 of Exercise issignal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo -- initial value
75
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
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- Slide 85
- Slide 86
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- Slide 88
-
The simulation underlines a second problem
The status changes on the clock trailing edges and the output is set frac12 clock period in comparison with the status Why
architecture Behavioral_1 of Exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=ldquo00rdquo
beginprocess_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00
12
76
Letrsquo analyze the code again
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
- Slide 52
- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
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- Slide 60
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- Slide 65
- Slide 66
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- Slide 78
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- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
elsif (CKevent) and (CK=1) then internal_status_signal lt= internal_status_signal + 1
end if
internal_status_counter lt= internal_status_signal
-- Here we use the old value of internal_status_signal ndash the statements are concurrent-- But the new value will be updated when this process will be triggered by the change of one
-- of the variables of the sensitivity list that is (with the exclusion of A_RES)-- when a new clock event occurs But the next event is the clock trailing edge
-- (in this case not conditioned by CK=1 ) -- Therefore upon the clock trailing edge internal_status_counter -- is immediately assigned the value + 1
end process process_counter
processo_output process(internal_status_signal l)begin
-- This process is triggered when the value of -- internal_status_signal (CAREFUL NOT internal_status_counter )-- is updated (independently from the clock )
-- that is as soon internal_status_signal is modifiedif (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend Behavioral_1
2277
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
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- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
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- Slide 33
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- Slide 35
- Slide 36
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-
Solution 2
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 -- exporta status internal_status_counter lt= internal_status_signal
end ifend process process_counterprocess_output process(internal_status_signal)begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
Letrsquos avoid to update the signal before the process ends
78
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
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- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
The signal internal_status_signal depends on the event
(CKevent) and (CK=1lsquo)
and this avoid the change upon the clock trailing edge
Buthellip internal_status_counter is updated one clock later (the output is 1 when the status is 10) Why
Letrsquos analyze the code
79
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
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- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
architecture behavioral of exercise is
signal internal_status_signal std_logic_vector(1 downto 0)=00begin
process_counter process(cka_res)begin
if (a_res=1) then internal_status_signal lt= 00 internal_status_counter lt= 00
elsif (ckevent) and (ck=1) then internal_status_signal lt= internal_status_signal + 1 internal_status_counter lt= internal_status_signal
-- internal_status_counter is delayed one clock -- after internal_status_signal
end if
end process process_counterprocess_output process(internal_status_signal )begin
if (internal_status_signal=11) then signal_outlt=1else signal_out lt= 0end if
end process process_outputend behavioral
80
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
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- Slide 53
- Slide 54
- Slide 55
- Slide 56
- Slide 57
- Slide 58
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- Slide 60
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- Slide 63
- Slide 64
- Slide 65
- Slide 66
- Slide 67
- Slide 68
- Slide 69
- Slide 70
- Slide 71
- Slide 72
- Slide 73
- Slide 74
- Slide 75
- Slide 76
- Slide 77
- Slide 78
- Slide 79
- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
architecture behavioral of Exercise isBegin
process_counter process(cka_res) isbegin
if (ckevent) and (ck=1) thenif (a_res=1) then counter_status lt= 00
signal_out lt= 0else
counter_status lt= counter_status + 1
if (counter_status = 10ldquo ) then signal_outlt=1
-- else signal_out lt= 0end if
end ifend if
end process process_counterend behavioral
81
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
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- Slide 14
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- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
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- Slide 39
- Slide 40
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- Slide 88
-
82
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
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- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
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- Slide 81
- Slide 82
- Slide 83
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- Slide 85
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- Slide 87
- Slide 88
-
Module N counter with synchronous reset
Letrsquos design a modulo N programmable counter with synchronous reset A_RES and an ENABLE The counter has an output END_COUNT activated when the count value is reeached
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsall
entity Counter_module_N is Port (CK in std_logic A_RES in std_logic
ENABLE in std_logic Max_val in std_logic_vector (15 downto 0) -- Max_val -gt N count COUNT inout std_logic_vector (15 downto 0) END_COUNT out std_logic)
end Counter_module_Narchitecture Behavioral of Counter_module_N isbeginprocesso process(CK A_RES ENABLE)begin
if (CK=1) and (CKevent) thenif (A_RES=1) then
COUNT lt= X0000 -- NB Hexadecimal notation END_COUNT lt= 0 -- 0 upon next clock
elsif ENABLE=1 then -- Only if reset is inactiveif COUNT lt Max_val then COUNT lt= COUNT +1 -- Input valueelse COUNT lt= X0000end ifif COUNT = Max_val -1 then END_COUNT lt= 1 -- Upon next clock else END_COUNT lt= 0end if
end ifend if
end process processoend Behavioral 83
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
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- Slide 58
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- Slide 60
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-
library IEEEuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_1164ALLuse IEEESTD_LOGIC_ARITHALLuse IEEESTD_LOGIC_UNSIGNEDALLUSE ieeenumeric_stdALLlibrary UNISIMuse UNISIMVComponentsallENTITY Test ISEND Test ARCHITECTURE behavior OF Test IS
COMPONENT Counter_modulo_N PORT( CK IN std_logic A_RES IN std_logic ENABLE IN std_logic Max_val IN std_logic_vector(15 downto 0) COUNT INOUT std_logic_vector(15 downto 0) END_COUNT OUT std_logic ) END COMPONENT signal CK std_logic = 0 signal A_RES std_logic = 0 signal ENABLE std_logic = 0 signal Max_val std_logic_vector(15 downto 0) = (others =gt 0) signal COUNT std_logic_vector(15 downto 0) signal END_COUNT std_logic constant CK_period time = 10 ns BEGIN uut Counter_modulo_N PORT MAP (
CK =gt CKA_RES =gt A_RESENABLE =gt ENABLEMax_val =gt Max_valCOUNT =gt COUNTEND_COUNT =gt END_COUNT)
Testbench12
Testbed internal signals
84
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
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- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
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- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
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- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
clock_process processvariable I integer
beginA_RES lt= 1Max_val lt= X0007 -- contare fino a 7for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopA_RES lt= 0ENABLE lt= 1for I in 3 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 0for I in 1 downto 0 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopENABLE lt= 1for I in 0 to 40 loop
ck lt= 0wait for ck_period2ck lt= 1wait for ck_period2
end loopwait
end process
END
Testbench 22
85
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
- Slide 11
- Slide 12
- Slide 13
- Slide 14
- Slide 15
- Slide 16
- Slide 17
- Slide 18
- Slide 19
- Slide 20
- Slide 21
- Slide 22
- Slide 23
- Slide 24
- Slide 25
- Xilinx schematic
- Slide 27
- Slide 28
- Xilinx schematic
- Slide 30
- Slide 31
- Slide 32
- Slide 33
- Slide 34
- Slide 35
- Slide 36
- Slide 37
- Slide 38
- Slide 39
- Slide 40
- Slide 41
- Slide 42
- Slide 43
- Slide 44
- Slide 45
- Slide 46
- Slide 47
- Slide 48
- Slide 49
- Slide 50
- Slide 51
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- Slide 80
- Slide 81
- Slide 82
- Slide 83
- Slide 84
- Slide 85
- Slide 86
- Slide 87
- Slide 88
-
In this simulation the counter basis is 7 and the notation is Hexadecimal
86
Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
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Statement others
With others it is possible to set the content of some or of all elements of a vector not otherwise explicitly set For instance
vector lt= (0=gt1 others =gt0)
(the right arrow means always assignment) This statement set to 1 the LSbit and all others to 0 (How many With others it is not necessary to know this information)
Array attributed
In VHDL there are also array attributes For instance for a vector
VECTOR std_logic_vector(4 downto 0)
VECTORrsquolength provides value 5 (like laquosizeofraquo in C)
87
Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
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- Xilinx schematic
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- Xilinx schematic
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Conversion functions
In the IEEE libraries some functions are defined to convert values For instance in the IEEEstd_logic_arith a function is defined to convert from integer to STD_LOGIC_VECTOR (and many others)
ltslv_siggt = CONV_STD_LOGIC_VECTOR(ltint_siggt ltint_sizegt)
For instance if half_word is a signal type STD_LOGIC_VECTOR(15 downto 0) and value is type integer the conversion of value to a STD_LOGIC_VECTOR can be achieved through
half_word = CONV_STD_LOGIC_VECTOR(value 16)
In Xilinx ISE the functions are displayed when the toolbar icon is clicked With the same command the precompiled components can be used
88
Integer with or withou sign
Bits numberVettore
- Synchronous logical networks II
- Slide 2
- Slide 3
- Slide 4
- Slide 5
- Slide 6
- Slide 7
- Slide 8
- Slide 9
- Slide 10
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- Xilinx schematic
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- Xilinx schematic
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