Synchronous Sequential Circuits

byDr. Amin Danial Asham

References

Digital Design 5th Edition, Morris Mano

Memory Elements Memory elements store binary information in the form of

either 1 or 0 for an indefinite time period as long as there is power to the storing circuit.

Each memory element stores a binary bit. Memory elements are classified into two types based on

how are they controlled:o Latches: are controlled by the input signal levels.

Latches are level sensitive to input signals. Therefore, these elements are asynchronous elements.

o Flip-flop: are triggered by the clock transitions and hence these elements are synchronous. Therefore, flip-flops are edge sensitive to clock signal.

NOT Gate SR Latch There are two input signal S (set) and R(reset):o S=1 and R=0 set the output Q to 1 and the output

complement Q’ to 0 (Set State)o S=0 and R=1 set the Q to 0 and the complement Q’ to

1 (Reset State)o When both S and R are 0’s the current value is stored.o When both S and R are 1’s both Q and Q’ are 0’s which

is forbidden.

NOT Gate SR Latch(continue) Why both S and R are forbidden to be set to 1 for NOR

SR Latch?o In case of both S and R are 1’s at the same time, both Q and

Q’ are zeros at the same time.o If then both S and R returned back to 0’s simultaneously the

device enters unpredictable state. SR latch has two useful states Set state and Reset state.

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NOT Gate SR Latch

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NAND Gate SR Latch (continue) SR Latch can be also implemented by NAND gates. There are two input signal S (set) and R(reset):

o S=1 and R=0 set the output Q to 0 and the output complement Q’ to 1 (Reset State).

o S=0 and R=1 set the Q to 1 and the complement Q’ to 0 (Set State).

o When both S and R are 1’s the current value is stored.o When both S and R are 0’s both Q and Q’ are 1’s which is

forbidden.

NAND Gate SR Latch (continue) Why both S and R are forbidden to be set to 0 for NAND

SR Latch?o In case of both S and R are 0’s, both Q and Q’ become 1’s.o If then both S and R returned back to 1’s simultaneously the

device enters unpredictable state. SR latch has two useful states Set state and Reset state.

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NAND Gate SR Latch (continue)

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Basic NAND Latch

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SR Latch With Enable: En signal is added to enable and disable the latch, that is, in case of

En= 0 the latch is disabled and hence the output does not change with the input signals.

When En= 0 the 1’ are fed to the set and reset of the original NAND latch circuit and hence the output is stored and not affected by the inputs

When En=1 both S and R signals are fed to the original NAND latch in inverted form.

SR Latch With Enable (continue) In case of S, R, En are 1’s, the basic latch is fed by 0’s on both

set and rest signals and hence both outputs are on 1’s (forbidden).

If then En is back to 0 then the inputs to the basic latch becomes ones which puts the latch into unpredictable state and the next state depends on which one of S and R becomes zero first.

Basic NAND Latch

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D-Latch This is called the transparent latch:

o In case of En=0 the output is stored and not affected by the input.

o In case od En=1 the output is following the input signal D, that is, .

o NOT gate ensures that S and R signals of the original NAND latch are never 0 at the same time and hence avoiding the indeterminate state. .

D-Latch (continue)

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D-Latch (continue)

The changes of the output of the latch follows the changes of the input D during the enable input En is at level high.

Therefore, latches are level sensitive devices.

Negative Edge Triggered D-FF

Edge Triggered D Flip-Flops: Master Slave Master-Slave D Flip-Flops is controlled by the clock signal:o In case of Clk is high the master D-latch samples the D signal and

the output . The slave D-latch is disabled and hence the output Q equals the previous value.

o When the Clk changes from 1 to 0 the master D-latch is disabled and hence Y is locked and not affected by the input. The slave D-latch is enabled and the Y is transferred to the output Q.

o The change of the output Q is triggered by the clock falling edge.

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Edge Triggered D Flip-Flops: Master Slave (continue)

Edge Triggered D Flip-Flops: Master Slave (continue) The behavior of the Master Slave D FF can be described as follows:o The output of the flip flop is changed once since a fixed value Y is transferred

to the output, which is stored immediately before the falling edge of the clock. Therefore input changes after falling edge has no effect since master latch is disabled and Y is locked.

o A change in the output is triggered by the negative edge of the clock.o The output change may complete only during the negative level of the clock.

A positive edge Master-Slave D-FF is:

Positive Edge Triggered D-FF

Edge Triggered D Flip-Flops: Master Slave (continue)

Edge Triggered D Flip-Flop Symbols

Other types of Flip-FlopsJK Flip Flop

If therefore . Consequently,

If therefore . Consequently, . Reset state.

If therefore . Consequently, . Set state.

If therefore . Consequently, . Toggle.

𝐷=𝑇⨁𝑄 (𝑡 )=𝑇𝑄 ′ (𝑡 )+𝑇 ′𝑄 (𝑡)

Other types of Flip-Flops (continue)Toggle Flip Flop

+¿Characteristic Table Characteristic Table

Other types of Flip-Flops (continue)Flip-Flop with Direct Inputs

011

Direct inputs drive the FF to a certain state independently of the clock. Direct Set or Preset drive the FF to set state (Q=1 and

Q’=0) Direct Reset or Clear drive the FF to reset state (Q=0 and

Q’=1) Direct inputs are useful to set the FF to a certain state after

turning the power on because the state is unknown at that case.

Characteristic Table The Characteristic table of a FF describes the output of the

next state as a function of the inputs and the present state . o the present state before the clock transition. o the next state after the clock transition.

Characteristic Equations Logic characteristics of FF’s in characteristic tables can

be expressed algebraically by characteristic Equations.

oFor

oFor

oFor

Thanks