synchronous sequential logicviplab.cs.nctu.edu.tw/course/dcd2017_spring/dcd_lecture_05.pdflecture 5...

Digital Circuit Design

Synchronous Sequential Logic

Lan-Da Van (范倫達), Ph. D.

Department of Computer Science

National Chiao Tung University

Taiwan, R.O.C.

Spring, 2017

[email protected]

http://www.cs.nctu.edu.tw/~ldvan/

Lecture 5


Lan-Da Van DCD-05-2

Outlines

Sequential Circuits

Storage Elements: Latches

Storage Elements: Flip-Flops

Analysis of Clocked Sequential Circuits

State Reduction and Assignment

Design Procedure

HDL Description

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Lan-Da Van DCD-05-3

Sequential Circuits

Sequential Circuits

a feedback path

the state of the sequential circuit

(inputs, current state) (outputs, next state)

synchronous: the transition happens at discrete instants of

time

asynchronous: at any instant of time

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Lan-Da Van DCD-05-4

Synchronous sequential circuits a master-clock generator to generate a periodic train of clock

pulses

the clock pulses are distributed throughout the system

clocked sequential circuits

most commonly used

no instability problems

the memory elements: flip-flops

binary cells capable of storing one bit of information

two outputs: one for the normal value and one for the complement value

maintain a binary state indefinitely until directed by an input signal to switch states

Sequential Circuits

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Synchronous Clocked Sequential Circuit

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Lan-Da Van DCD-05-6

S-R Latch

SR Latch with two NOR gates

1->0

1->0

0->1->0->1…

0->1->0->1…

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Lan-Da Van DCD-05-7

SR latch with two NAND gates

an asynchronous sequential circuit (S,R)= (1,1): no operation

(S,R)=(1,0): reset (Q=0, the clear state)(S,R)=(0,1): set (Q=1, the set state)(S,R)=(0,0): indeterminate state (Q=Q'=0)

consider (S,R) = (0,0) (1,1)

S-R Latch

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Lan-Da Van DCD-05-8

SR latch with control input

En=0, no change

En=1, see the function table

S-R Latch

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Lan-Da Van DCD-05-9

D Latch

eliminate the undesirable conditions of the indeterminate

state in the RS flip-flop

D: data

gated D-latch

D Q when C=1; no change when C=0

D Latch

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Lan-Da Van DCD-05-10

Graphic Symbols

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Flip-Flops

A trigger: The state of a latch or flip-flop is switched by a

change of the control input.

Level sensitive – latches

Edge triggered – flip-flops

Clock response in latch and flip-flop

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If level-triggered latches are used

the feedback path may cause instability problem

Edge-triggered flip-flops

the state transition happens only at the edge

eliminate the multiple-transition problem

Flip-Flops

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Negative Edge-Triggered D Flip-Flop

Master-Slave D flip-flop

Two separate flip-flops

A master flip-flop (positive-level triggered)

A slave flip-flop (negative-level triggered)

The most economical and efficient

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A D-type positive-edge-triggered flip-flop

D-type positive-edge-triggered flip-flop

Positive Edge-Triggered D Flip-Flop

Three basic flip-flops

(S,R) = (0,1): Q = 1

(S,R) = (1,0): Q = 0

(S,R) = (1,1): no operation

(S,R) = (0,0): should be avoided

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Operations of D-type positive-edge-triggered flip-flop

The S and R inputs of the output latch are maintained at the

logic-1 level when Clk=0.

If D=0 When Clk becomes 1, R changes to 0. This causes

the flip-flop to go to reset state making Q=0.

If there is a change in the D input while Clk=1, terminal R

remains at 0, terminal S remains at 1, and Q=0.

Thus, the filp-flop is locked out and is unresponsive to futher

changes in the input.

When the Clk returns to 0, R goes to 1, placing the output

latch in quiescent condition without changing the output.


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Clk

D

S

R

Q

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JK flip-flop

D=JQ'+K'Q J=0, K=0: D=Q(t) Q(t+1) =Q(t): No change

J=0, K=1: D=0 Q(t+1) =0: Reset

J=1, K=0: D=1 Q(t+1) =1: Set

J=1, K=1: D=Q‘(t) Q(t+1) =Q‘(t): Complement

J-K Flip-Flop

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D = T⊕Q = TQ'+T'Q

T=0: D=Q Q(t+1) =Q(t): No change

T=1: D=Q' Q(t+1) =Q‘(t): Complement

T Flip-Flop

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Characteristic Table

Characteristic equations

D flip-flop

Q(t+1) = D

JK flip-flop

Q(t+1) = JQ'+K'Q

T flip-flop

Q(t+1) = T⊕Q

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Direct Inputs

Asynchronous set and/or asynchronous reset

D flip-flop with asynchronous reset

11

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Analysis of Clocked Sequential Ckts

State equation

A(t+1) = A(t)x(t) + B(t)x(t)

B(t+1) = A'(t)x(t)

Output equation

y(t) = (A(t)+B(t))x'(t)

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State Table – First Form

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State Table – Second Form

A(t + 1) =Ax + Bx

B(t + 1) = Ax

y = Ax + Bx

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State Diagram

State transition diagram a circle: a state

a directed lines connecting the circles: the transition between

the states Each directed line is labeled 'inputs/outputs‘

a logic diagram a state table a state diagram

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Flip-Flop Input Equations

The part of circuit that generates the inputs to flip-

flops

Also called excitation functions

DA = Ax + Bx

DB = A'x

The output equations

y = (A+B)x'

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Analysis with D flip-flops

The input equation DA=A⊕x⊕y

The state equation A(t+1)=A⊕x⊕y

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Analysis with JK flip-flops

Determine the flip-flop input function in terms of the present

state and input variables

Use the corresponding flip-flop characteristic table to

determine the next state

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JA = B, KA= Bx'

JB = x', KB = A'x + Ax‘

derive the state table


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State transition diagram

State diagram

AKAJtA AA

'')1(

BKBJtB BB

'')1(

AxABBAABxBAtA '')''(')1(

'''')'('')1( BxAABxxBBxABxtB

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Analysis with T flip-flops

The characteristic equation Q(t+1)= T⊕Q = TQ'+T'Q

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The input and output functions

TA=Bx

TB= x

y = AB

The state equations

A(t+1) = (Bx)'A+(Bx)A' =AB'+Ax'+A'Bx

B(t+1) = x⊕B


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State table


TA TB

0 0

0 1

0 0

1 1

0 0

0 1

0 0

1 1

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Mealy and Moore Models

Mealy model: the output is the function of both the present

state and inputs.

the outputs may change if the inputs change during the clock pulse

period

Moore model: the output is the function of the present state

only.

The outputs are synchronous with the clocks.

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Mealy and Moore Models

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State Reduction reductions on the number of flip-flops and

the number of gates

a reduction in the number of states may

result in a reduction in the number of flip-

flops

An example state diagram

state a a b c d e f f g f g a b d f

input 0 1 0 1 0 1 1 0 1 0 0 1 1 1

output 0 0 0 0 0 1 1 0 1 0 0 0 0 1

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Algorithm: equivalent states

Two states are said to be equivalent.

For each member of the set of inputs, they give exactly the

same output and send the circuit to the same state or to an

equivalent state

One of them can be removed

State Reduction

g=e

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Reducing the state table based on g=e

State Reduction

f=d

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The final sequence list:

state a a b c d e d d e d e a

input 0 1 0 1 0 1 1 0 1 0 0

output 0 0 0 0 0 1 1 0 1 0 0

State Reduction

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Checking of each pair of states for possible

equivalence can be done systematically

The unused states are treated as don't-care condition

fewer combinational gates

Reduced State Diagram

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State Assignment

Minimize the cost of the combinational circuits

Three possible binary state assignments

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Any binary number assignment is satisfactory as long

as each state is assigned a unique number

use binary assignment 1

State Assignment

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Design Procedure

From the word description and specification of the

desired operation, derive a state diagram for the circuit.

Reduce the number of states if necessary.

Assign binary values to the states.

Obtain the binary-coded state table.

Choose the type of flip-flops to be used.

Derive the simplified flip-flop input equations and

output equations.

Draw the logic diagram.

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Specification: Design a circuit that detects a sequence of three

or more consecutive 1’s in a string of bits coming through an

input line (i.e., the input is a serial bit stream).

State Diagram:

Starting with state S0, the reset state

If the input is 0, the circuit stays in S0, but if the input is 1, it goes to

state S1 to indicate that a 1 was detected.

If the next input is 1 (i.e., two consecutive 1s), the change is to

state S2 to indicate the arrival of two consecutive 1’s, but if the input

is 0, the state goes back to S0.

If the next input is 1, (i.e., three consecutive 1s), the change is to

state S3 to indicate the arrival of three consecutive 1’s, but if the

input is 0, the state goes back to S0.

If more 1s are detected, the circuits stays in S3.

Any 0 input sends the circuit back to S0.

Moore machine!!

Sequence Detector UsingD Flip-Flops

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Sequence detector

state diagram and state table

00 01

1011

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The flip-flop input equations

A(t+1) = DA(A,B,x) = S(3,5,7)

B(t+1) = DB(A,B,x) = S(1,5,7)

The output equation

y(A,B,x) = S(6,7)

Logic minimization using the K map

DA= Ax + Bx

DB= Ax + B'x

y = AB


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The logic diagram


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Excitation Tables

A state diagram flip-flop input functions

straightforward for D flip-flops

we need excitation tables for JK and T flip-flops

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Synthesis Using JK Flip-Flops

The state table and JK flip-flop inputs

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3-Bit Binary Counter Using T Flip-Flops

An n-bit binary counter the state diagram

no inputs (except for the clock input)

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The state table and the flip-flop inputs


0

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Logic simplification using the K map

TA2 = A1A0

TA1 = A0

TA0 = 1

The logic diagram


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5-56

Synthesizable HDL Models of Sequential Circuits

Behavioral Modeling

Example: Two ways to provide free-running clock

Example: Another way to describe free-running clock

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5-57

Behavioral Modeling

always statement

Examples:

Two procedural blocking assignments: Two nonblocking assignments:

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5-58

HDL Models of Flip-Flops and Latches

■ HDL Example 5.1

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5-59

Flip-Flops and Latches

■ HDL Example 5.2

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5-60

Characteristic Equation

Q(t + 1) = Q ⊕ T

Q(t + 1) = JQ + KQ

For a T flip-flop

For a JK flip-flop

■ HDL Example 5.3

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5-61

HDL Example 5-3 (Continued)

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5-62

HDL Example 5-4 (JK Flip-Flop)

Functional description of JK flip-flop

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5-63

State Diagram-Based HDL Models (1/3)

■ HDL Example 5.5 Mealy Machine: Zero Detector

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5-64


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5-65


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5-66

Mealy_Zero_Detector

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5-67

HDL Example 5-6 Moore Machine: Zero Detector

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5-68

Simulation Output of HDL Example 5-6

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5-69

Structural Description of Clocked Sequential Circuits

■ HDL Example 5.7 Binary Counter_Moore Model

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5-70


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5-71


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5-72


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5-73

Simulation Output of HDL Example 5-7

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Conclusion

From this lecture, you have learned the follows:

Storage Elements: SR Latch, D Latch

Storage Elements: D Flip-Flop, JK Flip-Flop, T Flip-

Flop

Analysis of Clocked Sequential Circuits


Design Procedure

Verilog Design

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