system design and measurements of a 115-kv/3.5-ms solid ...€¦ · is permitted. however,...

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System Design and Measurements of a 115-kV/3.5-ms Solid-State Long-Pulse Modulator for the European Spallation Source

M. Jaritz, J. Biela

Power Electronic Systems Laboratory, ETH Zürich Physikstrasse 3, 8092 Zürich, Switzerland

mailto:[email protected]

3232 IEEE TRANSACTIONS ON PLASMA SCIENCE, VOL. 46, NO. 10, OCTOBER 2018

System Design and Measurements of a115-kV/3.5-ms Solid-State Long-Pulse Modulator

for the European Spallation SourceMichael Jaritz , Member, IEEE, and Juergen Biela, Senior Member, IEEE

Abstract— In this paper, the results of a 2.88-MW solid-statelong-pulse modulator, which has been designed for the new linearcollider at the european spallation source in Lund, are summa-rized. The presented modulator generates an output voltage pulseof 115 kV with a pulselength of 3.5 ms. The main components ofthe modular system, which include a series–parallel resonanceconverter, a high-voltage high-frequency transformer, and anoutput rectifier, are discussed. The modulator design is verifiedby measurements performed with a full-scale prototype, whichis operated under nominal load conditions. A detailed outputvoltage ripple evaluation is given, and in addition, the systemdesign has been proven by a 7- and 2/3-h heat run test. Allspecifications are well within the given limits, and the maximumoccurring temperatures in the transformer stay below 110 ◦Ceven under worst case assumptions. The system achieves a pulseefficiency (determined by the pulse shape) of 96.78%, an overallelectrical system efficiency of 91.9%, and a combined pulsesystem efficiency of 89%.

Index Terms— Modular converter design, pulse power,series–parallel resonance converter (SPRC).

I. INTRODUCTION

FOR performing the planned high sophisticated materialscience experiments at the new linear collider at the

European Spallation Source in Lund, Sweden, 2.88-MW long-pulse modulators with a pulsed output voltage of 115 kVand pulse lengths in the range of milliseconds are required(see Table I). Applying direct switched topologies, as e.g., theapproaches presented in [1] and [2], for these modulators havethe drawback that the pulse generating components (e.g., solidstate switch) have to be designed for the full pulse voltage,and this drawback could be avoided using pulse transformers.However, pulse transformer-based topologies (e.g., [3], [4])require a huge transformer due to the high voltage timeproduct caused by the large pulselength. In order to avoid thelarge transformers, series/parallel connected dc–dc convertersswitching at a high frequency resulting in a small voltagetime product for the transformer can be used. Such dc–dcmodules can be for example based on a single active bridge

Manuscript received August 9, 2017; accepted February 8, 2018. Date ofpublication March 6, 2018; date of current version October 9, 2018. Thiswork was supported by the project partners CTI and AMPEGON AG throughthe CTI-Research Project under Grant 13135.1 PFFLR-IW. The review ofthis paper was arranged by Senior Editor W. Jiang. (Corresponding author:Michael Jaritz.)

The authors are with ETH Zurich, 8092 Zürich, Switzerland (e-mail:[email protected]; [email protected]).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPS.2018.2808219

TABLE I

MODULATOR SPECIFICATIONS

converters with transformer and output rectifier as presentedin [5], or on soft switched series–parallel resonance converters(SPRC) as shown in Fig. 1(b) and presented in [6] and [7]. Forgenerating the high output voltage, usually several modulesare connected in series at the output. Due to the resonant tank,the SPRC has sinusoidal currents and voltages resulting in lowelectromagnetic interference and allows zero voltage switch-ing for all switches, which is beneficial for MOSFETs andenables high switching frequencies. Therefore, that topologyis chosen for the considered modulator system. The SPRCtopology consists of 18 SPRC-basic modules (SPRC-Bm)[see Fig. 1(b)], which are operated at high switching frequen-cies (100–110 kHz) to minimize the dimensions of the reactivecomponents and the transformers. Furthermore, to achieve thegiven pulse specifications in Table I, an optimization procedureis used to design the components.

In this paper, a full-scale prototype system and measure-ments of the output voltage pulse for the prototype systemare presented. In Section II, first, the optimization procedurerequired for determining the optimal design parameters ispresented and all design results are summarized. Second,

0093-3813 © 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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JARITZ AND BIELA: SYSTEM DESIGN AND MEASUREMENTS OF A 115-kV/3.5-ms SOLID-STATE LONG-PULSE MODULATOR ESS 3233

Fig. 1. (a) Prototype system of the long-pulse modulator (specifications see Table I). The depicted setup includes two separate full-modulator systems (2×18SPRC-Bms in total) with a power of 2 × 2.88 MW during the pulse. (b) Block diagram of one full-modulator system, where two SPRC-Bms form an ISOPconnected stack and 9 of the ISOP stacks are connected in parallel at the input and in series at the output forming an IPOS system [8], [9]. To balance theinput voltages, active balancing circuits (i) are used. The modulator system is powered by the IVCU, which is a PFC boost converter. The full-modulatorsystem has been built by AMPEGON AG.

the built prototype system is introduced in Section III andthe components of a SPRC-Bm are described. In Section IV,the critical temperatures of the transformers are determinedunder the assumption of a worst-case isolation oil temperature.Finally, the performance is evaluated by measured nominaloutput voltage pulses in Section V.

II. OPTIMIZATION PROCEDURE

Due to the high number of degrees of freedom as forexample the transformer geometry, number of turns or thenumber of parallel semiconductor devices/chip area, and anoptimization procedure, as depicted in Fig. 2, has been devel-oped for optimally designing the modulator system. First, allelectrical parameters as for example the primary current Iprimof the transformer, the transformer turns ratio N , the switchingfrequency f , and the dc-link voltage VDL or the output voltageof the transformer Vsec are determined with the electricalmodel of a single SPRC-Bm. These parameters in combinationwith the user-defined constraints are used within the optimiza-tion loops to minimize the transformer volume and to optimizethe number of parallel switches of the full bridge for minimallosses. In addition, the transformer leakage inductance Lσ

and the stray capacitance Cd are determined with modelsgiven in [7], because Lσ is a part of the resonant inductanceLS and Cd is a part of the parallel capacitance CP .

After the transformer optimization, a post isolation fieldconform design check of the transformer is performed withthe help of FEM computations. This step is performed out-side of the optimization loop, because it is not possible toinclude a detailed model of the complex isolation structure inthe optimization routine without increasing the computationaleffort too much. The detailed description of the transformeroptimization procedure is given in [10], and the appliedthermal model of the semiconductor switches is presentedin [6].

Fig. 2. Developed optimization procedure of the full-modulator system,which leads to an optimal design of a single SPRC-Bm and an optimal numberof modules.

Finally, if all global specifications (see Table I) are fulfilled,the procedure results in an optimal set of parameters and


Fig. 3. (a) Active input voltage balancing circuit operated with fixedswitching frequency fbal and fixed duty cycle Dbal in DCM. (b) Builtbalancing bridge.

components of the SPRC-Bm and in an optimal number ofmodules for the modulator system. The optimization resultsfor the considered specifications in Table I are summarizedin Table II.

III. PROTOTYPE SYSTEM

Based on the optimization results, the prototype modulatorsystem has been built and is presented together with thecomponents of the single SPRC-Bm in the following.

A. Full-Modulator System

The diagram are depicted in Fig. 1(a) and (b). A singleSPRC-Bm of the modulator consists of an MOSFET fullbridge, a resonant tank, a transformer, and an output rectifieras presented in [11] and depicted in Fig. 1(b). Two SPRC-Bms with a 400-V dc-link voltage are connected in series atthe input, sharing the same 800-V input voltage bus. At theoutput, the modules are connected in parallel, forming an inputseries output parallel stack (ISOP). To achieve the full outputvoltage and to deliver the full output power given in Table I,nine of the ISOP stacks are connected in parallel at the inputand in series at the output, forming an input parallel connectedoutput series connected (IPOS) system [see Fig. 1(b)].

Each ISOP system also contains an active balancing circuit(DC-Bi ) [8], [9], which equalizes the dc-link voltage VDL,iat the input of the SPRC-Bm after each pulse. The activebalancing circuit is shown in Fig. 3(a) and (b). This circuitacts as a buck converter where VDL1 is the input voltage andVDL2 is the output voltage, in case VDL1 > VDL2. In contrast,it acts as a buck converter with VDL2 as input voltage andwith VDL1 as the output voltage if VDL1 < VDL2. IGBTs areused for the buck converter because of the hard switching andthe 800-V dc-link. To keep the control simple, the balancingcircuit is operated at the fixed frequency fbal and the fixedduty cycle Dbal in discontinuous conduction mode (DCM).All component values as e.g. the dc-link capacitor CDL,i andthe buck inductance LDL values are given in Table III.

The input voltage charging unit (IVCU) is based on anindustrial power factor correction (PFC) boost converter [12]with an ac-to-dc efficiency > 98%. It is connected to a

standard three phase 400-V grid and provides the 800-V dc-link voltage Vin for the SPRC-Bms.

The voltage sharing between the SPRC-Bms could bebalanced by the control presented in [8] and [9]. The controlleralso performs a droop compensation for a constant pulsevoltage, which compensates the input voltage droop due to thehigh power consumption during the pulse. Furthermore detailsof the different control systems can be found in [8] and [9].

In the following, the optimized components of a singleSPRC-Bm are discussed.

B. Single SPRC-Bm ComponentsThe single SPRC-Bm [see Fig. 4(a)] consists of a water-

cooled full bridge with four semiconductor switches each withsix MOSFETs in parallel.

The required series inductance LS is realized by the sum ofthe leakage inductance of the transformer Lσ and an externalinductance LT [7]. Due to the high switching frequency of100 to 110 kHz and the high resonant peak current of up to1200 Apeak, an air toroid has been designed for the externalinductance LT in order to keep the losses low and to avoid sat-uration effects. The 21 turns winding is made of three parallelconnected litz wires each with 6390 mm × 0.071 mm strands.

The series capacitance CS is implemented by a single–double layered printed circuit board with 896 series/parallel-connected NP0 dielectric ceramic capacitors. The896 capacitors have low losses, are stable over a wide rangeof temperatures and frequencies and also do not suffer fromdc voltage derating.

The parallel capacitance CP [see Fig. 4(b) and (c)] is madeof 216 series- and parallel-connected ceramic capacitors ofthe same type of capacitors as the series capacitance. Theinfluence of the stray capacitance Cd of the transformer isnot considered in the design of CP , because it is negligible(see Table II). The series–parallel connection of k componentparts results in a low total tolerance s(k) = s1/

√k, where s1 is

the tolerance of each of the k-components. This is manda-tory for parallel- and series-connected SPRC-Bm systems,because the component tolerances are significantly influenc-ing the transfer characteristic of the SPRC-Bms and couldlead to unequal power sharing between the parallel-connectedSPRC-Bms [8], [9].

The output rectifier depicted in Fig. 4(b) consistsof 144 diodes in total, where one diode branch consistsof 36 diodes. Each diode branch is made of two printed circuitboards due to the high output voltage. The schematic of theoutput rectifier is depicted in Fig. 4(c) at the left side andhas the same basic behavior as the standard rectifier circuitat the right side. In the left-hand side circuit, the parallelcapacitor CP acts as resonant tank element, as a filter atthe output of the rectifier, and it is additionally utilized tosymmetrize the rectifier diodes voltages.

The high voltage and high frequency (HV-HF) transformeris shown in Fig. 4(d). Litz wire is used for the primary andsecondary winding and ferrite as core material due to thehigh switching frequency. The isolation of the transformer isdesigned with respect to the full output voltage of 115 kV dueto the series connection of the SPRC-Bms. The turns ratio N


Fig. 4. (a) Single SPRC-Bm consisting of the full bridge with sixMOSFETs in parallel for each switch, the series capacitance CS , and theseries inductance L S . (b) Output voltage rectifier and parallel capacitance CP .(c) Schematics of the output rectifier with identical input-to-output behavior.The parallel capacitor CP is additionally used for the voltage balancing ofthe rectifier diodes in the configuration on the left side compared with thestandard circuit on the right side. One diode branch consists of 36 diodesin series with 6 capacitors in series and in parallel for each diode. (d) Highvoltage high frequency transformer.

of the transformer is NS : NP = 20. The detailed design ofthe HV-HF transformer is presented in [10].

Fig. 5(a) shows the loss distribution and Fig. 5(b) shows thevolume distribution of a single SPRC-Bm. The main losses aregenerated in the switches due to the high conduction lossescaused by the high resonant current. Due to the high isolationvoltage of 115 kV, the volume of the transformer is the largestone compared with the other module components, as can beseen in Fig. 5(b).

Fig. 5. (a) Averaged loss distribution. (b) Volume distribution of a singleSPRC-Bm.

TABLE II

OPTIMIZATION RESULTS OF A SINGLE SPRC-BM AND

OPTIMAL NUMBER OF MODULES

In the following, a critical temperature evaluation of thetransformer is given.


TABLE III

PARAMETERS AND COMPONENT VALUES OF THEACTIVE BALANCING CIRCUIT

Fig. 6. Simplified thermal equivalent circuit of the SPRC-Bm transformer,which is shown in Fig. 4(d).

IV. TRANSFORMER TEMPERATURE EVALUATION

Due to the required high isolation voltage of the trans-former (115 kV), it is not possible to directly measure thecritical temperatures inside the transformer during normaloperation. Therefore, the critical transformer temperatures asfor example the temperatures inside the core and the surface ofthe core (T1 and T4) and the temperatures inside the windings(T2 and T3) are estimated with the validated thermal modelgiven in Fig. 6, which is derived in [13] and [14]. It includesthe convective heat transfer from the core and/or the windingsurfaces to the ambient (Rc-amb, Rws-amb, and Rwp-amb) andthe conductive heat transfer inside the transformer, which isrepresented by the thermal resistors of the windings, the coreand the bobbins (Rws, Rwp, Rcl, and Rwp-ws). The lossesof the windings and the core are modeled by equivalentcurrent sources (Pcr, Pcl, Pwp, and Pws). The model has beenverified with measurements of the transformer temperatures,where the transformer has been operated at a reduced outputvoltage Vsec of 3.04 kV in air without isolation oil. Themeasurement system was a Flir ThermoVision A320 thermalcamera [15] and the calculated temperature values have amaximal deviation of +12.5% compared with the measuredvalues as presented in [13].

By replacing the thermal parameters of air with the parame-ters of the isolation oil given in [16], all critical temperaturesduring normal operation can be determined with the model.

In order to determine the ambient (oil) temperature Tamb,which is required for the thermal model, a PT1000 temperaturesensor [17] is used inside the oil tank. The final oil temperaturesettles at approximately 60 ◦C after a heat run test of 7(2/3) h,where both modulator systems from Fig. 1(a) are dissipatingthe transformer and rectifier losses into the oil. The systemswere operated with two separate water-cooled resistive loads(2 × 4.6 k�) at nominal pulse conditions (see pulse specifi-cations in Table I). The oil is cooled by an oil to water heat

TABLE IV

OPERATION POINT AND TEMPERATURES OF THE TEST TRANSFORMER

Fig. 7. Measured oil temperature Ttank,m inside the tank of Fig. 1(a) and theexponentially fit curve Ttank,bf, which is used for extrapolation until a stabletemperature is reached.

exchange system with a water inlet temperature of 21.5 ◦Cand a water outlet temperature of 27.9 ◦C. Fig. 7 shows themeasured oil temperature data Ttank, m, which is used forfitting to the exponential curve Ttank,bf to estimate the steadystate temperature of the oil. Table IV shows the calculatedtemperatures of the transformer, the calculated thermal resistorvalues for the thermal model and the estimated losses of thewindings and the core. A worst case ambient temperature of65 ◦C (measured ambient temperature of 60 ◦C plus a marginof 5 ◦C) is used for the calculations. All critical temperaturesare below 110 ◦C, which is the allowed maximal temperature.

V. MEASUREMENT RESULTS

In the following, the measured output voltage pulse isevaluated with regard to the pulse specifications are givenin Table I.

A. Dynamic Pulse PerfomanceThe modulator system is designed for a nominal output

voltage of 115 kV. The switching frequency is starting at


Fig. 8. (a) Measured output voltage pulse Vout (blue line) and averaged outputvoltage pulse Vout,avg (green line). (b) The zoomed-in view of the beginningof the pulse shows the achieved rise time trise = 107.76 μs. (c) The zoomed-in view of the end of the pulse shows the achieved fall time tfall = 83.48 μs.The areas K1 and K2 represent the part of the transferred energy, which couldnot be used in the klystron load.

103.93 kHz at the beginning of the pulse and is ending at101.24 kHz in order to compensate the decreasing dc-linkcapacitor voltage. Fig. 8(a) shows a measured output voltage

Fig. 9. Zoom of the flat-top of the measured output voltage pulse Vout givenin Fig. 8(a). In addition, the measured averaged output voltage pulse Vout,avg(green line) is shown. The blue part of the flat-top is used for determiningthe ripple spectrum.

pulse, where Vout (blue line) is the output voltage and Vout,avg(green line) is the averaged voltage pulse, which is usedfor calculating the rise time trise and the fall time tfall. TheSPRC-Bms are working interleaved with an interleavingangle κ

κk,m = (k − 1)π

K+ (m − 1)π

M K(1)

and

k = [1 . . . K ], m = [1 . . . M] (2)

where each ISOP stack consists of K = 2 SPRC-Bms andM = 9 of this ISOP stacks are connected in series formingthe IPOS system.

The rise time is trise = 107.76 μs (0 . . . 99% of VK ) [seeFig. 8(b)] and the fall time is tfall = 83.48 μs (100 . . . 10%of VK ) [see Fig. 8(c)]. Both times are well below the givenlimits in Table I. The pulse efficiency ηpulse is the ratio betweenthe ideal rectangular and the real pulse with limited rise andfall time [18]

ηpulse =(

Kideal

Kreal

)· 100% = 96.78% (3)

with

Kideal = VK · (t1 − trise) (4)

Kreal =∫ t2

0Voutdt . (5)

The areas K1 [see Fig. 8(b)] and K2 [see Fig. 8(c)] representthe part of the transferred energy, which is lost\cannot be usedbecause the klystron load can just be initiated at a certain highvoltage level [4]. After the pulse dynamics, the ripple of theoutput voltage pulse in Fig. 8(a) is evaluated in the following.

B. Output Voltage Ripple EvaluationFig. 9 shows a zoomed region of the flat-top of the measured

output voltage pulse of Fig. 8(a). The blue part, which starts


Fig. 10. Ripple spectrum of the analyzed output voltage pulse in Fig. 9.(a) Full spectrum from 0 Hz to 6 MHz. (b) Zoomed-in view of the spectrumfrom 0 Hz to 1 MHz. (c) Zoomed-in view of the spectrum from 0 Hz to10 kHz. The main ripple frequency of the output voltage of a single SPRC-Bmis around 200 kHz. The yellow area indicates the maximum allowed peak topeak ripple voltage for each frequency component, according to Table I.

at trise and ends at t1, is used for calculating the ripple spectrumand results in the lowest resolvable frequency component f1

Fig. 11. Averaged loss distribution of the full-modulator system including thelosses of 18 SPRC-Bms, the IVCU, and the pulse shape losses. The resultingefficiencies are listed in Table V.

TABLE V

SYSTEM EFFICIENCY

of 294.8 Hz with

f1 = 1

t1 − trise. (6)

The measured data is sampled at a rate of 250 MS/s and hasbeen processed with a moving average filter with a cutofffrequency of 104 kHz resulting in Vout,avg. This resultingaveraged voltage gives a good indication for the low frequencyripple during the flat-top (see Fig. 9). The resulting outputvoltage ripple spectrum is depicted in Fig. 10, where anoverview is given for the full spectrum from 0 to 6 MHz[Fig. 10(a)], from 0 to 1 MHz [Fig. 10(b)] and for the lowfrequency range from 0 to 1 kHz [Fig. 10(c)]. It is clearlyvisible that all frequency components are well within the yel-low area, which indicates the maximum allowed peak-to-peakripple voltage for each frequency component (see Table I). Themain switching frequency is around 100 kHz, and becauseof the full wave output rectifier, the main output voltageripple frequency of a single SPRC-Bm is around 200 kHz.Despite the interleaving of all SPRC-Bms, also multiples ofthe 200 kHz appear in the spectrum below 9 × 200 kHz dueto the component tolerances. Fig. 11 shows the averaged lossdistribution of the full-modulator system, including the lossesof 18 SPRC-Bms, the IVCU, and the pulse-shape losses. Themain losses occur in the SPRC-Bms, but also the nonidealpulse shape (see Fig. 8) results in about a third of the losses.


Table V lists the achieved system performance. Thedesigned system easily fulfills the global pulse specifica-tions from Table I and achieves an electrical system effi-ciency ηelec,sys of 91.9% and a pulse system efficiency ηpulse,sysof 89%, which also considers the losses of the nonidealpulse shape. For the entire system 18 SPRC-Bm (2 × 9 unitsconnected in parallel) are required.

VI. CONCLUSION

In this paper, a long-pulse modulator prototype system ispresented and a detailed description of the measured pulseparameters is given. Two SPRC-Bms connected in series atthe input and in parallel at the output forming an ISOP stack.To generate the given output voltage of 115 kV, nine of thisISOP stacks are connected in series. A detailed descriptionof each SPRC-Bm component is presented. Due to the highoperating frequency and the high resonant current, litz wireis used as a winding material for the inductive componentsand six MOSFETs are connected in parallel, forming a switchin each submodule to keep the losses low. All critical tem-peratures of the transformer stay well below 110 ◦C, withan assumed worst case isolation oil temperature of 65 ◦C.The measured output voltage pulses are well within the givenspecification. The achieved rise time of 107.76 μs and theachieved fall time of 83.48 μs result in a pulse efficiencyof 96.78%, an overall electrical system efficiency of 91.9%and a pulse system efficiency of 89%, taking also the lossesdue to the nonideal pulse shape into account.

REFERENCES

[1] M. Kempkes, K. Schrock, R. Ciprian, T. Hawkey, and M. P. J. Gaudreau,“A klystron power system for the ISIS front end test stand,” in Proc.IEEE Int. Vac. Electron. Conf., Apr. 2009, pp. 493–494.

[2] I. S. Roth, R. Torti, M. P. J. Gaudreau, and M. A. Kempkes, “A high-voltage hard-switch modulator for the international linear collider,” inProc. Particle Accel. Conf. (PAC), Jun. 2007, pp. 2301–2303.

[3] H. Pfeffer et al., “A long pulse modulator for reduced size and cost,” inProc. 21st Conf. Power Modulator Symp., Jun. 1994, pp. 48–51.

[4] S. Blume and J. Biela, “Optimal transformer design for ultraprecisesolid state modulators,” IEEE Trans. Plasma Sci., vol. 41, no. 10,pp. 2691–2700, Oct. 2013.

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[6] M. Jaritz and J. Biela, “Optimal design of a modular series parallel reso-nant converter for a solid state 2.88 MW/115-kV long pulse modulator,”IEEE Trans. Plasma Sci., vol. 42, no. 10, pp. 3014–3022, Oct. 2014.

[7] M. Jaritz, S. Blume, D. Leuenberger, and J. Biela, “Experimentalvalidation of a series parallel resonant converter model for a solid state115-kV long pulse modulator,” IEEE Trans. Plasma Sci., vol. 43, no. 10,pp. 3392–3398, Oct. 2015.

[8] M. Jaritz, T. Rogg, and J. Biela, “Analytical modelling and controllerdesign of a modular series parallel resonant converter system for asolid state 2.88MW/115-kV long pulse modulator,” IEEE Trans. PowerElectron., to be published, accessed: Aug. 8, 2017. [Online]. Avail-able: https://people.ee.ethz.ch/jbiela/papers/Journal_EPE_2015.pdf doi:10.1109/TPEL.2017.2785128.

[9] M. Jaritz, T. Rogg, and J. Biela, “Control of a modular series parallelresonant converter system for a solid state 2.88MW/115-kV long pulsemodulator,” in Proc. 17th Eur. Power Electron. Appl. Conf., Sep. 2015,pp. 1–11.

[10] M. Jaritz, S. Blume, and J. Biela, “Design procedure of a 14.4 kV,100 kHz transformer with a high isolation voltage (115 kV),” IEEETrans. Dielectr. Electr. Insul., vol. 24, no. 4, pp. 2094–2104, Sep. 2017.

[11] M. Jaritz and J. Biela, “Optimal design of a modular 11 kW series par-allel resonant converter for a solid state 115-kV long pulse modulator,”in Proc. 19th IEEE Pulsed Power Conf. (PPC), Jun. 2013, pp. 1–6.

[12] Accessed: Apr. 10, 2017. [Online]. Available: http://www.revcon.de/fileadmin/pdf/datenblaetter/RSU_d_DB.pdf

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Michael Jaritz (M’17) was born in Graz, Aus-tria, in 1984. He received the Dipl.-Ing. degree inelectrical engineering from the Graz University ofTechnology, Graz, in 2010. His diploma thesis dealtwith dc voltage link inverters in a power rangeof 500 kW.

In 2011, he joined the High Power ElectronicsLaboratory as a Ph.D. Student, where he is focusingon series-parallel resonant converters which are usedin long pulse modulators generating highly accuratevoltage pulses.

Juergen Biela (S’04–M’06–SM’16) received theDiploma (Hons.) degree from Friedrich-Alexander-Universitaet, Erlangen-Nuernberg, Germany,in 1999, and the Ph.D. degree from the PowerElectronic Systems Laboratory (PES), ETH Zurich,Zürich, Switzerland, in 2006, with a focus onoptimized electromagnetically integrated resonantconverters.

He dealt, in particular, with resonant dc-linkinverters with the University of Strathclyde,Glasgow, U.K., and the active control of series-

connected integrated gate-commutated thyristors with the TechnicalUniversity of Munich, Munich, Germany, during his studies. In 2000,he joined the Research Department of Siemens Automation and Drives,Erlangen, Germany, where he was involved in inverters with very highswitching frequencies, SiC components, and electromagnetic compatibility.From 2006 to 2007, he was a Post-Doctoral Fellow with PES and a GuestResearcher with the Tokyo Institute of Technology, Tokyo, Japan. From2007 to 2010, he was a Senior Research Associate with PES. Since 2010,he has been an Associate Professor of high-power electronic systems withETH Zurich. His current research interests include the design, modeling,and optimization of PFC, dc–dc and multilevel converters with emphasison passive components, and the design of pulsed-power systems and powerelectronic systems for future energy distribution.

http://dx.doi.org/10.1109/TPEL.2017.2785128

system design and measurements of a 115-kv/3.5-ms solid ...€¦ · is permitted. however,...

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