System-level ESD Failure Diagnosis with

Chip-Package-System Dynamic ESD Simulation

Robert(Soung-ho) Myoung*, Byong-su Seol, Norman Chang*

*ANSYS, Inc., 2645 Zanker Road, San Jose, CA 95134 USA

Samsung Electronics Co., Ltd.,416 Maetan 3-dong, Suwon, Korea 443-742

e-mail: {robert.myoung,nchang@ansys.com, byongsu.seol@samsung.com}

Abstract – A comprehensive chip-package-system (CPS) electrostatic discharge (ESD) simulation methodology is developed for addressing IEC61000-4-2 testing conditions. An innovative chip ESD compact model is proposed, combined with full-wave models of the ESD gun, ESD protection devices, PCB wires/vias and connectors for CPS analysis. Two examples of CPS ESD application are illustrated demonstrating good correlation with measurement.

I. Introduction

A modeling and simulation methodology for IEC61000-4-2 [9] compliant system-level ESD testing is outlined in Figure 1. ESD generator is preferred rather than ESD gun in the IEC standard as shown in Figure 1. As stated in reference [1], a realistic IC ESD model has to be used together with the models of ESD

gun/generator, connector, ESD protection element and PCB wires/vias for accurate dynamic system-level ESD simulation. It is also clear from the paper that a realistic chip ESD model is important for accurately predicting voltage/current on the chip pins. Other recent work [2,3,4] focused on the accuracy of the models in terms of ESD gun pulse, protection

elements, PCB traces and of the model against measurement. Moreover, creating a full-wave compliant model for different forms of connectors is difficult and a challenge in system-level ESD simulation. In this paper, we outline a comprehensive Chip-Package-System ESD simulation methodology that addresses the interface modeling between an ESD gun and system, as well as between the system and IC chip(s).

Figure 1: Modeling components needed in PCB ESD

simulation, courtesy of IEW 2010 [1].

II. CPS ESD Simulation Methodology This paper outlines a comprehensive Chip-Package-System (CPS) ESD dynamic methodology intended to achieve the following goals:

1. Provide a realistic view of voltage/current versus time on the chip pins through accurate modeling and simulation of the CPS ESD prior to hardware availability.

2. Perform diagnosis of potential failure mechanisms when CPS ESD failures occur.

3. Verify robustness of an ESD fix by comparing

differential voltage/current values against maximum safe thresholds on the IC chip(s) pins with hard or soft failure.

In section III we describe modeling methods for

various components in CPS and the integrated simulation used to achieve these goals. We specifically focus on the full-wave modeling needed for a connector and its interface to the ESD gun pulse

model, and the realistic, compact chip modeling methodology that will provide accurate V(t) and I(t) on the chip pins. Once the V(t) and I(t) are obtained, chip-level static or dynamic ESD simulation can be performed [5,6]. Two realistic application examples are provided in section IV.

III. Modeling for CPS ESD Simulation

Various models needed for achieving well correlated Chip-Package-System ESD simulation are described in detail below.

A. Chip ESD Compact Model A Chip ESD Compact Model (CECM) (Figure 2) is an accurate and compact representation of a die. It contains a passive RC(L) model, scenario-specific

current signature models of ports [7], and models of optional ESD protection elements (e.g. diodes and RC-based clamps). For the passive model, the total capacitance (i.e. Cdie) of a power/ground domain pair includes power/ground coupled capacitance, intentional decap, device intrinsic capacitance, and capacitance from non-switching cells and their C-loads. Because the ESD spectrum is broadband, the

die model must be accurate in the GHz range. Therefore a reduced RC or RLC network model of the die is included.

Figure 2: Chip ESD Compact Model (CECM)

The Chip ESD Compact Model enables users to perform various "what if" analysis, such as leaving the on-chip ESD protection in or out to see how the PCB ESD protection performs in PCB ESD simulation. Without on-chip ESD protection elements in CECM,

the V(t) and I(t) on the chip pin (or pad) will become the energy that is propagated through the connector/PCB/on-board ESD protection elements. In general the larger the Cdie, the smaller the amplitude of voltage/current at the chip pins. Since this is a power-on PCB ESD simulation, voltage and/or current amplitude should not be excessive at the chip

pins. When running a PCB ESD simulation with chip ESD protection elements in CECM, the V(t) and I(t) of the chip pins will be reduced accordingly, and may not easily reveal the inefficiency of the ESD protection designs at the PCB level.

B. ESD Gun Zap Modeling

ESD generators are used for testing the robustness of electronics subjected to ESD effects. There are two different discharge methods for an ESD simulator, and this paper will replicate a contact discharge mode

ESD generator modeling [8,10] as shown in Figure 3.

(a) Measured and simulated current discharge wave

(b) HFSS ESD Gun Model with Transient Solver

Figure 3-1: HFSS ESD Gun Model and simulation

results.

Figure 3-2: ESD Gun current propagation

C. TVS Diodes, CMF/EMI/ESD Filter

Commercial Transient Voltage Suppressor (TVS) diode vendors provide model parameters in their data sheets. ANSYS DesignerSI provides a model for the TVS diodes that is dependent on input parameters from the datasheet, as illustrated in Figure 4-1.

Figure 4-1: TVS diode modeling.

A typical piecewise linear curve as the ones reported in Figure 4-2 could provide sufficient information[12] for diode behaviour. For example, only two I-V points

could describe a simple Diode (piecewise linear 2). Additional points could be added (piecewise linear 3 to n) to more accurately represent the behavior of the diodes. For snapback devices, using the information related to snapback ensures representation of the sudden break point in the I(V) curve.

Figure 4-2: Piecewise linear description of I(V) from

TLP measurements

TVS protection circuit with Spice modeling as shown

in Figure 4-3 can be used to analyze a system’s EOS/ESD issue against surge current/voltages.

Zener and TVS avalanche diodes have similar electrical characteristics; however, there are significant differences between the two devices. A

Zener diode is designed to regulate a steady-state voltage, while a TVS diode is designed to clamp a transient-surge voltage.

TVS diodes typically have a larger junction area than a standard Zener diode, which provides the ability to

absorb high peak energy. The spice level current versus voltage relationship of a TVS diode is shown in Figure 4-4 as an example and it can be modeled many different ways to address real TVS diode behaviors.

In order to do accurate prediction of the ESD current propagation, we have to consider the temperature dependent characteristic for component as well as for PCB.

Simplorer and DesignerSI/RF support diode

parameters such as “nz” and “tnom” which are not usually supported by other Spice simulators. Temperature dependent current distribution or temperature dependent PCB joule heating can also be modeled in SIwave.

Figure 4-3: Spice Model of TVS Diode.

Figure 4-4: Spice Level TVS diode’s I-V characteristics.

For snapback protection modeling, 4 states are

defined and reported on the measured I(V) curves

(following the state diagram reported in the Figure 4-

5). Six pairs of voltages and currents are defined as

parameters. The number of points to define the

structure can be extended if needed[13]. These

(Vx,Ix) pairs define the inflection points of the silicon

controlled rectifier (SCR) and the equivalent

equations for the states 0, 1, 2 and 3. The model has

been used in previous works for simulation of ESD

stress injection (TLP and IEC 61000-4-2). An

example of TVS Diode I-V Point pair in Figure 4-6

and the VHDL-AMS code in Figure 4-7 shows the

dynamic aspect of the protection function in system

level TVS Diode modeling. VHDL-AMS code base

TVS diode modeling result is shown in Figure 4-8.

(a) Piecewise linear I(V) characteristic

(b) State Diagram

Figure 4-5: Piecewise linear I(V) characteristic and

State Diagram.

Figure 4-6: TVS Diode I-V points pair.

Figure 4-7: VHDL AMS Model for TVS Diode.

Figure 4-8: TVS snapback I-V curve.

Using DesignerSI a parameterized 3D FEM model

with manufacturing tolerance can be created for an ESD filter in the full-wave 3D FEM solver (ANSYS HFSS). This model can be directly plugged into the circuit simulation tool as an EM-based parametric model of a component and verified with measured result as shown in Figure 5.

Figure 5: ESD Filter Modeling Results.

(Gray: Measured, Red: Simulation)

A typical EMI filter model will have an approximate

frequency dependent equivalent circuit as displayed in Figure 6. In general, for common mode filters or chokes, as frequency increases, the impedance and distortion will increase. Therefore the effects of the common mode choke on full-speed and high-speed

signal quality should be tested.

(a) Component SpecSpec

(b) Modeling Results

Figure 6: Common Mode EMI/Noise Filter Modeling.

D. Connector and PCB Modeling

By using push excitation with HFSS Transient solver, a good electrical representation of PCB interconnects with ESD discharge current can be obtained. Figure 7 shows the actual board implementation of a mobile

PCB including USB receptacle on the right top corner, signals, power/ground networks, and results of 3D FEM Transient simulation. The USB Connector grounds are directly attached to the PCB GND and the ESD current is injected on the Micro USB connector shield. The ESD current propagation is captured in nano-second units.

Figure 7: ESD current injection on Micro USB

Connector and its propagation.

IV. Application Examples

Efficient ESD design for a system calls for recognizing energy entering into the interface IC pin in terms of a residual pulse. A typical implementation of a USB2 interface is shown in Figure 8 as the first application example. System-level ESD protection is primarily ensured with an external TVS, CMF/EMI filter, and/or ESD filter.

As secondary protection, IC pins have their own respective on-chip ESD protection that meets the requirements of both Human Body Model (HBM) and

Charged Device Model (CDM). The IC1 in the PCB schematic in Figure 8 shows differential pins for the USB that need protection using a TVS device. As will

be discussed here, the Common Mode Filter (CMF) plays an important role in overall protection efficiency. CMF is primarily intended to filter Common Mode noise that results from two phase lags between the differential signals (either unequal PCB

trace lengths or unequal loadings), or from EMI pick-up through a USB cable. All of these protection devices have parasitic capacitance that will affect high-speed signal leading to greater distortion. The optimal placement of components in Figure 8 determines the effectiveness of ESD protection while having minimum impact on signal integrity.

Figure 8 shows the actual board implementation for IEC protection. It includes the Processor IC, the TVS diode, EMC filter or CMF, board traces, and the USB

receptacle on the left. Most of the USB signals are routed within inner layers in a strip-line configuration to minimize cross-talk between the traces and coupling from radiation sources such as RF chips and/or the ESD gun. The EMI Filter is placed after the TVS, precisely between the TVS and Processor IC. The TVS is placed just behind the receptacle. The PCB interconnect from the TVS to the Processor IC is about 5.5 cm long.

Figure 8: Typical implementation of a USB2 interface.

Figure 9: Demonstrates the simulation method and the

resulting residual voltage waveform (blue curve) at the

IC pin when the connector shield is stressed with the ESD discharge current (red curve) from the 5kV ESD

gun model.

CPS transient simulations, performed to determine the residual pulse voltage/current waveform at the IC pin is shown in Figure 9. The simulation takes into account the TVS, PCB interconnects, passive devices, and CECM. We injected the 5kV ESD discharge current waveform (red curve) on the USB connector shield (120Vp @ USB connector ground) and

detected a residual voltage pulse on the processor IC input signal trace, 2.78Vp (blue curve).

Another example demonstrates ESD propagation

modeling [11] with a return ground path effect as shown in Figure 10. This return path impacts ESD propagation on PWR, GND and the signals. In this model, we intentionally selected the SLC line on the Mobile PCB to see how the return ground path effect would depend on the impedance variation ranging from the zero ohm to hundreds of ohms.

Figure 10: System-level ESD waveform propagation

modeling.

When we perform System-level ESD waveform propagation modeling, discharge current will be discharged at “Probe Point A” and we will detect propagated current or voltage at “Probe point B” in ideal case. In a real world design and measurement, it

is IC pin or packge bump location and it is impossible to probe current /voltage without breaking it. When we use software to do virtual prototyping for System-level ESD, we do not have such limitation like measurements.

With zero ohm reference return current path, we get 42.5uV on SLC node1. With one ohm return ground path impedance, we get 2.7V on SLC node1, which is large enough to create ESD damage on the SMD containing SLC nodes (Figure 11). Figure 12 shows chip pin V(t) with different chip Cdie in CECM(s). This gives designers an insight on whether to put

more ESD protection on PCB or on-chip.

(a)42.5uVp @ 0ohm

(b)2.7Vp @ 1ohm

(c) 11Vp @ 5ohm GND

(d) 60Vp @ 100ohm

Figure 11: ESD propagation modeling result at SLC nodes with various Reference GND effect.

Figure 12: Chip pin V(t) in CPS ESD simulation with CECMs containing different Cdies.

V. Experimental Verification

The ESD discharge current waveform injected by the

ESD generator and the voltage waveform on the

processor IC input signal trace are measured to

validate the simulation results as shown in Figure

13(a). The injected current waveform is measured

using a test board and a current probe shown in Figure

13(b). Figure 13(c) shows the simulation result (red

line) for ESD current waveform compared with the

measurement result (blue line). As seen from Figure

13(c), the first and second peak current match well

with the measured data.

Figure 13: ESD discharge current waveform

measurement: (a) measurement setup; (b) current probe

setup; (c) measured and simulation result.

The voltage waveforms across the TVS and CMF are

measured using a custom designed test board with

three TVS diodes and a mounted CMF as shown in

Figure 14. To measure the voltage waveform, 5kV

ESD current was discharged on signal pin, two 50

ohm coaxial cables were used to connect the test

board (via SMA connection) to the oscilloscope with

an Attenuator(1/100) and ferrite beads. Five zero Ohm

registers are used for ground connection between test

DUT to bottom GND Plate.

Figure 14: Test board and measurement setup.

Figure 15 shows measured and simulated voltage

waveforms correlation on the controller IC input

signal trace via SMA Connector. Since we are using

Attenuator, actual measured peak to peak voltage is

22V.

(a)

(b)

Figure 15: IC input signal trace with SMA Probe

connection (a) Measured (Sky Blue) and Simulated

(Orange) voltage waveform: (b) on the Controller side SMA connector.

VI. Summary

We outlined a comprehensive Chip-Package-System ESD simulation methodology for diagnosis and

predictive simulation of PCB ESD discharging events, particularly for IEC61000-4-2 testing. This includes 3D full-wave connector modeling addressing the interface modeling between the ESD gun and system, and the interface modeling between the system and the IC chip(s) using CECM (Chip ESD Compact Model) representing a realistic chip impedance and

current macro-model. Good correlation with measured values were illustrated using two design examples with realistic CPS ESD models and running what-if analysis on 1) different CECMs on Cdie values and 2) different ground impedances with various ESD protection devices that include TVS diode, Varistor, ESD filter and Common Mode EMI/Noise Filter.

Acknowledgements

The Authors would like to thank Zuken (Naoyuki Sugaya) and Ansys Japan (Akira Ohta), respectively for the PCB Layout support. Hyungseok Lee and Jongsung Lee of Samsung Electronics for building the test fixture and help with performing the tests. We also would like to thank Dr. Seung-il Jung (CTO of Huwin), Robert Ashton, and ESDA “System Level

ESD Modeling Team” for their helpful comments and numerous discussions about modeling. We would also like to thank S. Rousselle, D. Soldo, S. Lin, Y. Cao, Y. Liao, J. Zheng, R. Ravikumar, D. Yang, and A. Yang for providing supports and continuous discussions on solving real world ESD problems.

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