SYSTEM-LEVEL TEST TECHNIQUESSYSTEM-LEVEL TEST TECHNIQUES

INTRODUCTIONINTRODUCTION • In the 1970s, the in-circuit testing (ICT) method appeared.In the 1970s, the in-circuit testing (ICT) method appeared.• Mechanical testing becomes difficult with board trace Mechanical testing becomes difficult with board trace

widths ard separations widths ard separations • below 0.1 mm or 100 Jam.below 0.1 mm or 100 Jam.• In 1985 a group of European manufacturer formedthe Joint In 1985 a group of European manufacturer formedthe Joint

European Test Action Group (JETAG) to study board testing.European Test Action Group (JETAG) to study board testing.• In 1986 JETAG becomes Joint Test Action Group (JTAG) with In 1986 JETAG becomes Joint Test Action Group (JTAG) with

the addition of North American Companies.the addition of North American Companies.• The main virtue of the 1149.1 standard can be used by The main virtue of the 1149.1 standard can be used by

board designers, IC designers, and systems dejgners.board designers, IC designers, and systems dejgners.• without the need for members of each design community to without the need for members of each design community to

fully understand the testing problems of the other fully understand the testing problems of the other communities.communities.

BOUNDARY SCANBOUNDARY SCAN

• Boundary scan is actually a collection of design rules, Boundary scan is actually a collection of design rules, applied at the IC level for testing hoards using a four-wire applied at the IC level for testing hoards using a four-wire interface (five wires with an optional master reset signal). interface (five wires with an optional master reset signal).

• Boundary scan provides the following major modes of Boundary scan provides the following major modes of operation:operation:

• These resources enable asynchronous communication with These resources enable asynchronous communication with the outside world to serially read in test data and the outside world to serially read in test data and instructions or serially read out test results.instructions or serially read out test results.

• The activities are invisible to the normal IC behaviour.The activities are invisible to the normal IC behaviour.• The pin-permission modes of the standard take control of The pin-permission modes of the standard take control of

the IC input/output pins, thus disconnecting the system logic the IC input/output pins, thus disconnecting the system logic from the outside world. from the outside world.

• These modes allow testing of the system interconnect These modes allow testing of the system interconnect separately from component testing.separately from component testing.

• And also allow testing of components separately from And also allow testing of components separately from system interconnect testing. system interconnect testing.

• The testing actvities totally disrupt the normal IC behaviour.The testing actvities totally disrupt the normal IC behaviour.

SYSTEM CONFIGURATION WITHBOUNDARY SCANSYSTEM CONFIGURATION WITHBOUNDARY SCAN• It is integrated circuit that is complaint with the 1149.1 boundary-scan It is integrated circuit that is complaint with the 1149.1 boundary-scan

standard. standard. • Note that on each pin of the chip, there is internal hardware that provides Note that on each pin of the chip, there is internal hardware that provides

a register dt that pin position.a register dt that pin position.• The serial connection of these registers around the periphery of the chip The serial connection of these registers around the periphery of the chip

at the pins is known as the at the pins is known as the boundary registerboundary register• The input to a boundary-scan shift register is the test-data input (TDI).The input to a boundary-scan shift register is the test-data input (TDI).• The output of a boundary-scan shift register is the test-data output (TDO).The output of a boundary-scan shift register is the test-data output (TDO).• . The boundary-scan shift register in each IC is one of several test-data . The boundary-scan shift register in each IC is one of several test-data

registers (TDR) that may included in each IC. registers (TDR) that may included in each IC. • All the TDRs in an IC are connected dirctIy between the TDI and TDO ports. All the TDRs in an IC are connected dirctIy between the TDI and TDO ports. • • • The Device ID register provides the device identification.The Device ID register provides the device identification.• • • The bypass register bypasses the boundary register for this component. The bypass register bypasses the boundary register for this component.

This is useful when all boundary registers of all components on the PCB This is useful when all boundary registers of all components on the PCB are chained together into one long shift registers, and it is desired to are chained together into one long shift registers, and it is desired to reduce the length of the register by ignoring hardware on components reduce the length of the register by ignoring hardware on components that are not involved in the current test.that are not involved in the current test.

SCHAMATIC OF SYSTEM TEST LOGICSCHAMATIC OF SYSTEM TEST LOGIC

BST CELLSBST CELLS

• That may be used to implement any of the TDRs. That may be used to implement any of the TDRs. • The most common DR cell is a boundary-scan cell. The most common DR cell is a boundary-scan cell. • A BSC contains two sequential elements. A BSC contains two sequential elements. •

(i) The capture flip-flop or capture register formed by series Connection of (i) The capture flip-flop or capture register formed by series Connection of BCs. BCs.

•(ii) The update flip-flop, or update FF Latch is an edge-triggered D flip-flop. (ii) The update flip-flop, or update FF Latch is an edge-triggered D flip-flop.

THE INPUTS TO A BSTARE:THE INPUTS TO A BSTARE:

• • • Scan in (serial in or SI)Scan in (serial in or SI)

• • • data in (parallel in or P1)data in (parallel in or P1)

• • • Control signal, mode (also called test/normal).Control signal, mode (also called test/normal).

• THE BST OUTPUTS ARE:THE BST OUTPUTS ARE:

• • • Scan out (serial out or SO)Scan out (serial out or SO)

• • • data out (parallel out or P0)data out (parallel out or P0)

• The sequential logic in a BSC controlled by the The sequential logic in a BSC controlled by the gated clocks: clockDR and updat)R.gated clocks: clockDR and updat)R.

BYPASS-REGISTER CELL BYPASS-REGISTER CELL (BR)(BR)

• The BR inputs and outputs, The BR inputs and outputs, • SCANSCAN• in (serial in, SI) and scan out (Serial out, SO), have the same names as the DR cell in (serial in, SI) and scan out (Serial out, SO), have the same names as the DR cell

ports,ports,• but DR cells and BR cells are not directly connected.but DR cells and BR cells are not directly connected.

• INSTRUCTION - REGISTER CELLINSTRUCTION - REGISTER CELL• THE JR CELL INPUTS ARE:THE JR CELL INPUTS ARE:

• • • scan inscan in• • • data_indata_in• • • ClockClock• • • Shift Shift •

• • update signals update signals •

• • reset signals reset signals

• INSTRUCTION-REGISTER CELL (IR)INSTRUCTION-REGISTER CELL (IR)•

The The two LSBs of data_in must permanently be set to ‘01’ this helps two LSBs of data_in must permanently be set to ‘01’ this helps in checking the integrity of the scan chain during testing. in checking the integrity of the scan chain during testing.

• The update sequential element in each JR cell may be set or reset The update sequential element in each JR cell may be set or reset depending on reset_value.depending on reset_value.

• The JR cell outputs are: The JR cell outputs are: •

• • data_out (the instruction bit passed to the instruction decoder). data_out (the instruction bit passed to the instruction decoder). • scan_out (the data passed to the next JR cell in the IR) • scan_out (the data passed to the next JR cell in the IR)

•The instruction register has to be at least two bits long which are The instruction register has to be at least two bits long which are decoded with the following instruction. decoded with the following instruction.

•• • BYPASS This instruction is represented by an JR having all the bit BYPASS This instruction is represented by an JR having all the bit positions to be zero. It is used to bypass any serial- data registers in positions to be zero. It is used to bypass any serial- data registers in a chip with a 1-bit register. This allows specific chips to be tested in a chip with a 1-bit register. This allows specific chips to be tested in a serial-scan chain without having to shift throught the accumulated a serial-scan chain without having to shift throught the accumulated SR stages in all the chips.SR stages in all the chips.

•

• • • EXTEST, external test — This instruction is represented by JR having all the bit EXTEST, external test — This instruction is represented by JR having all the bit positions to be one. Drives a known value onto each output pin to test connections positions to be one. Drives a known value onto each output pin to test connections between JCs. between JCs.

•• • SAMPLE/PRELOAD — Performs two functions: first sampling the present input value SAMPLE/PRELOAD — Performs two functions: first sampling the present input value from input pad during capture; and then preloading the BSC update register output from input pad during capture; and then preloading the BSC update register output during update. during update.

•• • IDCODE —. An optical instruction that allows the device-identification to be shifted IDCODE —. An optical instruction that allows the device-identification to be shifted out. out.

•• • INTEST .— This instruction allows for single-step testing of internal circuitry via the INTEST .— This instruction allows for single-step testing of internal circuitry via the boundary-scan registers. boundary-scan registers.

•• • RUNBIST — This instruction is used to run internal self-testing procedures within aRUNBIST — This instruction is used to run internal self-testing procedures within a

• The data bit may be directed to internal circuitry in the INTEST Or RIJNBIST modes The data bit may be directed to internal circuitry in the INTEST Or RIJNBIST modes (Mode=1). When mode=0, the cell is in EXTEST or (Mode=1). When mode=0, the cell is in EXTEST or SAMPLEIPRELOAD SAMPLEIPRELOAD mode. mode.

•

TAP CONTROLLERTAP CONTROLLER

• The following figure is TAP controller finite-state machine.The following figure is TAP controller finite-state machine.

• The Suffix The Suffix ‘—DR’ ‘—DR’ operate on the data registers and those with operate on the data registers and those with suffix ‘—IR’ apply to the instruction register.suffix ‘—IR’ apply to the instruction register.

• All transitions between states are determined by the TMS (test All transitions between states are determined by the TMS (test

mode select) signal and occur at the rising edge of TCKmode select) signal and occur at the rising edge of TCK. .

BOUNDARY SCAN BOUNDARY SCAN DESCRIPTION LANGUAGEDESCRIPTION LANGUAGE

• The Boundary scan Description Language The Boundary scan Description Language (BSDL) was added to the JTAG Boundary (BSDL) was added to the JTAG Boundary scan standard to provide a standard scan standard to provide a standard means of communicating information means of communicating information about the boundary scan hardware on a about the boundary scan hardware on a chip to users of the chip and to CAD tools chip to users of the chip and to CAD tools through the VHDL hardware description through the VHDL hardware description language.language.

• BSDL can b used by automatic test-pattern BSDL can b used by automatic test-pattern generator to generate chip test pattern, generator to generate chip test pattern, and by high-level and logic synthesis tools and by high-level and logic synthesis tools to synthesize test logic. to synthesize test logic.

An active-low reset signal. An active-low reset signal. TRST resets the state machine TRST resets the state machine to the initial state. to the initial state.

• reset: reset: Resets the JR to IDCODE Resets the JR to IDCODE • Select -IR: Select -IR: Connects a register, the IR or a Connects a register, the IR or a

TDR, to TDO TDR, to TDO • Shift4R: Selects the serial input to the Shift4R: Selects the serial input to the

capture flip-flop in the JR cells. capture flip-flop in the JR cells. update-IR: update-IR: update the sequential element on the update the sequential element on the positive edge of positive edge of TCK. TCK.

• • • EXIT-IR: EXIT-IR: unknown or dirty signal. unknown or dirty signal. • • • ShiftDR, Update-DR: ShiftDR, Update-DR: Same functions as Same functions as

corresponding JR signals applied to the TDRcorresponding JR signals applied to the TDR

THANKING YOUTHANKING YOU

• Present Present by by

• soundersounder