system-level trade-off of networks-on-chip architecture choices network-on-chip system-on-chip...
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System-level Trade-off of Networks-on-Chip Architecture
Choices
Network-on-Chip
System-on-Chip Group, CSE-IMM, DTU
© System-on-Chip Group, CSE-IMM, DTU
2
Motivation
a b c
1 os
3
4
os HdSmapping
App
licat
ion
Mid
dlew
are
Har
dwar
e
System-on-ChipNetwork
Tasks and their dependencies
1
4
3
52
a c
Network
b
2
5
© System-on-Chip Group, CSE-IMM, DTU
3
System-level Analysis
Ω Consequences of different application decomposition and mappings of tasks to processors – software or hardware
Ω Effects of different middleware – scheduling, synchronization and resource allocation policies
Ω Effects of different network topologies and communication protocols.
© System-on-Chip Group, CSE-IMM, DTU
4
Outline
Ω MotivationΩ Modeling of Communication
Properties of Networks-on-Chip (NoC)Ω ExampleΩ Design Space Exploration
Timing Aware and othersΩ Conclusions
© System-on-Chip Group, CSE-IMM, DTU
5
Modeling of Communication
a b
21
1
2
a
b
a b
BUS
1 2BUS
1
2
a
b
BUS
L1
R1
L2R2
R3L4 L3
ba
1 2
NoC
R1L1
R2L2
R3
1a
b
R1
L1
R2
L2
R3
2
Point-to-pointNetworks-on-Chip
(eg. Mesh)BUS
NoC combines multi-hop, concurrency and sharing
© System-on-Chip Group, CSE-IMM, DTU
6
System Analysis Methodology
Choose hardware
Map tasks
Choose communication architecture
Evaluate the performance and cost
Iterate until performance and cost are met
Optimal System!!
Specifically for NoC
© System-on-Chip Group, CSE-IMM, DTU
7
Networked Multi-processors
Ω Data transfers between processors are considered as message tasks
Ω The network can be considered as a communication processor on which message tasks are scheduled
Ω The network provides,Topology = resource allocatorProtocol = scheduler
© System-on-Chip Group, CSE-IMM, DTU
8
Design Space Explorationz
Tasks and their dependencies
2x
y
5
4
1
3
ba c
4
2
3
1
5Z
Y
X
Network??
Allocation Aware
ba c
4
2
31
5Z
YX
Network??
Timing Aware
Simple MPSoC Example• 5 Identical Tasks• 3 Inter-task Dependencies• 3 Identical Processors• Unknown Network!!
© System-on-Chip Group, CSE-IMM, DTU
9
Timing Aware
bus
b
a
c
BUS
1
4
3
2
5
xy z
R1 R2 R3L1 L2
L3
L1
L2
b
a
c
L3
2
4
3
x
x
5
1
z
y
L1
L2
b
a
c
L3
2
4
3
1
5
x
y
z
z
X: R1,L3,R3,L2,R2Y: R3,L2,R2Z: R1,L3,R3
zTasks and their dependencies
2
x
y
5
4
1
3
PEa: 1 & 2
PEb: 3
PEc: 4 & 5
X: R1,L1,R2Y: R3,L2,R2Z: R1,L1,R2,L2,R3
X: BUSY: BUS Z: BUS
TORUS MESH BUS
8 8 8
L4
L1 L2
L3
R3R2R1
X: R1,L3,R3,L2,R2Y: R3,L2,R2Z: R1,L3,R3
X: R1,L3,R3,L2,R2Y: R3,L2,R2Z: R1,L3,R3
© System-on-Chip Group, CSE-IMM, DTU
10
Deadline-based Performance
b
a
c
bus
1
4
3
2
5
xyz
L1
L2
b
a
c
L3
2
4
3
1
5
x
y
z
zL1
L2
b
a
c
L3
1
4 5
3
2
x
x
z
y
QoS AwareAny traffic from “a” has higher priority
Timing AwarePEa: 1 & 2PEb: 3PEc: 4 &5
L3L4 y xz
b
a
c
bus
1
4
32
5
zyx
L1
L2
b
a
c 1
4
32
5
z
L1
L3
b
a
c 1
4
32
5
z
xx
xy
Allocation AwarePEa: 2 & 3PEb: 4 &5PEc: 1
b
a
c
bus
1
4
3
2
5
xy z
L1
L2
b
a
c
L3
2
4 5
3
1
x
x
z
y
L1
L2
b
a
c
L3
2
4
3
1
5
x
y
z
z
TORUS MESH BUS
© System-on-Chip Group, CSE-IMM, DTU
11
Power Profile
Timing AwarePEa: 1 & 2PEb: 3PEc: 4 &5
L4
b
a
c
bus
1
4
32
5
zyx
L3
b
a
c
L3 z
L1
L2
b
a
c 1
4
32
5
zx
xy
Allocation AwarePEa: 2 & 3PEb: 4 &5PEc: 1
b
a
c
bus
1
4
3
2
5
xyz
L1
L2
b
a
c
L3
1
4 5
3
2
x
x
z
y
QoS AwareAny traffic from “a” has higher priority
b
a
c
bus
1
4
3
2
5
xy z
L1
L2
b
a
c
L3
2
4 5
3
1
x
x
z
y L2
b
a
c
L3
TORUS
L1
L2
b
a
c
L3
2
4
3
1
5
x
y
z
z
y x
L1
1
4
32
5
z
x
L1
2
4
3
1
5
x
y
z
z
MESH BUS
Deadline-based Performance
© System-on-Chip Group, CSE-IMM, DTU
12
Power Profile
L3
L1
L2
b
a
c
z
1
4
32
5
zx
xy b
a
c
bus
1
4
3
2
5
xy z
TORUS BUS
Deadline-based Performance
= 100 power unit = 10 power unit
Power Profile power
units
84.61 power-units/cycle 66.25 power-units/cycle
© System-on-Chip Group, CSE-IMM, DTU
13
Power Profile over 3 Period
Torus
Bus
~4 cycles faster
Torus is faster but causes power spikes!!!
250%
201%
© System-on-Chip Group, CSE-IMM, DTU
14
Conclusions
Ω System-level modeling framework which combines application, middleware and execution platform
Ω Extension to model network-on-chipΩ Example
System-level trade-off analysis Early design space exploration
Ω Work in progressFind real application for evaluation!!