System-On-a-Chip (SoC)

Design

Dr. Eng. Amr T. Abdel-Hamid

ELECT 1002

Spring 2009

System-On-a-Chip Design

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SoC Design

Digital System v. Embedded System

� Digital SystemDigital SystemDigital SystemDigital System: may provide service

� as a self-contained unit (e.g., desktop PC)

� as part of a larger system (e.g., digital control system for manufacturing plant)

� Embedded SystemEmbedded SystemEmbedded SystemEmbedded System:

� part of a larger unit

� provides dedicated service to that unit

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Embedded Systems Overview (cont.)

� Embedded computing systems

� Computing systems embedded within electronic devices

� Hard to define. Nearly any computing system other than a desktop computer

� Billions of units produced yearly, versus millions of desktop units

� Perhaps 100s per household and per automobile

Computers are in here...

and here...

and even here...

Lots more of these,

though they cost a lot

less each.

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SoC Design

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SoC Design

Some Common Characteristics

� Single-functioned

� Executes a single program, repeatedly

� Tightly-constrained

� Low cost, low power, small, fast, etc.

� Reactive and real-time

� Continually reacts to changes in the system’s environment

� Must compute certain results in real-time without delay

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SoC Design

SOC Paradigms

� A System-on-Chip (SoC) is a blend of software and silicon hardware components intended to perform a pre-defined set of functions in order to serve a given market. Examples are SoCs for cell phones, DVD players, ADSL line cards or WLAN transceivers.

� Embedded systemEmbedded systemEmbedded systemEmbedded system on 1111 CHIPCHIPCHIPCHIP = SOCSOCSOCSOC WHY WHY WHY WHY 1111 CHIP?!CHIP?!CHIP?!CHIP?!

� SOC (System-On-a-Chip)

� Millions of gates on a chip

� Decreasing processing technologies (deep sub-micron, 0.25 µm and below): decreasing geometry size, increasing chip density

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SOC Examples

� Game consoles

� Mobile phones

� Telecommunication Systems

� Routers

Credits to Intel Cooperation

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SoC Design

Smart Dust Project: SoC Example

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SoC Design

An Embedded System Example

Microcontroller

CCD preprocessor Pixel coprocessorA2D

D2A

JPEG codec

DMA controller

Memory controller ISA bus interface UART LCD ctrl

Display ctrl

Multiplier/Accum

Digital camera chip

lens

CCD

� Single-functioned -- always a digital camera

� Tightly-constrained -- Low cost, low power, small, fast

� Reactive and real-time -- only to a small extent

� Digital Camera

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Design Challenge – Optimization

� Obvious design goalObvious design goalObvious design goalObvious design goal:

� Construct an implementation with desired functionality

� Key design challenge:

� Simultaneously optimize numerous design metricsdesign metricsdesign metricsdesign metrics

� Design metric

� A measurable feature of a system’s implementation

� Optimizing design metrics is a key challenge

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SoC Design

Design Challenge – Optimization (cont.)

� Common metrics:

� Unit costUnit costUnit costUnit cost: the monetary cost of manufacturing each copy of the system, excluding NRE cost

� NRE cost (NonNRE cost (NonNRE cost (NonNRE cost (Non----Recurring Engineering cost):Recurring Engineering cost):Recurring Engineering cost):Recurring Engineering cost): The one-time monetary cost of designing the system

� SizeSizeSizeSize: the physical space required by the system� PerformancePerformancePerformancePerformance: the execution time or throughput of the system� PowerPowerPowerPower: the amount of power consumed by the system� FlexibilityFlexibilityFlexibilityFlexibility: the ability to change the functionality of the syste

m without incurring heavy NRE cost

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SoC Design

Design Challenge – Optimization (cont.)

� Common metrics (continued)

�TimeTimeTimeTime----totototo----prototypeprototypeprototypeprototype: the time needed to build a working version of the system

�TimeTimeTimeTime----totototo----marketmarketmarketmarket: the time required to develop a system to the point that it can be released and sold to customers

�MaintainabilityMaintainabilityMaintainabilityMaintainability: the ability to modify the system after its initial release

�Correctness, safety, ………………………

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SoC Design

Time-to Market

� Time required to develop a product to the point it can be sold to customers

� Market window

� Period during which the product would have highest sales

� Average time-to-market constraint is about 8 months

� Delays can be costly

Revenues ($)

Time (months)

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Delayed Market Entry

� Simplified revenue model

� Product life = 2W, peak at W

� Time of market entry defines a triangle, representing market penetration

� Triangle area equals revenue

� Loss

� The difference between the on-time and delayed triangle areas

On-time Delayed

entry entry

Peak revenue

Peak revenue from

delayed entry

Market

riseMarket

fall

W 2W

Time

D

On-

time

DelayedRevenues ($)

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SoC Design

NRE and Unit Cost Metrics

� Costs:� Unit cost: the monetary cost of manufacturing each copy of the system, exclu

ding NRE cost

� NRE cost (Non-Recurring Engineering cost): the one-time monetary cost of designing the system

� total cost = NRE cost + unit cost * # of units� per-product cost = total cost / # of units

= (NRE cost / # of units) + unit cost

• Example

– NRE=$2000, unit=$100

– For 10 units

– total cost = $2000 + 10*$100 = $3000

– per-product cost = $2000/10 + $100 = $300

Amortizing NRE cost over the units results in an additional $200 per unit

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SoC Design

NRE and unit cost metrics

� Compare technologies by costs -- best depends on quantity

� Technology A: NRE=$2,000, unit=$100

� Technology B: NRE=$30,000, unit=$30

� Technology C: NRE=$100,000, unit=$2

• But, must also consider time-to-market

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Design Productivity Exponential Increase

� Exponential increase over the past few decades

100,000

10,000

1,000

100

10

1

0.1

0.01

1983

1987

1989

1991

1993

1985

1995

1997

1999

2001

2003

2005

2007

2009

Pro

ductivity

(K) Trans./S

taff –

Mo.

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SoC Design

Design Productivity Gap

� While designer productivity has grown at an impressive rate over the past decades, the rate of improvement has not kept pace with chip capacity

10,000

1,000

100

10

1

0.1

0.01

0.001

Logic transistors

per chip

(in millions)

100,000

10,000

1000

100

10

1

0.1

0.01

Productivity

(K) Trans./Staff-Mo.IC capacity

productivity

Gap

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SoC Design

Design Productivity Gap (cont.)

� 1981 leading edge chip required 100 designer months� 10,000 transistors / 100 transistors/month

� 2002 leading edge chip requires 30,000 designer months� 150,000,000 / 5000 transistors/month

� Designer cost increase from $1M to $300M

10,000

1,000

100

10

1

0.1

0.01

0.001

Logic transistors

per chip

(in millions)

100,000

10,000

1000

100

10

1

0.1

0.01

Productivity

(K) Trans./Staff-Mo.IC capacity

productivity

Gap

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SoC Design

The Mythical Man-Month

� The situation is even worse than the productivity gap indicates

� In theory, adding designers to team reduces project completion time

� In reality, productivity per designer decreases due to complexities of team management and communication

� In the software community, known as “the mythical man-month” (Brooks 1975)

� At some point, can actually lengthen project completion time! (“Too many cooks”)

10 20 30 400

10000

20000

30000

40000

50000

60000

43

24

19

1615

1618

23

Team

Individual

Months until completion

Number of designers

� 1M transistors, 1 designer=5000 trans/month

� Each additional designer reduces for 100 trans/month

� So 2 designers produce 4900 trans/month each

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SoC Design

SoC Challenges

� TimeTimeTimeTime----totototo----market:market:market:market:

� Human productivity

� Electronic design automation (EDA) tools

� CoCoCoCo----Design:Design:Design:Design:

� Software + Hardware

� Analog + Digital (Heterogeneous Systems)

� SoC Testing and VerificationSoC Testing and VerificationSoC Testing and VerificationSoC Testing and Verification

� NetworksNetworksNetworksNetworks----onononon----aaaa----Chip (NOC) Chip (NOC) Chip (NOC) Chip (NOC)

� Intellectual Property (IP) Intellectual Property (IP) Intellectual Property (IP) Intellectual Property (IP)

� Reuse

� Protection

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SoC Design

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Research Directions

Source: System Level Design Potential Solutions ,

The International Roadmap for Semiconductor 2005

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SoC Design

SoC Course Contents

� Introduction to Embedded Systems

� Pipelining Basics

� SoC design flow (HW/SW Codesign Flow)

� Abstraction levels (Transaction Level Modeling)

� Platform-based Design, Models of Computations

� SystemSystemSystemSystem----level description languages (C++/SystemC)level description languages (C++/SystemC)level description languages (C++/SystemC)level description languages (C++/SystemC)

� Computation vs. Communication

� Networks-on-a-Chip (NOC) � SoC Testing and Verification

� Advanced SoC Topics:� Heterogeneous System design

� Intellectual Property (IP) Protection

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SoC Design

Course Grading

� ExamsExamsExamsExams

� Quizzes 3333 Quizzes:Quizzes:Quizzes:Quizzes: best best best best 2222

� Mid Term

� Final exam

� AssignmentsAssignmentsAssignmentsAssignments

� ProjectProjectProjectProject

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SoC Design

SoC Project

� Course Project:Course Project:Course Project:Course Project:

� Building a Mini-MIPS Risc Processor Using SystemC

� Building a C application on the processor (Networking, DSP,…)

� Co-Simulation of the design.

� Other Project:Other Project:Other Project:Other Project:

� Getting familiar with one of the academic co-design tools.

� Implementation of a typical system on it.

� Other topicsOther topicsOther topicsOther topics (after instructor approval)

� Mixed Signal Design

� IP Protection

� …………

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SoC Design

SoC Project

� Phase Phase Phase Phase 0000: Select your partner (9/3/2009)

� Submit list of your group members (2-3 per group)

� Phase Phase Phase Phase 1111: : : : Design project specification (1st week of April)

� Collect related tools, papers, any other references

� Submit a brief (2-3 pages) document containing

� List of all collected material

� Your project design

.

.

.

.

.

� Phase NPhase NPhase NPhase N: Project Implementation + Report (2222 weeks before finalsweeks before finalsweeks before finalsweeks before finals)

FINAL Non-Negotiable deadline

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SoC Design

In time & It is too LATE Policy

� In phases In phases In phases In phases 0000, & , & , & , & 1111::::

� 5% of project grade penalty per day for being late

� In phase In phase In phase In phase 2222, to n:, to n:, to n:, to n:

� No late presentation is possible.

� Honor codeHonor codeHonor codeHonor code

� 100% penalty for both copier and copy-giver of Any Report/CAny Report/CAny Report/CAny Report/CODEODEODEODE.