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SOCSA Slides: Introduction
© Institute for Integrated Systems
Technische Universität München www.lis.ei.tum.de
System-on-Chip Solutions & Architectures
A. Herkersdorf M. Vonbun
© Institute for Integrated Systems
Technische Universität München www.lis.ei.tum.de
Introduction
System-on-Chip
Solutions & Architectures A. Herkersdorf
SOCSA Slides: Introduction
© Institute for
Integrated Systems
A. Herkersdorf SoC - Introduction - 3
Organisational matters
Lectures (A. Herkersdorf) Mon – Fri, 9:30 am – 12:30 pm
Tutorials (M. Vonbun) Mon – Fri, 1:30 pm – 3:00 pm
Homework: (30% of total grade) 4 exercise sheets (Tu, Th, Mo, We) to be returned in next but one
lecture
Exam: (70% of total grade) Date and room to be announced by GIST office,
written exam (75 min.), calculators & 1 US Letter / A4 sheet allowed (no computers, PDA, phones)
© Institute for
Integrated Systems
A. Herkersdorf SoC - Introduction - 4
Reading material / Literature
Course handouts and lecture notes Recommended as primary reference during course Sufficient for exam preparation
Text books Digital Integrated Circuits, A Design Perspective, J. Rabaey,
Prentice Hall
Computer Networks, A. Tannenbaum, Prentice Hall
Computer Architecture: A Quantitative Approach, J. Hennessy, Morgan Kaufmann Publishers
Useful Web links Cisco Internetworking Handbook
http://docwiki.cisco.com/wiki/Internetworking_Technology_Handbook Techlearner: A Guide to Semiconductors
http://www.techlearner.com/Semiconductors.htm http://ece-www.colorado.edu/~bart/book/book/chapter7/ch7_1.htm
SOCSA Slides: Introduction
© Institute for
Integrated Systems
A. Herkersdorf SoC - Introduction - 5
What is this course about?
System perspective of (digital) IC technology Foundation of CMOS scaling Key elements of IC technology (memory, µP, FPGA,
interconnect, I/O, packages) SoC (System-on-chip) design and modeling methodology
Impact of IC evolution on data networking and communications equipment evolution
… towards higher speed / capacity … towards more sophisticated and tighter integrated
functions … criticality of cost and power consumption
© Institute for
Integrated Systems
A. Herkersdorf SoC - Introduction - 6
Foundation of CMOS Scaling 1947:
First transistor
John Bardeen and Walter Brattain (Bell Laboratories )
1958:
First integrated circuit (IC)
Jack Kilby (TI), Robert Noyce (Fairchild)
2002:
PowerPC 970, 0.13µm, 1.8 GHz, 52 M transistors (IBM [1])
simplified CMOS transistor model
Oxt
minL
w
ddV
DrainSource
SOCSA Slides: Introduction
© Institute for
Integrated Systems
A. Herkersdorf SoC - Introduction - 7
Key Elements of IC Technology Memories:
- SRAM, DRAM, FLASH, RAMBUS, MRAM
- rd/wr latencies, access BW
(8 Mbit SRAM chip [1])
Processors:
- RISC, CISC, superscalar, VLIW
- performance: µP – cache - memory
(Intel Pentium I [2])
Interconnects:
- wireability and its performance impact
- on-chip buses Network-on-chip (NoC)
(IBM CMOS7S Cu 0.13µm [1])
Packages:
- I/O bottleneck
- high-speed I/O
- power limits
(Flip-chip CBGA [1])
© Institute for
Integrated Systems
A. Herkersdorf SoC - Introduction - 8
Course Outline
Module (Fundamentals) Module (Case Studies)
Introduction Microprocessors, Comm. Controllers
CMOS Basics Network Processor
Memory LAN/SAN Switch
Interconnect / Timing SONET/SDH Framer
SOCSA Slides: Introduction
© Institute for
Integrated Systems
A. Herkersdorf SoC - Introduction - 9
DR
AM
pric
es (M
icro
cen
t per b
it sto
red
)
107
106
105
104
103
102
10
1
10-1
10-2
Microprocessors 8008 8086
80286 80386
80486 Pentium
Pentium II Pentium III
Pentium 4 Core 2 Duo
Core i7
4k 16k
64k
256k 1M
4M
16M
64M 256M
1G
4G
16G
32G
DRAM-Chips
1972 1976 1980 1984 1988 1992 1996 2000 2012 2004 2008
2
0.5
0.2
0.1
0.05
0.02
0.01
1
Tra
nsis
tor g
ate
len
gth
L (u
m)
5
20
10
50
Moore’s Law CMOS Scaling Good news
Year
Source: ITRS Roadmap 99, 09
2016 2020
1011
1010
109
108
107
106
105
104
103
1013
1012
Ch
ipcap
acit
y (
tran
sis
tors
per
ch
ip)
© Institute for
Integrated Systems
A. Herkersdorf SoC - Introduction - 10
Microprocessors
1972 1976 1980 1984 1988 1992 1996 2000 2012 2004 2008
2
0.5
0.2
0.1
0.05
0.02
0.01
1
Tra
nsis
tor g
ate
len
gth
L (u
m)
5
20
10
50
Moore’s Law CMOS Scaling Challenges
Year 2016 2020
1011
1010
109
108
107
106
105
104
103
1013
1012
Ch
ipcap
acit
y (
tran
sis
tors
per
ch
ip)
Number of cores Frequency
Performance
8008 8086
80286 80386
80486 Pentium
Pentium II Pentium III
Pentium 4 Core 2 Duo
Core i7
hot plate
nuclear
reactor
rocket
nozzle
Power Dissipation
Po
wer
den
sit
y (
W/c
m2)
10
100
1
0.1
1000
Source: ITRS Roadmap 99, 09
SOCSA Slides: Introduction
© Institute for
Integrated Systems
A. Herkersdorf SoC - Introduction - 11
4k 16k
64k
256k 1M
4M
16M
64M 256M
1G
4G
16G
32G
DRAM-Chips
1972 1976 1980 1984 1988 1992 1996 2000 2012 2004 2008
2
0.5
0.2
0.1
0.05
0.02
0.01
1
Tra
nsis
tor g
ate
len
gth
L (u
m)
5
20
10
50
Moore’s Law CMOS Scaling
Year
Source: ITRS Roadmap 99, 09
2016 2020
1011
1010
109
108
107
106
105
104
103
1013
1012
Ch
ipcap
acit
y (
tran
sis
tors
per
ch
ip)
Economic Challenge
© Institute for
Integrated Systems
A. Herkersdorf SoC - Introduction - 12
Projection: CMOS in 2007
Technology: 0.07 µm Voltage: 0.9 V Die Area: 2.3x2.3 cm = 530 mm2
DRAM: 3 Gbit/cm2 eDRAM: 0.9 Gbit/cm2
SRAM (cache): 110 Mbit/cm2
Custom logic: 25 Mgates/cm2 54 W/cm2 3.3 GHz Std. cell: 10 Mgates/cm2 27 W/cm2 1.6 GHz eFPGA: 0.4 Mgates/cm2 4.5 W/cm2 0.25 GHz
SOCSA Slides: Introduction
© Institute for
Integrated Systems
A. Herkersdorf
1972 1976 1980 1984 1988 1992 1996 2000 2012 2004 2008
2
0.5
0.2
0.1
0.05
0.02
0.01
1
5
20
10
50
2016 2020
1011
1010
109
108
107
106
105
104
103
1013
1012
8008 8086
80286 80386
80486 Pentium
Pentium II Pentium III
Pentium 4 Core 2 Duo
Core i7
If Moore‘s Law …
… could have been applied to other technologies of our daily life over the past 30 years, then …
the energy of a 1.5 V AA-Mignon cell would be around 2 MWh today, Corresponds to the half year energy consumption
of a 4 persons house hold
the flight time between Munich and Singapore be less than 2 seconds, and …
the tuition fee for 1 semester in Harvard be SGD 1.50
© Institute for
Integrated Systems
A. Herkersdorf SoC - Introduction - 14
Designer Productivity Growth
1975: Polygons reflecting mask structure
1980: Transistor circuit design
1985: Boolean algebra, standard cells
A A’
In
Out
GND V DD
Layout
Transistor
Gate
SOCSA Slides: Introduction
© Institute for
Integrated Systems
A. Herkersdorf SoC - Introduction - 15
Designer Productivity Growth
1975: Polygons reflecting mask structure
1980: Transistor circuit design
1985: Boolean algebra, standard cells
1990: RTL design entry, logic synthesis
1995: High-level programming language like design entry, behavioral synthesis
Productivity growth due progress in EDA tools
enabling to move up the abstraction hierarchy
A A’
In
Out
GND V DD
Layout
Transistor
Gate
Reg 1
+
Reg 2 Reg 3
Reg 4
Comp
Register Transfer Block
Behavior
Begin
WAIT UNTIL (CLK’EVENT AND
CLK = ‘1’);
LCDltch <= tmp;
tmp := LCD;
END PROCESS;
© Institute for
Integrated Systems
A. Herkersdorf SoC - Introduction - 16
The Need for SoC Design Paradigm
Chip capacities of multi 10 to 100 M gates enable new dimensions of function integration
Challenge:
How to cope with this complexity and develop operational systems within …
reasonable time (time-to-market) and
costs (engineering and manufacturing)
µ-processor
Next level of abstraction: Functional IP macros / cores
eRAM
DRAM cntrl.
specific
network i/o
applic.
SOCSA Slides: Introduction
© Institute for
Integrated Systems
A. Herkersdorf SoC - Introduction - 17
The Need for SoC Design Paradigm
specific
Bus
Next level of abstraction: Functional IP macros / cores
eRAM µ-processor
eRAM M cntrl.
µ-processor
plus a standard on-chip interconnect structure
(NoC)
Chip capacities of multi 10 to 100 M gates enable new dimensions of function integration
Challenge:
How to cope with this complexity and develop operational systems within …
reasonable time (time-to-market) and
costs (engineering and manufacturing)
© Institute for
Integrated Systems
A. Herkersdorf SoC - Introduction - 18
SoC: Another way to look at it
MCU
SRAM SRAM
ROM
ROM DSP
Analog
ASIC
i/f i/f
~ 10
cm
~ 0.8 cm
What in the past was on a board, today fits on a chip
Source: Berkeley BWRC, TI cellular phone baseband SoC [4]
MCU ROM
DSP
SRAM
ASIC
An’lg
i/f
DC
SOCSA Slides: Introduction
© Institute for
Integrated Systems
A. Herkersdorf SoC - Introduction - 19
System on Package (SoP)
Multi-Chip Modules (MCM) Different processes/
technologies
Chip-on-Chip (CoC) Extension into third dimension
Sources: esa DSP MCM [5], Valtronic hearing aid CoC [6]
© Institute for
Integrated Systems
A. Herkersdorf SoC - Introduction - 20
Computational Density
Log COMPUTATIONAL DENSITY = performance / area
103 . . . 104
Lo
g
P O
W E
R
C
ON
SU
MP
TIO
N
10
5 .
. . 10
6
ASIP DSP CPU
FPGA
ASIC
Custom IC Lo
g
F L
E X
I B
I L
I T
Y
Instr
ucti
on
Dep
th
Flexibility vs. Performance / Power dissipation dilemma
Source: A. DeHon [7]; A. Cuomo, T. Noll [8]
SOCSA Slides: Introduction
© Institute for
Integrated Systems
A. Herkersdorf SoC - Introduction - 21
Computational Density
Log COMPUTATIONAL DENSITY = performance / area
103 . . . 104
ASIP DSP CPU
FPGA
ASIC
Custom IC Lo
g
F L
E X
I B
I L
I T
Y
Instr
ucti
on
Dep
th
Flexibility vs. Performance / Power dissipation dilemma
Source: A. DeHon [7];
A. Cuomo, T. Noll [8]
Log Power Efficiency = performance / W
105 . . . 106
© Institute for
Integrated Systems
A. Herkersdorf SoC - Introduction - 22
Functional Diversity
Source: DeHon, PhD Thesis [7]
Computational Density Computations performed per
unit area and time Implementation technique
descriptor [CD] = ops / N [Lmin
2 tiles] CPU: 40 – 80 FPGA: 400 ASIC: 4’000 Custom: > 10’000
approx. values
Instruction Depth View 1: Number of
instructions resident and rapidly accessible by a compute unit
View 2: Empiric metric for the variance of instructions executed on a compute unit
Application descriptor [ID] = instr.
CPU: ~256 – 16 K FPGA: 1 ASIC: 10-3 - 10-6
Custom IC: ~ 0
SOCSA Slides: Introduction
© Institute for
Integrated Systems
A. Herkersdorf
Custom Logic
Parallel in space and time
Time 0
Time 1
Time 2
+
-
C D
y
SoC Implementation Styles
+
A B
SoC - Introduction - 23
Pipelined RISC CPU
Parallel in space, sequential in time
IF ID OF EX WB M
IF ID OF EX WB M
IF ID OF EX WB M
t1 = A + B
t2 = C + D
Y = t1 - t2
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Integrated Systems
A. Herkersdorf SoC - Introduction - 24
Telephony Milestones
March 10, 1876:
Alexander G. Bell first transmitting speech electrically
(1910: AT&T phone [9])
1930:
AT&T transatlantic switchboard
(New York – London via radio, Capacity: 1 call at a time, Price: $75 / 3 min. [10])
1980:
Siemens EWSD switching center
(Today, 2002: 240’000 ports,
100’000 Erlang, 16 M BHCA [11])
2003:
Mobile phone, PDA, video camera & player, WEB browser
SOCSA Slides: Introduction
© Institute for
Integrated Systems
A. Herkersdorf SoC - Introduction - 25
Inter-Networking Milestones
Ethernet LAN:
Privately-owned networks within building or on campus (1976: Metcalf’s sketch of first ethernet)
1974: TCP/IP
Introduction of the Internet Protocol suite by V. Cerf and B. Kahn. However, … (Honored with national medal
of technology, 1997)
1989: WWW.
… it took 20 years to make it ubiquitous
T. Berners-Lee, CERN physicist inventing http
… the future: GRID computing
Distributed compute server infrastructure
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A. Herkersdorf SoC - Introduction - 26
Real-world Case Studies
Sonet/SDH Transmission LAN/SAN
Switch
Internet Router
Control Procesors Sonet/SDH
Transmission
SOCSA Slides: Introduction
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Integrated Systems
A. Herkersdorf SoC - Introduction - 27
Communication Controllers
Separation between Data Path and Control functions in Network Equipment
Control functions
System operation, administration and maintenance (OAM)
• Bring-up, bit error rate supervision,
• Topology, connectivity administration
• Security (encryption, authentication)
• Protection switching, failure recovery Data Path
Control
CPU Mem
System & Mem. i/f’s
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Integrated Systems
A. Herkersdorf SoC - Introduction - 28
Design challenges High, scalable processor
performance embedded, stand-alone
High-bandwidth on-chip / intra-chip memory and system interfaces
Key system requirements High, scalable processor
performance
Different, high-bandwidth memory and system interfaces
Standard development tool chains and (RT)OS’s
1:1
Communication Controllers
SOCSA Slides: Introduction
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A. Herkersdorf SoC - Introduction - 29
Internet Router / Gateways
IP (Internet Protocol)
Layer 3 protocol of the Internet for inter-networking
TCP (Transmission Control Protocol)
Dominant Layer 4 Transport protocol of the Internet (2000: 95 % of Internet flows)
IP Router in the past
Packet forwarding only
“Moderate” link rates (155 Mb/s)
Initially full CPU/SW based
IP Router today and future
HW accelerated
NP based due to increasing link rates and new functions
Time
L2 / VLAN
History
L2 / VLAN
Layer 3: IP Routing
Current Trend
L2 / VLAN
Layer 3: IP Routing
Future
L2 / VLAN
Layer 3: IP Routing
Today
AS
IC
Netw
ork
Pro
ce
sso
r
Market Trends
Layer 4: DiffServ Security Filtering
Layer 4: DiffServ Security Filtering
Deep Packet Processing
© Institute for
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A. Herkersdorf SoC - Introduction - 30
Internet Router / Gateways
Unique design challenges High processor
performance
Generic HW coprocessors and accelerators
High-capacity and –BW on-/off-chip memories
High-capacity on-chip processor busses / interconnects
Key system requirements Flexibility
Wide spectrum of functions / new applications depending on topology location
Performance
10’s M packets / s
1000 instr. / packet
Converged data, voice, multi-media services
SOCSA Slides: Introduction
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A. Herkersdorf SoC - Introduction - 31
LAN/SAN Switches
Ethernet / IEEE 802.3 Ubiquitous shared/switched-
medium, packet-based Layer 2 local area network standard
10/100 Mb/s, 1 Gb/s, 10 Gb/s Evolution towards VPN (security)
and support for real-time streams
Shared-medium Single connection (@ full
media speed) Collisions Fairness, QoS ?!
Bytes 7 1 2 x 6 2 46 – 1500 4
Data Addr’s CRC P’ble S L
© Institute for
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A. Herkersdorf SoC - Introduction - 32
LAN/SAN Switches
Ethernet / IEEE 802.3 Ubiquitous shared/switched-
medium, packet-based Layer 2 local area network standard
10/100 Mb/s, 1 Gb/s, 10 Gb/s Evolution towards VPN (security)
and support for real-time streams
Shared-medium Single connection (@ full
media speed) Collisions Fairness, QoS ?!
Switched-medium Multiple, simultaneous
connections Output contention -> queuing
Bytes 7 1 2 x 6 2 46 – 1500 4
Data Addr’s CRC P’ble S L
SOCSA Slides: Introduction
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A. Herkersdorf SoC - Introduction - 33
LAN / SAN Switches
Unique design challenges High function integration,
parallel data paths
High-speed PHY i/f’s
Fair, multi-priority services
DiffServ, QoS, VoIP
High pin count, complex interconnect wiring, large on-chip memory
Key system requirements Low-cost, high speed
(10/100 Mbit/s to 10 Gbit/s) in-house and campus area networks
Emerging mix of data, real-time voice and multi-media services
Large number of ports, lossless operation
© Institute for
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A. Herkersdorf SoC - Introduction - 34
SONET/SDH Transmission
Globally accepted standard for digital information transmission over physical media (copper, fiber)
SONET (ANSI), SDH (ITU)
Built-in OAM
Uniform multiplexing hierarchy
SONET/SDH Framer
PHY
IP T1 ATM IP T1 ATM
OSI Layer 1
TDM (circuit
switched)
Payload OAM
OAM
1
1
9
N x 90
T = 125µs
OC-N = N x 90 x 9 x 8 bit
125 µs
STM-K = K x OC-3 = OC-3K
N = [1, 3, 12, 48, 192, 768]; K = [1, 4, 16, 64, 256]
SONET/SDH Ring
SOCSA Slides: Introduction
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A. Herkersdorf SoC - Introduction - 35
SONET/SDH Transmission
Unique design challenges Exploitation of parallel
data path structures and algorithms
Deterministic FSM design with guaranteed latencies
High-speed parallel and serial (mixed-signal) PHY interfaces
Key system requirements High-speed (51/155
Mbit/s to 10/40 Gbit/s)
Synchronous TDM concept for congestion-free reliable transport of voice and data
Automated system operation, administration and control
© Institute for
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A. Herkersdorf SoC - Introduction - 36
References [1] IBM press release, „New 64-bit PowerPC microprocessor“, Oct. 14, 2002,
http://www-3.ibm.com/chips/news/2002/1014_powerpc.html
[2] IBM Microelectronics Photo Catalog, http://www-3.ibm.com/chips/photolibrary/photo10.nsf/home?ReadForm
[3] Molecular Expressions, Chip Shots, Microscopy of Integrated Circuits, http://micro.magnet.fsu.edu/chipshots/pentium/index.html
[4] Design Technology for Low Power Radio Systems, Reth Davis, BWRC, Berkeley, http://bwrc.eecs.berkeley.edu
[5] DSP multi chip module, esa, http://www.estec.esa.nl/tech/spacewire/products/#modules
[6] Chip-On-Chip, Valtronic SA, http://www.valtronic.ch
[7] Reconfigurable Architectures for General Purpose Computing, Andre DeHon, PhD Thesis, MIT, 1996
[8] A. Cuomo, Semiconductor Challenges, DATE03 Keynote, March 03, http://www.date-conference.com/conference/2003/keynotes/andrea/andrea.pdf
SOCSA Slides: Introduction
© Institute for
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A. Herkersdorf SoC - Introduction - 37
References
[9] Telephone History Photo Gallery, http://www.schoelles.com/Telephone/telphoto.htm
[10] History of the AT&T network: milestones, http://www.att.com/spotlight/nethistory/milestones.html
[11] Siemens Chronik, Gegenwart, http://w4.siemens.de/archiv/de/chronik/epoche_1945_gegenwart.html