SystemCSystemC

M. Barış UyarM. Barış Uyar

What Is SystemC?What Is SystemC?

�� A subset of C++ that models/specifies synchronous digital A subset of C++ that models/specifies synchronous digital hardwarehardware�� Processes (for concurrency)Processes (for concurrency)�� Clocks (for time)Clocks (for time)�� Hardware (finite) data types [bit vectors, 4Hardware (finite) data types [bit vectors, 4--valued logic, fixedvalued logic, fixed--point types, point types,

arbitrary precision integers] and infinite data typesarbitrary precision integers] and infinite data typesWaiting and watching (for reactivity)Waiting and watching (for reactivity)�� Waiting and watching (for reactivity)Waiting and watching (for reactivity)

�� Modules, ports, signals (for hierarchy)Modules, ports, signals (for hierarchy)

�� SystemC providesSystemC provides�� Modelling in a higher level of abstractionModelling in a higher level of abstraction�� Faster simulation timesFaster simulation times�� TTesting the behaviour of the entire chip before productionesting the behaviour of the entire chip before production�� Allows to make an Allows to make an “Executable Specification”“Executable Specification”

�� Synthesis support??!!Synthesis support??!!

Where to use?Where to use?1.1. Modelling in a higher level of abstractionModelling in a higher level of abstraction

2.2. SynthesisSynthesis

Why not just C++Why not just C++

• Concurrency support is missing (HW is inherently parallel)No notion of time (clock, delays)Communication model is very Communication model is very different from actual HW model (signals)Weak/complex reactivity to eventsMissing data types (logic values, bit vectors, fixed point math)

SystemC SystemC

�� … C++ extensions!

� New library (libsystemc.a) providing additional functionality

� Building upon C++ features (inheritance!) and data types to Building upon C++ features (inheritance!) and data types to better express HW behavior

� “SystemC” HW-modeling code is actually C++ code and can be freely mixed with plain C++

SystemC usage modelsSystemC usage models

Standard Methodology for ICsStandard Methodology for ICs

�� SystemSystem--level designers write a C or C++ modellevel designers write a C or C++ model

�� Written in a stylized, hardwareWritten in a stylized, hardware--like formlike form

�� Sometimes refined to be more hardwareSometimes refined to be more hardware--likelike

�� C/C++ model simulated to verify functionalityC/C++ model simulated to verify functionalityC/C++ model simulated to verify functionalityC/C++ model simulated to verify functionality

�� Model given to Verilog/VHDL codersModel given to Verilog/VHDL coders

�� Verilog or VHDL specification writtenVerilog or VHDL specification written

�� Models simulated together to test equivalenceModels simulated together to test equivalence

�� Verilog/VHDL model synthesizedVerilog/VHDL model synthesized

Designing Big Digital SystemsDesigning Big Digital Systems

�� Every system company was doing this differentlyEvery system company was doing this differently

�� Every system company used its own simulation libraryEvery system company used its own simulation library

�� “Throw the model over the wall” approach makes it “Throw the model over the wall” approach makes it easy to introduce errorseasy to introduce errorseasy to introduce errorseasy to introduce errors

�� Problems:Problems:

�� System designers don’t know Verilog or VHDLSystem designers don’t know Verilog or VHDL

�� Verilog or VHDL coders don’t understand system Verilog or VHDL coders don’t understand system designdesign

Idea of SystemCIdea of SystemC

�� C and C++ are being used as adC and C++ are being used as ad--hoc modeling hoc modeling languageslanguages

�� Why not formalize their use?Why not formalize their use?

�� Why not interpret them as hardware Why not interpret them as hardware �� Why not interpret them as hardware Why not interpret them as hardware specification languages just as Verilog and specification languages just as Verilog and VHDL were?VHDL were?

Quick OverviewQuick Overview

�� A SystemC program consists of module definitions plus a topA SystemC program consists of module definitions plus a top--level function that starts the simulationlevel function that starts the simulation

�� Modules contain processes (C++ methods) and instances of Modules contain processes (C++ methods) and instances of other modulesother modules

�� Ports on modules define their interfacePorts on modules define their interface�� Rich set of port data types (hardware modeling, etc.)Rich set of port data types (hardware modeling, etc.)�� Rich set of port data types (hardware modeling, etc.)Rich set of port data types (hardware modeling, etc.)

�� Signals in modules convey information between instancesSignals in modules convey information between instances

�� Clocks are special signals that run periodically and can trigger Clocks are special signals that run periodically and can trigger clocked processesclocked processes

�� Rich set of numeric types (fixed and arbitrary precision numbers)Rich set of numeric types (fixed and arbitrary precision numbers)

System

Process BProcess C

Module 1 Module 2

channels

portsProcess A

ModulesModules�� Hierarchical entityHierarchical entity

�� Similar to Verilog’s moduleSimilar to Verilog’s module

�� Actually a C++ class definitionActually a C++ class definition

�� Simulation involvesSimulation involves

�� Creating objects of this classCreating objects of this class

�� They connect themselves togetherThey connect themselves together�� They connect themselves togetherThey connect themselves together

�� Processes in these objects (methods) are called by the Processes in these objects (methods) are called by the

scheduler to perform the simulationscheduler to perform the simulation

ModulesModules� map functionality of HW/SW blocks

� derived from SystemC class sc_module

� represent the basic building block of every system

� modules can contain a whole hierarchy of sub-modules

� and provide private variables/signals

�� Communication: Modules

can interface to each other viacan interface to each other via

ports/interfaces/channels

� Functionality: achieved by

means of processes

ModulesModules

PortsPorts

�� Define the interface to each moduleDefine the interface to each module

�� Channels through which data is communicatedChannels through which data is communicated

�� Port consists of a directionPort consists of a direction

inputinput sc_insc_in�� inputinput sc_insc_in

�� outputoutput sc_outsc_out

�� bidirectionalbidirectional sc_inoutsc_inout

�� and any C++ or SystemC typeand any C++ or SystemC type

PortsPorts

SignalsSignals

�� Convey information between modules within a Convey information between modules within a modulemodule

�� Directionless: module ports define direction of Directionless: module ports define direction of data transferdata transferdata transferdata transfer

�� Type may be any C++ or builtType may be any C++ or built--in typein type

SignalsSignals

SC_MODULE(mymod) {SC_MODULE(mymod) {

/* port definitions *//* port definitions */

sc_signal<sc_uint<32> > s1, s2;sc_signal<sc_uint<32> > s1, s2;

sc_signal<bool> reset;sc_signal<bool> reset;

/* … *//* … */

SC_CTOR(mymod) {SC_CTOR(mymod) {

/* Instances of modules that connect to the signals *//* Instances of modules that connect to the signals */

}}

};};

Instances of ModulesInstances of Modules

�� Each instance is a pointer to an object in the moduleEach instance is a pointer to an object in the module

SC_MODULE(mod1) { … };SC_MODULE(mod1) { … };

SC_MODULE(mod2) { … };SC_MODULE(mod2) { … };

SC_MODULE(foo) {SC_MODULE(foo) {

Connect instance’s ports to signals

SC_MODULE(foo) {SC_MODULE(foo) {

mod1* m1;mod1* m1;

mod2* m2;mod2* m2;

sc_signal<int> a, b, c;sc_signal<int> a, b, c;

SC_CTOR(foo) {SC_CTOR(foo) {

m1 = new mod1(“i1”); (*m1)(a, b, c);m1 = new mod1(“i1”); (*m1)(a, b, c);

m2 = new mod2(“i2”); (*m2)(c, b);m2 = new mod2(“i2”); (*m2)(c, b);

}}

};};

Signal instanciation and bindingSignal instanciation and binding

ProcessesProcesses

�� They provide module functionality

� Implemented as member functions

� Three kinds of processes available:

� SC_METHOD

� SC_THREAD

SC_CTHREAD� SC_CTHREAD

� All of the processes in the design run concurrently

� Code inside of every process is sequential

METHOD ProcessesMETHOD Processes

�� Sensitive to any change on input ports

� Usually used to model purely combinational logic (i.e. NORs, NANDs, muxes, …)

� Cannot be suspended. All of the function code is executed every time the SC_METHOD is invoked

� Does not remember internal state among invocations (unless explicitly kept � Does not remember internal state among invocations (unless explicitly kept in member variables)

MethodMethod

Thread ProcessesThread Processes

� Adds the ability to be suspended to SC_METHOD processes by means of wait() calls (and derivatives)

� Still has a sensitivity list. wait() returns when a change is detected on a port in the sensitivity list

� Remembers its internal state among invocations (i.e. execution resumes from where it was left)resumes from where it was left)

� Very useful for clocked systems, memory elements, multi-cycle behavior

� Imposes a heavier load onto the SystemC scheduler (slower simulations) due to context switches and state tracking

ThreadThread

SystemC TypesSystemC Types

�� SystemC programs may use any C++ type along SystemC programs may use any C++ type along with any of the builtwith any of the built--in ones for modeling in ones for modeling systemssystems

SystemC BuiltSystemC Built--in Typesin Types

�� sc_bit, sc_logicsc_bit, sc_logic

�� TwoTwo-- and fourand four--valued single bitvalued single bit

�� sc_int, sc_unintsc_int, sc_unint

�� 1 to 641 to 64--bit signed and unsigned integersbit signed and unsigned integers

sc_bigint, sc_biguintsc_bigint, sc_biguint�� sc_bigint, sc_biguintsc_bigint, sc_biguint

�� arbitrary (fixed) width signed and unsigned integersarbitrary (fixed) width signed and unsigned integers

�� sc_bv, sc_lvsc_bv, sc_lv

�� arbitrary width twoarbitrary width two-- and fourand four--valued vectorsvalued vectors

�� sc_fixed, sc_ufixedsc_fixed, sc_ufixed

�� signed and unsigned fixed point numberssigned and unsigned fixed point numbers

Fixed and Floating Point TypesFixed and Floating Point Types

�� IntegersIntegers

�� PrecisePrecise

�� Manipulation is fast and cheapManipulation is fast and cheap

�� Poor for modeling continuous realPoor for modeling continuous real--world behaviorworld behavior

�� FloatingFloating--point numberspoint numbers

�� Less preciseLess precise

�� Better approximation to real numbersBetter approximation to real numbers

�� Good for modeling continuous behaviorGood for modeling continuous behavior

�� Manipulation is slow and expensiveManipulation is slow and expensive

�� FixedFixed--point numberspoint numbers

�� Worst of both worldsWorst of both worlds

�� Used in many signal processing applicationsUsed in many signal processing applications

Integers, FloatingIntegers, Floating--point, Fixedpoint, Fixed--

pointpoint

�� IntegerInteger

Decimal (“binary”) point

�� FixedFixed--pointpoint

�� FloatingFloating--pointpoint ×××× 2

Using FixedUsing Fixed--Point NumbersPoint Numbers

�� HighHigh--level models usually use floatinglevel models usually use floating--point for conveniencepoint for convenience

�� FixedFixed--point usually used in hardware implementation because point usually used in hardware implementation because

they’re much cheaperthey’re much cheaper

�� Problem: the behavior of the two are differentProblem: the behavior of the two are different

�� How do you make sure your algorithm still works after it’s How do you make sure your algorithm still works after it’s �� How do you make sure your algorithm still works after it’s How do you make sure your algorithm still works after it’s

been converted from floatingbeen converted from floating--point to fixedpoint to fixed--point?point?

�� SystemC’s fixedSystemC’s fixed--point number classes facilitate simulating point number classes facilitate simulating

algorithms with fixedalgorithms with fixed--point numberspoint numbers

SystemC’s FixedSystemC’s Fixed--Point TypesPoint Types

�� sc_fixed<8, 1, SC_RND, SC_SAT> fpn;sc_fixed<8, 1, SC_RND, SC_SAT> fpn;

�� 8 is the total number of bits in the type8 is the total number of bits in the type

�� 1 is the number of bits to the left of the decimal point1 is the number of bits to the left of the decimal point

SC_RND defines rounding behaviorSC_RND defines rounding behavior�� SC_RND defines rounding behaviorSC_RND defines rounding behavior

�� SC_SAT defines saturation behaviorSC_SAT defines saturation behavior

RoundingRounding

�� What happens when your result doesn’t land What happens when your result doesn’t land exactly on a representable number?exactly on a representable number?

�� Rounding mode makes the choiceRounding mode makes the choice�� Rounding mode makes the choiceRounding mode makes the choice

SC_RNDSC_RND

�� Round up at 0.5Round up at 0.5

�� What you expect?What you expect?

SC_RND_ZEROSC_RND_ZERO

�� Round toward zeroRound toward zero

�� Less error accumulationLess error accumulation

SC_TRNSC_TRN

�� TruncateTruncate

�� Easiest to implementEasiest to implement

OverflowOverflow

�� What happens if the result is too positive or too What happens if the result is too positive or too negative to fit in the result?negative to fit in the result?

�� Saturation? WrapSaturation? Wrap--around?around?

�� Different behavior appropriate for different Different behavior appropriate for different �� Different behavior appropriate for different Different behavior appropriate for different applicationsapplications

SC_SATSC_SAT

�� SaturateSaturate

�� Sometimes desiredSometimes desired

SC_SAT_ZEROSC_SAT_ZERO

�� Set to zeroSet to zero

�� Odd behaviorOdd behavior

SC_WRAPSC_WRAP

�� WraparoundWraparound

Easiest to implementEasiest to implement�� Easiest to implementEasiest to implement

Layers of HW designLayers of HW design

Scope of LayersScope of Layers

Purpose of layersPurpose of layers

� Low-level layers: Clock management (sc_clock), signal support

(sc_signal),01XZ values (sc_lv), flexible synchronization of

modules(SC_METHOD, SC_THREAD), VHDL-like

scheduling

� High-level layers: Powerful object-oriented features (C++ � High-level layers: Powerful object-oriented features (C++

roots), easy synchronization of modules (SC_THREAD,

SC_CTHREAD), reconfigurable sensitivity according to

circumstances (sc_event), high-level abstractions of HW

resources (FIFOs, mutexes,semaphores…)

SystemC PhilosophySystemC Philosophy

Channel bindingChannel binding

RTL Model ExampleRTL Model Example

�� An 8 bit counter. This counter can be loaded on a clk

rising edge by setting the input load to 1 and placing a

value on input din. The counter can be cleared by setting

input clear high.

� A very basic 8 bit shifter. The shifter can be loaded on a� A very basic 8 bit shifter. The shifter can be loaded on a

clk rising edge by placing a value on input din and setting

input load to 1. The shifter will shift the data left or right

depending on the value of input LR. If LR is low the shifter

will shift right by one bit, otherwise left by one bit.

� Local temporary values are needed because the value of

output ports cannot be read.

Bus Cycle Accurate modelBus Cycle Accurate model

UnTimed FunctionalUnTimed Functional

Timed FunctionalTimed Functional

Synthesis Subset of SystemCSynthesis Subset of SystemC

�� At least twoAt least two

�� “Behavioral” Subset“Behavioral” Subset

�� Resource sharing, binding, and allocation done automaticallyResource sharing, binding, and allocation done automatically

System determines how many adders you haveSystem determines how many adders you have�� System determines how many adders you haveSystem determines how many adders you have

�� RegisterRegister--transfertransfer--level Subsetlevel Subset

�� More like VerilogMore like Verilog

�� You write a “+”, you get an adderYou write a “+”, you get an adder

Do People Use SystemC?Do People Use SystemC?

�� Not as many as use Verilog or VHDLNot as many as use Verilog or VHDL

�� Growing in popularityGrowing in popularity

�� People recognize advantage of being able to People recognize advantage of being able to share modelsshare modelsshare modelsshare models

�� Most companies were doing something like it Most companies were doing something like it alreadyalready

�� Use someone else’s free libraries? Why not?Use someone else’s free libraries? Why not?

ConclusionsConclusions

�� C++ dialect for modeling digital systemsC++ dialect for modeling digital systems

�� Provides a simple form of concurrencyProvides a simple form of concurrency

�� Cooperative multitaskingCooperative multitasking

�� ModulesModules

�� Instances of other modulesInstances of other modules

�� ProcessesProcesses

ConclusionsConclusions

�� Perhaps even more flawed than VerilogPerhaps even more flawed than Verilog

�� Verilog was a hardware modeling language Verilog was a hardware modeling language forced into specifying hardwareforced into specifying hardware

�� SystemC forces C++, a software specification SystemC forces C++, a software specification �� SystemC forces C++, a software specification SystemC forces C++, a software specification language, into modeling and specifying hardwarelanguage, into modeling and specifying hardware

�� Will it work? Time will tell.Will it work? Time will tell.

ReferencesReferences

�� Course slides : Course slides : Prof. Stephen A. EdwardsProf. Stephen A. Edwards

�� Course slides : Federico AngioliniCourse slides : Federico Angiolini