systemverilog & verilog 2001 -...
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Copyright ©2001-2003,Model Technology
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™
SystemVerilog & Verilog 2001
ModelSim®
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SystemVerilog & Verilog 2001 AgendaVerilog 2001
OverviewSeveral features - generate, configurations, & re-entrant tasksModelSim and Verilog 2001Summary & Resources
SystemVerilogWhat, Why, WhoInterfaces, Structures, Packed & Unpacked Arrays, DPIAssertionsTestbenchesModelSim support of SystemVerilogSummary & Resources
Question & Answer
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Verilog 2001Verilog 2001 adds a huge number of new design constructs to the original IEEE 1364-1995 standardVerilog 2001 is more than just new design constructs
– It documents features already in use but not defined in the 1995standard
– It provides enhanced file I/O– It provides enhanced VCD file generation– It allows better modeling for timing– It updates PLI support
Some errata since the original release of IEEE 1364-2001– Original version dated 28 September 2001 had many publishing errors– Current release is Version C
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GenerateQuestion:
Hand instantiating multiple instances of the same module is error prone, time consuming, and makes hard to read code, is there a better way??
Answer:
Verilog 1995 provides a construct called “array of instances”, however … its limited.
Verilog 2001 greatly improves upon that construct with a complete generate statement.
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Generate
Top level module created from many smaller memory blocks
Qout
data
clk
enrst
memcelli0
memcelli2
memcelli1
memcelli3
memcelli4
memcelli…n
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Generatemodule memory ( … );
wire [WORD_SIZE-1:0] Qout [0:(1 << ADDR_SIZE - 1) - 1]; memcell i0 ((.q(Qout[0][0]),.d(data[0][0]),.clk(clk),.rst(rst),.en(en)); memcell i1 ((.q(Qout[0][1]),.d(data[0][1]),.clk(clk),.rst(rst),.en(en));memcell i2 ((.q(Qout[0][2]),.d(data[0][2]),.clk(clk),.rst(rst),.en(en));memcell i3 ((.q(Qout[0][3]),.d(data[0][3]),.clk(clk),.rst(rst),.en(en));memcell i4 ((.q(Qout[0][4]),.d(data[0][4]),.clk(clk),.rst(rst),.en(en));
…memcell i…n ((.q(Qout[i][j]),.d(data[i][j]),.clk(clk),.rst(rst),.en(en));
endmodule
Always been very verbose in Verilog
32-bit vectors with address range of 1024??
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Generatemodule memory ( … );
wire [WORD_SIZE-1:0] Qout [0:(1 << ADDR_SIZE - 1) - 1]; generate
genvar i, j;for (i = 0; i < (1 << ADDR_SIZE - 1); i = i + 1)begin:depth
for (j = 0; j < WORD_SIZE; j = j + 1)begin:width
memcell r0 (.q(Qout[i][j]),.d(data[i][j]),.clk(clk),.rst(rst),.en(en));end
endendgenerate
endmodule
Very simple and readable block regardless of memory dimensions
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New Feature - Configurations
Question:
How can I replace just one instance of a module in my design with its gate level version??
Answer:
This can’t really be done in Verilog 1995. Verilog 2001 now makes this easy with configurations.
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Configurations
dut:top:
module adder ( );rtl code …
endmodule
module adder ( );rtl code …
endmodule
i0: i1:
module add2bit (input [1:0] A, B, output [1:0] SUM, output CO);
adder i0 (SUM[0], carry, A[0], B[0], 1’b0);
adder i1 (SUM[1], CO, A[1], B[1], carry);
endmodule
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Configurations
dut:top:
module adder ( );rtl code …
endmodule
module adder ( );gate level code …
endmodule
i0: i1:
config-file.cfg:config mixed;
design work.top;default liblist rtl;instance top.dut.i1 liblist gate;
endconfig
lib.map: (optional)library work top.v;library rtl add2bit.v, rtl-adder.v;library gate gate-adder.v;
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New Feature - Automatic tasks
Question:
How can I make concurrent calls to a task without one call “clobbering” the other??
Answer:
This can’t be done in Verilog 1995 even though concurrent execution from multiple procedures is legal Verilog:
All tasks are defined as static
Hence all variables in the task share the same memory space
Verilog 2001 adds automatic tasks making this safe.
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Automatic (re-entrant) tasksBy defining “automatic” or re-entrant tasks, each call to the task gets its own unique memory space for its variables
module TEST (input A, B, CLK)always @(posedge A)
clk_cnt;always @(posedge B)
clk_cnt;task automatic clk_cnt;
integer i;begin
$display(“%t COUNT started …”, $realtime);for (i = 0; i < 5; i = i + 1)
@(posedge CLK) $display(“%t COUNT = %0d”, $realtime, i);$display(“%t COUNT finished!”, $realtime);
endendtask
endmodule
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Automatic (re-entrant) tasks1995 style task - BAD:
75 ns COUNT started ...150 ns COUNT = 0250 ns COUNT = 1320 ns COUNT started ...350 ns COUNT = 0350 ns COUNT = 1450 ns COUNT = 2450 ns COUNT = 3550 ns COUNT = 4550 ns COUNT finished!550 ns COUNT = 5550 ns COUNT finished!
2001 automatic task - GOOD:
75 ns COUNT started ...150 ns COUNT = 0250 ns COUNT = 1320 ns COUNT started ...350 ns COUNT = 0350 ns COUNT = 2450 ns COUNT = 3450 ns COUNT = 1550 ns COUNT = 2550 ns COUNT = 4550 ns COUNT finished!650 ns COUNT = 3750 ns COUNT = 4750 ns COUNT finished!
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Verilog 2001 & ModelSim
Project complete in the ModelSim 5.8 releaseNew constructs available in 5.8:— Configurations— Automatic (re-entrant) tasks— Automatic (recursive) functions— Constant functions
IEEE 1364-2001 default for ModelSim verilog compiler— vlog -vlog95compat for backward compatibility
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Verilog 2001 Summary
Verilog 2001 adds a huge amount of new capabilities to the Verilog language
Our implementation of Verilog 2001 is complete today in ModelSim 5.8
ModelSim was the first simulator on the market with a complete implementation
Verilog 2001 is the foundation for implementing SystemVerilog
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Verilog 2001 ResourcesVerilog 2001 application note is available at:
http://www.model.com/products/pdf/appnotes/Verilog-2001.pdf
“Verilog 2001” by Stuart Sutherland:
Excellent reference for comparing features
Kluwer Academic Publishers (ISBN 0-7923-7568-8)
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Who is SystemVerilog?SystemVerilog is being developed by AccelleraAccellera is composed of many individuals & companies– End users– Consultants/Trainers– EDA venders
Many Accellera members also on IEEE 1364 committeesDennis Brophy of Mentor Graphics chairs Accellera
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What is SystemVerilog?It’s the next logical extension to Verilog– Based on IEEE 1364-2001– New design constructs – New Testbench and Verification constructs
It’s an industry standard– SystemVerilog 3.1 and 3.0 are NOT different standards– 3.1 is the current approved standard– SystemVerilog 3.1a is the current working draft
3.1a adds a number of new constructs– Functional coverage– Packages
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What is SystemVerilog?
Verilog 95
Verilog 2001
SystemVerilogC
modulesparametersfunctions/tasksalways/initialassignwire, reg, time
multi-dimensional arrays
$display, $fopen, $finish
generate
constant functions
configurations
memory part selects
variable part selects
enhanced file I/O
`line, `ifndef, `elsif
@*
localparam
(* attributes *)
2-state types - int, shortint
shortreal (float), real (double)
enumerated data types - enum
user defined types - typedef
structures and unions
do-while bottom testing loop
operators ++, --, +=, *=, >>=, |=, &=
signed arithmetic (v2k)
automatic tasks/functions (v2k)
power operator ** (v2k)
while, for, if/else, repeat (v1995)
interfaces
packed/unpacked arrays
dynamic arrays
associative arrays
assertions
classes
functional coverage
constrained random test
semaphore/mailbox
clocking domains
always_comb, always_latch, always_ff
program block
packages
.* and .name port connections
time literals - #10ns
logic data type
unique/priority
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Why SystemVerilog?Higher levels of abstraction & system level modeling
– Design larger and larger chips in less time
New Verification and Test constructs
– Validate these rapidly growing designs
Both of the above integrated into a single language
– Still includes RTL and gate level modeling constructs
Backward compatible to legacy designs
Standard portable across tools
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InterfacesQuestion:
Why use a SystemVerilog interface??
Answer:Encapsulation of the interface specifics
Make port declarations only once
Simplifies design unit instantiations
Better debug with embedded assertions
Include tasks/functions directly in the interface
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InterfacesAn interface is like a white board drawing with as little or as much detail as is needed.
Inputs
Outputs
Block to Block
CTRL MEM
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Interfacesinterface top_if (input mclk, rst, strt);
tri [31:0] mb;logic [15:0] addr;logic mrd, mwr;modport mem_mp (inout mb,
input addr, mrd, mwr);modport ctrl_mp (inout mb,
output addr, mrd, mwr,input mclk, rst, strt);
endinterface: top_if
module top;top_if io (mclk, rst, strt);ctrl dut (io);mem m0 (io);…
endmodule
module ctrl (top_if.ctrl_mp io);always @(posedge io.mclk)…
endmodule
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Interfacesinterface top_if (input mclk, rst, strt);
tri [31:0] mb;logic [15:0] addr;logic mrd, mwr, mrf;modport mem_mp (inout mb,
input addr, mrd, mwr, mrf);modport ctrl_mp (inout mb,
output addr, mrd, mwr, mrf,input mclk, rst, strt);
endinterface: top_if
module top;top_if io (mclk, rst, strt);ctrl dut (io);mem m0 (io);…
endmodule
module ctrl (top_if.ctrl_mp io);always @(posedge io.mclk)
io.mrf = 1’b1;…
endmodule
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StructuresQuestion:
In Verilog, creating groups of common elements is difficult and we usually use common name prefixes. Does SystemVerilog provide a better method??
Answer:
Yes, SystemVerilog adds C like structures & unions giving users greater flexibility in grouping common elements within their design.
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Structures
Arrays are a collection of elements of the same data type and size
structures are a collection of elements that can be of different types and sizes
structures can be assigned to as a whole or to each individual members in the structure
Structures can be packed or unpacked
Packed structures can be signed or unsigned
Can be passed through ports
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Structures
reg [4:0] opcode, ra, rb, rc;reg [11:0] c3;always @(posedge clk, negedge rstn)
if (~rstn){opcode, ra, rb, rc, c3} = '0;
else{opcode, ra, rb, rc, c3} = dpb;
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Structurestypedef enum [4:0] {R[31]} reg_t;typedef enum [4:0] {
NOP, LD, ST, BR, ADD, SUB, NEG, AND, OR, NOT, SHR, SHL, STOP} opc_t;struct packed {
opc_t opcode;reg_t ra, rb, rc;logic [11:0] c3;
} IR;always @(posedge clk, negedge rstn)
if (~rstn)IR <= '0;
elseIR <= dpb;
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Structures
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Packed & Unpacked ArraysQuestion:
Even though Verilog 2001 added multi-dimensional arrays to the language, I still can’t access my array in a single statement. Does SystemVerilog add this capability?
Answer:
Yes, with SystemVerilog you can access a multi-dimensional array in a single statement provided it is completely packed.
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Packed & Unpacked ArraysA completely unpacked array:
reg array_3d [3:0][3:0][3:0];
The largest element that can be accessed at one time is a single bit:
array_3d[2][2][2] = 1’b1;
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Packed & Unpacked ArraysVerilog 2001 allows the user to pack arrays in one dimension only:
reg [3:0] array_3d [3:0][3:0];
At most, the array can be accessed in 4-bit slices:
array_3d[2][2] = 4’h6;
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Packed & Unpacked ArraysSystemVerilog allows the users to continue packing the array beyond one dimension:
reg [3:0][3:0] array_3d [3:0];
An array packed in two dimensions can be accessed 16-bits at a time:
array_3d[2] = 16’h16a8;
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Packed & Unpacked ArraysPacking ALL dimensions:
reg [3:0][3:0][3:0] array_3d;
The whole array can be accessed in a single statement:
array_3d = 64’h10fc16a80012aa0f;
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Direct Programming InterfaceQuestion:
I have a model written in C. Do I need to write all the PLI code in order to interface it with my verilog design?
Answer:
No, SystemVerilog provides a Direct Programming Interface (DPI) exactly for this purpose.
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Direct Programming Interface
DPI provides a natural inter-language interface between SystemVerilog and C/C++– Allows for other foreign languages in the future
Make function calls without writing PLI code– Call C/C++ functions from SystemVerilog
– Call SystemVerilog functions from C/C++
Data types are automatically converted
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Direct Programming InterfaceC Test
#define ADDR_BASE 0x10000000#define REG_ADDR ADDR_BASE + 0x100
void ctest(){
unsigned int data, HWIntVector;/* perform calculations in zero simulation time */data = someCfunction();
/* write to register in the DUT */writeHW(REG_ADDR, data);
/* read data & check */readHW(REG_ADDR, &data);
if (data != 0x1)printf(“Oh no!\n”);
return;}
Verilog Test Benchmodule TestBench;
initial begin// initial set-up using Verilog tasksSetUpSequence();
// run C verification testtop.ctest();
$finish(2);endtask writeHW;
input [31:0] addr;input [31:0] data;begin
CpuBusWrite(addr, data);end
endtask
task readHW;input [31:0] addr;output [31:0] data;begin
CpuBusRead(addr, data);end
endtaskendmodule
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Assertion-Based Verification
Assertion-Based Verification (ABV):“A verification methodology that ensures properties specified about the behavior of the design are not violated.”
SystemVerilog Assertions (SVA)– Part of the Accellera SystemVerilog language
Properties can reference internal state of the design– Enables white-box testing– Errors don’t need to propagate to primary outputs
Tools instrument the design with the properties
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Why ABV?
20%
40%
Early Detection■ Increases verification productivity
– Documents requirements and assumptions– Guide & direct stimulus generation– System and block verification
■ Measuring Verification Completeness
– Functional coverage not code coverage– Check corner cases and deep states – Allows controlled white-box verification of
IP
■ Increases Debug Productivity– White box: Bugs don’t have to propagate to
outputs– Bugs identified earlier– And closer to the source of the problem
60%
0%Spec Design Implement Test
Error Introduced
Error Observed
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SystemVerilog TestbenchSystemVerilog extends the Verilog queueReactive region executes after all active and nonblocking events– Assures race free communication between Testbench and DUT– Does NOT eliminate race conditions in designs - this is still
VerilogConstrained random stimulus generationNew synchronization and communication mechanisms– Semaphore and Mailbox built-in classes
Object oriented types and techniques– classes
Clocking domain– Tests defined in terms of cycles and transactions
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SystemVerilog Extended QueuePrevious Time Slot Current Time Slot
Preponed
Pre-active
Inactive
Next Time Slot
PLI
Active
Pre-NBA
NBA
Post-NBA
Observed
Post-Observed
Reactive
Postponed
PLI
PLI
PLI
Blocking AssignmentsEvaluate RHS NBA
Continuous Assignment$display
Eval inputs and update primitive outputs
#0 blocking assignments
Update LHS of NBA
New SV regions
$monitor and $strobe
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Using SystemVerilog in ModelSimSystemVerilog design components:
– part of our verilog compiler
– works with current verilog license
SystemVerilog verifications components:
– packaging and licensing TBD
Two methods to enable SystemVerilog in ModelSim
– use -sv switch with vlog during compilation
– use .sv file extension on source files
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SystemVerilog Support inModelSim 5.8
Sect 2.6 - String literalsSect 2.7 - Array literalsSect 2.8 - Structure literalsSect 3.3 - Integer data typesSect 3.7 - String data typeSect 3.9 - User-defined typesSect 3.10 - Enumerated data typeSect 3.11 - Structures and unionsSect 4.2 - Packed and unpacked arrays
Sect 4.6 - Dynamic arraysSect 4.6 - Dynamic array methodsSect 4.7 - Array assignmentSect 7.3 - Incr and decr operatorsSect 18.7.3 - Implicit .name port connectionSect 18.7.4 - Implicit .* port connectionSect 19.2 - Interfaces
Sect 19.3 - Ports in interfaces
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SystemVerilog - Most Useful Design Constructs
ModelSim 5.81) Simplified netlists with implicit port connections .* & .name2) Enumerated data types3) C like structures and unions4) User defined types5) Dynamic arrays including the predefined string data type6) Packed & unpacked arrays7) Increment & decrement operators ++/--8) Logic literals `1 `z `x9) Interfaces
Next release of ModelSim10) Direct Programming Interface11) Enhanced procedural blocks always_ff/comb/latch12) Void functions13) Unique & priority
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Future Support for SVAPSL VHDL supported in
ModelSim 5.8a
PSL Verilog flavor next
– Will work in SystemVerilog
SVA after PSL Verilog
Assertion engine and infrastructure being reused for SystemVerilog Assertions
PSL
ModelSim
Simulator User Interface
Tri-lingual Kernel
Assertion Engine
SystemVerilog Assertions
AssertionBrowser
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SystemVerilog SummaryTwo parts to SystemVerilog
– Design– Test & Verification
One language from start to finish– Its Verilog …– Therefore … Still includes all the RTL and gate constructs that designers need
ModelSim works today with many Design features -Testbench & Assertions under development
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SystemVerilog ResourcesSystemVerilog LRM available at:
http://www.eda.org/sv/SystemVerilog_3.1_final.pdf
SystemVerilog application note available at:
http://www.model.com/products/pdf/appnotes/SystemVerilog.pdf
“SystemVerilog For Design” by Stuart Sutherland:
Kluwer Academic Publishers (ISBN 0-4020-7530-8)
“SystemVerilog for Verification” available later this year
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Question & Answer