tackling the search for lepton flavor violation with ghz waveform digitizing using the drs chip
DESCRIPTION
Tackling the search for Lepton Flavor Violation with GHz waveform digitizing using the DRS chip. Stefan Ritt Paul Scherrer Institute, Switzerland. Agenda. MEG Experiment searching for m e g down to 10 -13. DRS1. DRS2. DRS3. Motivation. Why should we search for m e g ?. - PowerPoint PPT PresentationTRANSCRIPT
Tackling the search forLepton Flavor Violation
with GHz waveform digitizing using the DRS chip
Stefan RittPaul Scherrer Institute, Switzerland
Feb. 26th, 2008 Fermilab 2
Agenda
DRS2
DRS3
DRS1MEG Experiment searchingfor e down to 10-13
MotivationWhy should we search for e ?
Feb. 26th, 2008 Fermilab 4
The Standard ModelFermions (Matter)
Quarks
uup
ccharm
ttop
ddown
sstrange
bbottom
Leptons
eelectronneutrino
muon
neutrino
tau
neutrino
eelectron
muon
tau
Bosons
photon
Force carriers
ggluon
WW boson
ZZ boson Higgs*
boson
*) Yet to be confirmedGeneration I II III
Feb. 26th, 2008 Fermilab 5
The success of the SM• The SM has been proven to be extremely successful since
1970’s• Simplicity (6 quarks explain >40 mesons and baryons)• Explains all interactions in current accelerator particle
physics• Predicted many particles (most prominent W, Z )
• Limitations of the SM• Currently contains 19 (+10) free parameters such as
particle (neutrino) masses• Does not explain cosmological observation
such as Dark Matter and Matter/Antimatter Asymmetry
CDF
Today’s goal is to look for physics beyond the standard
model
Feb. 26th, 2008 Fermilab 6
Beyond the SM
Find New PhysicsBeyond the SM
High Energy Frontier• Produce heavy new particles directly• Heavy particles need large colliders• Complex detectors
High Precision Frontier• Look for small deviations from SM
(g-2) , CKM unitarity• Look for forbidden decays• Requires high precision at low energy
Feb. 26th, 2008 Fermilab 7
•Discovery: 1936 in cosmic radiation•Mass: 105 MeV/c2
•Mean lifetime: 2.2 s
The MuonSeth Neddermeyer
Carl Anderson
e
-
W- e-
e
e
e
e
e ≈ 100%
0.014
< 10-11
led to Lepton Flavor Conservationas “accidental” symmetry
Feb. 26th, 2008 Fermilab 8
LFV and Neutrino Oscillations
Neutrino Oscillations Neutrino mass e possible even in the SM
W-
ee-
SM
604
4B 10R( )W
e mm
LFV in the charged sector is forbidden in the Standard Model
mixing
Feb. 26th, 2008 Fermilab 9
LFV in SUSY• While LFV is forbidden in SM, it is possible in SUSY
W-
ee-
e-0~
~e~
SM
604
4B 10R( )W
e mm
SUSYBR( )e
4
5 2
SUS2
Y
2 100 GeV10 tanemmm
≈ 10-12
Current experimental limit: BR( e ) < 10-11
2~~em
Feb. 26th, 2008 Fermilab 10
History of LFV searches• Long history dating back to 1947!
• Best present limits:
• 1.2 x 10-11 (MEGA)
• Ti → eTi < 7 x 10-13 (SINDRUM II)
• → eee < 1 x 10-12 (SINDRUM II)
• MEG Experiment aims at 10-13
• Improvements linked to advancein technology
1940 1950 1960 1970 1980 1990 2000 2010
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-6
10-9
10-10
10-11
10-12
10-13
10-14
10-15
→ e → eA → eee
MEG
SUSY SU(5)BR( e ) = 10-13
Ti eTi = 4x10-16
BR( eee) = 6x10-16
cosmic
stopped
beams
stopped
Feb. 26th, 2008 Fermilab 11
Current SUSY predictions
“Supersymmetric parameterspace accessible by
LHC”W. Buchmueller, DESY, priv.
comm.
current limit
MEG goal
1) J. Hisano et al., Phys. Lett. B391 (1997) 3412) MEGA collaboration, hep-ex/9905013
ft(M)=2.4 >0 Ml=50GeV 1)
tan
Experimental MethodHow to detect e ?
Feb. 26th, 2008 Fermilab 13
Decay topology e
e
e
180º
→ e signal very clean• Eg = Ee = 52.8 MeV• e = 180º• e and in time
52.8 MeV
52.8 MeV
10 20 30 40 50 60 E[MeV]
N
52.8 MeV
10 20 30 40 50 60 Ee[MeV]
N
52.8 MeV
Feb. 26th, 2008 Fermilab 14
“Accidental” Background
e
e
180º
→ e signal very clean• Eg = Ee = 52.8 MeV• e = 180º• e and in time
e
e
e
e
Annihilationin flight
Background
Good energy resolutionGood spatial resolution
Excellent timing resolutionGood pile-up rejection
Feb. 26th, 2008 Fermilab 15
Previous Experiments
Exp./Lab
Author Year Ee/Ee %FWHM
E/E %FWHM
te
(ns)
e (mrad)
Inst. Stop rate (s-1)
Duty cycle (%)
Result
SIN (PSI)
A. Van der Schaaf
1977 8.7 9.3 1.4 - (4..6) x 105 100 < 1.0 10-9
TRIUMFP.
Depommier1977 10 8.7 6.7 - 2 x 105 100 < 3.6 10-9
LANLW.W.
Kinnison1979 8.8 8 1.9 37 2.4 x 105 6.4 < 1.7 10-10
Crystal Box
R.D. Bolton 1986 8 8 1.3 87 4 x 105 (6..9) < 4.9 10-11
MEGA M.L. Brooks 1999 1.2 4.5 1.6 17 2.5 x 108 (6..7) < 1.2 10-11
MEG ? ? ? ? ? ? ~ 10-13
How can we achieve a quantum step in detector technology?
Feb. 26th, 2008 Fermilab 16
Collaboration
~70 People (40 FTEs) from five countries
Feb. 26th, 2008 Fermilab 17
Paul Scherrer Institute
Swiss Light Source
Proton Accelerator
Feb. 26th, 2008 Fermilab 18
PSI Proton Accelerator
Feb. 26th, 2008 Fermilab 19
MEG beam line
+
R ~ 1.1x108 +/s at experiment
~ 10.9 mm
e+
+
Feb. 26th, 2008 Fermilab 20
Liquid Xenon Calorimeter• Calorimeter: Measure Energy, Position
and Time through scintillation light only• Liquid Xenon has high Z and homogeneity• ~900 l (3t) Xenon with 848 PMTs
(quartz window, immersed)• Cryogenics required: -120°C … -108°• Extremely high purity necessary:
1 ppm H20 absorbs 90% of light• Currently largest LXe detector in the
world: Lots of pioneering work necessary
Liq. Xe
H.V.
Vacuumfor thermal insulation
Al Honeycombwindow
PMT
Refrigerator
Cooling pipe
Signals
fillerPlastic
1.5m
Feb. 26th, 2008 Fermilab 21
• Use GEANT to carefully study detector
• Optimize placement of PMTs according to MC results
Feb. 26th, 2008 Fermilab 22
The complete MEG detector
1m
e+
Liq. Xe Scintilla tionDetector
Drift Chamber
Liq. Xe ScintillationDetector
e+
Tim ing Counter
Stopping TargetThin S uperconducting Coil
M uon Beam
Drift C hamber
Feb. 26th, 2008 Fermilab 23
Current resolution estimates
Exp./Lab
Author Year Ee/Ee %FWH
M
E/E %FWHM
te (ns)
e (mrad)
Inst. Stop rate (s-1)
Duty cycle (%)
Result
SIN (PSI)
A. Van der Schaaf
1977 8.7 9.3 1.4 - (4..6) x 105 100 < 1.0 10-9
TRIUMFP.
Depommier1977 10 8.7 6.7 - 2 x 105 100 < 3.6 10-9
LANLW.W.
Kinnison1979 8.8 8 1.9 37 2.4 x 105 6.4 < 1.7 10-10
Crystal Box
R.D. Bolton 1986 8 8 1.3 87 4 x 105 (6..9) < 4.9 10-11
MEGA M.L. Brooks 1999 1.2 4.5 1.6 17 2.5 x 108 (6..7) < 1.2 10-11
MEG 2008 0.8 4.3 0.18 18 3 x 107 100 ~ 10-13
Feb. 26th, 2008 Fermilab 24
MEG Current Status• Goal: Produce “significant” result before LHC• R & D phase took longer than anticipated• Detector has been completed by the
end of 2007• Expected sensitivity in 2008: 2 x 10-12
(current limit: 1 x 10-11)
R&D
199920002001200220032004200520062007200820092010
EngineeringData
Taking
Set-up
http://meg.psi.ch
Feb. 26th, 2008 Fermilab 25
Pile-up in the DC system• Pile-up can severely degrade the experiment performance (
MEGA Experiment) !• Traditional electronics cannot detect pile-up
TDC
Amplifier Discriminator Measure Time
Need fullwaveform digitization
> 100 MHz to reject pile-up
Moving average baseline
hit
s
Feb. 26th, 2008 Fermilab 26
Beam induced background
108 /s produce 108 e+/s produce 108 /s
Cable ductsfor Drift Chamber
Feb. 26th, 2008 Fermilab 27
Pile-up in the LXe calorimeter
n
E[MeV]50 51 52
e
radiativemuondecay
t
PMTsum
e
(e)2 +
e
51.5 MeV
0.511 MeV
• ’s hitting different parts of LXe can be separated if > 2 PMTs apart (15 cm)
• Timely separated ’s need waveform digitizing > 300 MHz
• If waveform digitizing gives timing <100ps, no TDCs are needed
~100ns
Feb. 26th, 2008 Fermilab 28
• Need 500 MHz 12 bit digitization for Drift Chamber system• Need 2 GHz 12 bit digitization for Xenon Calorimeter +
Timing Counters• Need 3000 Channels• At affordable price
Requirements summary
Solution: Develop own“Switched Capacitor Array” Chip
Feb. 26th, 2008 Fermilab 29
The Domino Principle
Shift RegisterClock
IN
Out
“Time stretcher” GHz MHz
Waveform stored
Inverter “Domino” ring chain0.2-2 ns
FADC 33 MHz
Keep Domino wave running in a circular fashion and stop by trigger Domino Ring Sampler (DRS)
Feb. 26th, 2008 Fermilab 30
Switched Capacitor Array
•Cons• No continuous acquisition• No precise timing• External (commercial) FADC needed
•Pros• High speed (~5 GHz) high resolution (~12 bit equiv.)
• High channel density (12 channels on 5x5 mm2)• Low power (10 mW / channel)• Low cost (< 100$ / channel incl. VME board)
t t t t t
Feb. 26th, 2008 Fermilab 31
Folded Layout
Linear inverter chain causes non-linearity
Feb. 26th, 2008 Fermilab 32
“Tail Biting”
enable
1 2 3 4
1
2
3
4
speed
Feb. 26th, 2008 Fermilab 33
Sample readout
0.2 pF 20 pF
DRS1Tiny signal
TemperatureDependence
~kT
DRS2I
DRS3
Feb. 26th, 2008 Fermilab 34
DRS3• Fabricated in 0.25 m
1P5M MMC process(UMC), 5 x 5 mm2, radiation hard
• 12 ch. each 1024 bins,6 ch. 2048, …, 1 ch. 12288
• Sampling speed 10 MHz … 5 GHz
• Readout speed 33 MHz, multiplexedor in parallel
• 50 prototypes receivedin July ‘06
CHANNEL 0IN0+IN0-
CHANNEL 1IN1+IN1-
CHANNEL 2IN2+IN2-
CHANNEL 3IN3+IN3-
CHANNEL 4IN4+IN4-
CHANNEL 5IN5+IN5-
CHANNEL 6IN6+IN6-
CHANNEL 7IN7+IN7-
CHANNEL 8IN8+IN8-
CHANNEL 9IN9+IN9-
CHANNEL 10IN10+IN10-
CHANNEL 11
STOP SH IFT REGISTER
READ SHIFT REGISTER
IN11+IN11-
WSRCLKSRIN
WSRO UTSRLO AD
RSRLOAD
WR
ITE
SH
IFT
RE
GIS
TER
DENABLEDW R ITEDSPEEDDM ODE
DOMINO WAVE CIR CUIT
DG ND
AGND
DVDD
AVDD
DTAP A0 A1 A2 A3
M UX
EN
AB
LE
M UXOUT /OUT0
OU T1
OU T2
OU T3
OU T4
OU T5
OU T6
OU T7
OU T8
OU T9
OU T10
OU T11BIASRO FS
SSROUT
RSRCLKRSRRST
RSROU T
Feb. 26th, 2008 Fermilab 35
VME Board32
cha
nnel
s inp
ut
General purpose VPC board built at PSI
40 MHz 12 bit FADC USB adapter
board
Feb. 26th, 2008 Fermilab 36
Bandwidth + LinearityReadout chain shows excellent linearity from 0.1V … 1.1V @ 33 MHz readout
Analog Bandwidth is currently limited by high resistance of on-chip signal bus, will be increased significantly with DRS4
AM
PLIT
UE
[dB
]
FREQUENCY [MHz]1 10 100
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
450 MHz (-3dB)
NO
NLI
NEA
RIT
Y [m
V]
ANALOG OUTPUT [V]0 0.2 0.4 0.6 0.8 1 1.2
-2
-1
0
1
2
ROFS = 0.95 VBIAS = 0.70 V
0.5 mV max.
Feb. 26th, 2008 Fermilab 37
Signal-to-noise ratio
“Fixed pattern” offset error of 5 mV RMScan be reduced to 0.35 mV by offsetcorrection in FPGA
SNR:
1 V linear range / 0.35 mV = 69 dB (11.5 bits)
AN
ALO
G O
UTP
UT [V
]
BIN NUMBER0 200 400 600 800 1000
0.48
0.49
0.5
0.51
0.52
Crosstalk from trigger signal
OC
CU
REN
CE
OUTPUT VOLTAGE [V]0.48 0.49 0.5 0.51 0.520
20
40
60
80
100
120
140
160
180
200
OC
CU
REN
CE
OUTPUT VOLTAGE [V]0.48 0.49 0.5 0.51 0.520
20
40
60
80
100
120
140
160
180
200
OffsetCorrection
Feb. 26th, 2008 Fermilab 38
12 bit resolutionW
AVEF
OR
M [V
]
TIME [ns]0 20 40 60 80 100 120 140 160 180 200
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
11.5 bits effective resolution <8 bits effective resolution
Feb. 26th, 2008 Fermilab 39
Sampling speed
PLL
ReferenceClock (1-4 MHz)
Vspeed
~200 psec~200 psec
• Unstabilized jitter: ~70ps / turn• Temperature coefficient: 500ps / ºC
f SAM
P[G
Hz]
DSPEED [V]0 0.5 1 1.5 2 2.5
0
1
2
3
4
5
6
30°C
50°C
R. Paoletti, N. Turini, R. Pegna, MAGIC collaboration
How far wan we go?
• 0.250 um technology: 8 GHz• 0.130 um technology: 15 GHz
Feb. 26th, 2008 Fermilab 40
Timing Reference
signal
20 MHz Reference clock
PMT hit
Domino stops aftertrigger latency
8 in
puts
shift registerReferenceclock
domino wave
MUX
• Calibrate inter-cell t’s for each chip• 200 ps uncertainty using PLL• 25 ps uncertainty for timing relative to edge
Feb. 26th, 2008 Fermilab 41
What timing can be obtained?
• Detailed studies by G. Varner1) for LAB3 chip
• Bin-by-bin calibration using a 500 MHz sine wave
• Accuracy after calibration: 20 ps
1) G. Varner et al., Nucl.Instrum.Meth. A583, 447 (2007)
1ns
Feb. 26th, 2008 Fermilab 42
On-chip PLL
PLL
ReferenceClock
fclk = fsamp / 2048
Vspeed
• On-chip PLL should show smaller phase jitter• If <100ps, no clock calibration required
loop
filte
r
DRS4
Simulation:
Feb. 26th, 2008 Fermilab 43
Comparison with other chipsMATACQ
D. BretonLABRADORG. Varner
DRS3
Bandwidth (-3db) 300 MHz > 1000 MHz 450 MHzSampling frequency
1 or 2 GHz 10 MHz … 3.5 GHz
10 MHz … 5 GHz
Full scale range ±0.5 V +0.4 …2.1 V +0.1 … 1.1VEffective #bits 12 bit 10 bit 12 bitSample points 1 x 2520 9 x 256 12 x 1024Channel per board
4 N/A 32
Digitization 5 MHz N/A 33 MHzReadout dead time
650 s 150 s 3 s – 370 s
Integral nonlinearity
± 0.1 % ± 0.1 % ± 0.05%
Radiation hard No No Yes (chip)Board V1729
(CAEN)- planned (CAEN)
Waveform AnalysisWhat can we learn from acquired waveforms?
Feb. 26th, 2008 Fermilab 45
On-line waveform display
click
templatefit
pedestalhisto
848PMTs
“virtual oscilloscope”
Feb. 26th, 2008 Fermilab 46
QT Algorithm
originalwaveform
smoothed anddifferentiated (Difference Of
Samples)Threshold in DOS
Region for pedestal
evaluation
integration area
t• Inspired by H1 Fast Track Trigger (A.
Schnöning, Desy & ETH)• Difference of Samples (= 1st derivation)• Hit region defined when DOS is above
threshold• Integration of original signal in hit region• Pedestal evaluated in region before hit• Time interpolated using maximum value
and two neighbor values in LUT 1ns resolution for 10ns sampling time
Feb. 26th, 2008 Fermilab 47
Pulse shape discrimination
)tt[...]θ.. )tθ(td)/τt(te
/τ)t(te i/τ)t(teAV(t) r00
000
CsB
Leading edge Decay time AC-coupling Reflections
Feb. 26th, 2008 Fermilab 48
-distribution
= 21 ns = 34 ns
Waveforms can be clearly
distinguished
Feb. 26th, 2008 Fermilab 49
Coherent noise
i Vi (t)All PMTs
Pedestal average
Charge integration
• Found some coherent low frequency (~MHz) noise
• Energy resolution dramatically improved by properly subtracting the sinusoidal background
• Usage of “dead” channels for baseline estimation
Feb. 26th, 2008 Fermilab 50
Pileup recognition
original
derivativet = 15ns
E1 E2
T 8ns
T 10ns
T 15ns
T 50ns
T 100ns
211EE
E
MC simulation
Rule of thumb: Pileup can be detected if T ~ rise-time of signals
Feb. 26th, 2008 Fermilab 51
Crosstalk elimination Crosstalk removal by subtracting empty channel
Hit Hit
subtract
Feb. 26th, 2008 Fermilab 52
Spurious Noise Problem• Found “sometimes” a high frequency
“ring” on all channels• 40 MHz, ~20 mV, 1kHz repetition• Finally identified the liquid xenon
pump as the source• This noise can screw up timing
for rare events• Without waveform digitizing, this
would have been very hard todebug
Feb. 26th, 2008 Fermilab 53
Template Fit• Determine “standard” PMT pulse by
averaging over many events “Template”• Find hit in waveform• Shift (“TDC”) and scale (“ADC”)
template to hit• Minimize 2
• Compare fit with waveform• Repeat if above threshold
• Store ADC & TDC values
Experiment500 MHz sampling
Feb. 26th, 2008 Fermilab 54
High pass filtering
originalwaveform
template fit
after optimized high pass FIR filter
integrationarea
• Get rid ofbaseline (lowfrequency)noise
• Improveresolutionsignificantly
Feb. 26th, 2008 Fermilab 55
Latc
h
Latc
h
Latc
h
Latc
h
Latc
h
Baseline Subtraction
BaselineSubtraction
Latc
h12 bit
100 MHz Clock
-+
<thr
+
-
BaselineRegister
Baselinesubtracted
signal LUT12x12
Calibrated and
linearized signal
Feb. 26th, 2008 Fermilab 56
Latc
h
Latc
h
Latc
h
Latc
h
Constant Fraction Discr.
Latc
h12 bit
Clock
+
+
MULT
Latc
h
0
&<0
Delayedsignal
Invertedsignal
Sum
Feb. 26th, 2008 Fermilab 57
Data Reduction• Zero suppression: hit if max. value > n
x (baseline)
• Readout window: start / width in respect to trigger
• Pile-up flag: Zero-crossings of first derivation
• Re-binning 4:1, 8:1, 16:1
• ADC: Numerical integral of hit over baseline
• TDC: Only simple threshold (usable to recognize accidentals) and time-over-threshold
MEG: Applying to 94% of 100 Hz dataKeeping only 6 Hz of waveforms
TOT
0.5 ns bins 4 ns bins
Feb. 26th, 2008 Fermilab 58
Huffman encodingDiff Bin. Code-1 00
0 01
1 10
2 11
Diff Bin. Code0 011 100 01-1 001 100 010 01-1 000 010 01
0
1
-1
2
0.6
0.2
0.2
00.2
0.4
1
0
1
10
11110
111
20 16
Huffman110
0
10
111
Huffman0100
1101000
11000
-10
-5
0
5
10
15
1
signal
diff
Feb. 26th, 2008 Fermilab 59
Where to perform waveform analysis?
• Switching from ADC/TDC to ~GHz waveform digitization increases amount of data by ~1000x
• Many algorithms suitable for on-board (FPGA) processing• Charge integration and time estimation (“QT”)• Zero-suppression, re-binning, Huffman encoding• Basic pile-up recognition (zero-crossings of derivative)
• Algorithms for embedded CPUs or PC farms• Inter-channel cross-talk removal• Template fit (floating point)
DRS FPGAFrontEndPC
Off-line Analysis
Feb. 26th, 2008 Fermilab 60
DAQ System Principle
Active Splitter
Drift Chamber Liquid Xenon Calorimeter Timing Counter
WaveformDigitizing
Trigger
TriggerEvent number
Event type
Busy
Rack PCRack PCRack PCRack PCRack PC
opticallink
(SIS3100)
Rack PCRack PCRack PCRack PC
Event Builder
Switch
GBit Ethernet
LVDS parallel bus
VME VME
Feb. 26th, 2008 Fermilab 61
Multi-threading model
VMETransferThread
CalibrationThread
CalibrationThread
CalibrationThread
CalibrationThread
CollectorThread
VME
Round-Robindistribution
Network
Zero-copy ring
buffers
Feb. 26th, 2008 Fermilab 62
Optimal rate with 4 calibration threads
Feb. 26th, 2008 Fermilab 63
DAQ System• Use waveform digitization
(500 MHz/2 GHz) on all channels
• Waveform pre-analysis directly in online cluster (zero suppression, calibration) using multi-threading
• MIDAS DAQ Software
• Data reduction: 900 MB/s 5 MB/s
• Data amount: 100 TB/year
2000 channelswaveform digitizing
DAQ cluster
Advanced TopicsReduced dead time, integrated triggering
Feb. 26th, 2008 Fermilab 65
“Residual charge” problem
R
“Ghost pulse”2% @ 2 GHz
After sampling a pulse, some residual charge remains in the capacitors on the next turn and can mimic wrong pulsesSolution: Clear before write
write clear Implementedin DRS4
Feb. 26th, 2008 Fermilab 66
ROI readout mode
readout shift register
Triggerstop
normal trigger stop after latency
Delay
delayed trigger stop
Patent pending!
33 MHz
e.g. 100 samples @ 33 MHz 3 us dead time
(2.5 ns / sample @ 12 channels)
Feb. 26th, 2008 Fermilab 67
Daisy-chaining of channels
Channel 0 – 1024 cells
Channel 1 – 1024 cells
Channel 2 – 1024 cells
Channel 3 – 1024 cells
Channel 4 – 1024 cells
Channel 5 – 1024 cells
Channel 6 – 1024 cells
Channel 7 – 1024 cells
Domino Wave Generation
DRS4 can be partitioned in: 8x1024, 4x2048, 2x4096, 1x8192 cells
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
Feb. 26th, 2008 Fermilab 68
Interleaved samplingde
lays
(200
ps/8
= 2
5ps)
G. Varner et al., Nucl.Instrum.Meth. A583, 447 (2007)
5 GSPS * 8 = 40 GSPS
Feb. 26th, 2008 Fermilab 69
“Almost” Dead time free system
CMC1
CMC232
chan
nel
16
chan
nel
MUX
VME board
One board is active while other board is read out
Feb. 26th, 2008 Fermilab 70
DRS4 packaging
6 4 -L ea d L Q F P
6 4 -L ea d Q F N
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31
50
32
49
3316341535143613371238113910409418427436445454463472481
DRS3TOP VIEW
(N ot to Scale )
PIN 1
DR S3TO P VIEW
(Not to Scale)
PIN 1
P IN C O N F IG U R AT IO N
A 0
A 0
IN8+
IN 8+A 1
A 1
IN8-
IN 8-A 2
A 2
IN7+IN 7+A 3
A 3IN7-
IN 7-OU T11 OU T 11IN6+ IN 6+OU T10 OU T 1 0IN6- IN 6-
OU T9OU T 9
IN5+ IN 5+
OU T8OU T 8
IN5-IN 5-
OU T7
OU T 7
IN4+
IN 4+
OU T6
OU T 6
IN4-
IN 4-
OU T5
OU T 5
IN3+
IN 3+
OU T4
OU T 4
IN3-
IN 3-
OU T3
OU T 3
IN2+
IN 2+
OU T2
OU T 2
IN2-
IN 2-
OU T1
OU T 1
IN1+
IN 1+
IN1-
IN 1-
DG
ND
DV
DD
DTA
PD
SPE
ED
DW
RIT
ED
EN
AB
LED
MO
DE
RO
FSIN
11+
IN11
-IN
10+
IN10
-IN
9+IN
9-
DV
DD
DG
ND
DG
ND
DV
DD
DTA
PD
SP
EE
DD
WR
ITE
DE
NA
BLE
DM
OD
ER
OFS
IN11
+IN
11-
IN10
+IN
10-
IN9+
IN9-
DV
DD
DG
ND
M U XO UT/OU T0
M U XO UT/OU T 0
AG
ND
AG
ND
AVDD
AVD
D
BIAS
BIA
S
SR
IN
SR
IN
RS
RLO
AD
RS
RLO
AD
RS
RC
LK
RS
RC
LK
RS
RO
UT
RS
RO
UT
RS
RR
ST
RS
RR
ST
SSR
LOAD
SS
RLO
AD
SSR
OU
T
SS
RO
UT
WSR
CLK
WS
RC
LK
WSR
OU
T
WS
RO
UT
IN0-
IN0-
IN0+
IN0+
AVDD
AVD
D
AG
ND
AG
ND
DRS3 DRS4
9 mm
18 mm
5 mm
DRS4flip-chip
Feb. 26th, 2008 Fermilab 71
New generation of FADCs• 8 simultaneous flash ADCs on one chip• Require
differentialinput
• DRS4 has beenredesigned withdifferentialoutput
Feb. 26th, 2008 Fermilab 72
Trigger an DAQ on same board
• Using a multiplexer, input signals can simultaneously digitized at 65 MHz and sampled in the DRS
• FPGA can make local trigger(or global one) and stop DRSupon a trigger
• DRS readout (5 GHz samples)though same 8-channel FADCs
• Multiplexer will be included in DRS4analog front end
DRSFADC12 bit
65 MHzM
UX FPGA
trigger
LVDS
SRAM
DRS4
glob
al tr
igge
r bus
No splitter (signal quality!), no dedicated trigger boards, no dedicated scalers
Feb. 26th, 2008 Fermilab 73
“Redefinition of DAQ”Because of the high channel density of the DRS system, it becomes
affordable to use waveform digitizing in experiments which today use ADC/TCDs
Conventional New
AC coupling Baseline subtraction
Const. Fract. Discriminator DOS – Zero crossing
ADC Numerical Integration
TDCBin interpolation (LUT)
Waveform Fitting
Scaler (250 MHz) Scaler (50 MHz)
Oscilloscope Waveform sampling
400 $ / channel 100 $ / channel
TDCDisc.
ADC
Scaler
Scope
FADC
FPGA
CPU
DRS ~GHz
~100MHz
Feb. 26th, 2008 Fermilab 74
Availability• DRS4 will become available in larger quantities
in summer ’08• Chip can be obtained from PSI on a “non-profit” basis
• Delivery “as-is”• Reference design (schematics) from PSI• Costs ~ 10-15$/channel• Costs decrease if we find sell more…
• Full VME board can be purchased from CAENprobably end of ’08 with firmware forpeak sensing ADC, QDC, …
• Struck, others, … ?32-channel
65 MHz/12bit digitizer“boosted” by
DRS4 chip to 5 GHz
Feb. 26th, 2008 Fermilab 75
Other experiments using DRS
MACE TelescopeIndia
PET scanners
BPM for XFEL@PSI
8 chn.withPGA
Magic Telescope, Canary Islands
Feb. 26th, 2008 Fermilab 76
Conclusions• Switched Capacitor Array techniques has prospects to trigger
a quantum step in data acquisition• The DRS chip has been designed with maximum flexibility
and can therefore be used in many applications• Collaboration on a scientific basis is very welcome
http://midas.psi.ch/drs
Datasheets, publications: