td-scdma digital front-end - design...

TD-SCDMA Digital Front-End Design Description

November 2006 MAC-EXFR-21-029

Commercial in Confidence 2/119

MAC-EXFR-21-029-01.01

This specification was commissioned by Xilinx.

Copyright © 2006 Multiple Access Communications Ltd

Multiple Access Communications LtdDelta House, Enterprise Road Southampton Science Park SOUTHAMPTON SO16 7NS, UK Tel: +44 (0)23 8076 7808 Fax: +44 (0)23 8076 0602


Revision History

Version Summary of Changes Date Author

01.00 Initial release. 03/11/2006 DK/TJ/SC

01.01 Updated following Xilinx review 07/11/2006 DK/TJ/SC

TBD Record

Section TBD Date needed


Table of Contents

List of Abbreviations ............................................................................................................... 10

1 Introduction...................................................................................................................... 12

1.1 Digital Front-End Architecture ................................................................................ 12

1.2 Performance Summary............................................................................................. 13

1.3 Target Platform ........................................................................................................13

1.4 Development Tools.................................................................................................. 14

1.5 Library Installation................................................................................................... 14

1.6 Nomenclature........................................................................................................... 14

1.7 Document Formatting Conventions......................................................................... 16

1.8 Document Structure ................................................................................................. 16

2 Digital Up-Converter ....................................................................................................... 17

2.1 Six-Channel DUC Subsystem.................................................................................. 18

2.1.1 Root-Raised Cosine Filter.................................................................................... 19

2.1.1.1 Spectrum Mask Requirements ..................................................................... 20

2.1.1.2 Adjacent Channel Leakage Ratio................................................................. 21

2.1.1.3 Error Vector Magnitude............................................................................... 22

2.1.1.4 Group Delay................................................................................................. 23

2.1.1.5 Design .......................................................................................................... 23

2.1.1.6 Implementation ............................................................................................ 24

2.1.2 First Interpolation Filter....................................................................................... 25

2.1.2.1 Design .......................................................................................................... 25

2.1.2.2 Implementation ............................................................................................ 26

2.1.3 Intermediate Mixer (With Combiner)..................................................................27

2.1.3.1 Gain Profile Adjustment .............................................................................. 27

2.1.3.2 Frequency Translation and Channel Combining ......................................... 27

2.1.3.3 Implementation ............................................................................................ 28


2.1.3.4 DDS for the Intermediate Mixer ..................................................................30

2.1.4 Second Interpolation Filter (Half-Band).............................................................. 31

2.1.4.1 Design .......................................................................................................... 31

2.1.4.2 Implementation ............................................................................................ 32

2.1.5 Third Interpolation Filter (Half-Band)................................................................. 33

2.1.5.1 Design .......................................................................................................... 33

2.1.5.2 Implementation ............................................................................................ 33

2.1.6 Composite Filter Response and Output Spectrum............................................... 34

2.2 IF Mixer and Direct Digital Synthesiser.................................................................. 35

2.2.1 Direct Digital Synthesiser .................................................................................... 36

2.2.1.1 Sine/Cosine Lookup Implementation Method.............................................36

2.2.1.2 Local Oscillator Output Interface ................................................................ 38

3 Digital Down-Converter .................................................................................................. 40

3.1 Data Path Resolution................................................................................................ 41

3.2 IF Mixer and Direct Digital Synthesiser.................................................................. 42

3.2.1 Quarter-Rate IF Mixer ......................................................................................... 42

3.2.2 ‘Full’ IF Mixer ..................................................................................................... 43

3.2.3 Direct Digital Synthesiser .................................................................................... 44

3.3 Six-Channel DDC Subsystem.................................................................................. 44

3.3.1 First Decimation Filter (Half-Band) .................................................................... 45

3.3.1.1 Design .......................................................................................................... 45

3.3.1.2 Implementation ............................................................................................ 46

3.3.2 Second Decimation Filter (Half-Band)................................................................ 47

3.3.2.1 Design .......................................................................................................... 47

3.3.2.2 Implementation ............................................................................................ 48

3.3.3 Gain Adjustment and Intermediate Mixer ........................................................... 48

3.3.3.1 Gain Adjustment and Intermediate Mixer Implementation .........................48


3.3.3.2 DDS for the Intermediate Mixer ..................................................................49

3.3.3.3 Optional Fixed Gain of Two........................................................................ 49

3.3.4 Third Decimation Filter ....................................................................................... 50

3.3.4.1 Design .......................................................................................................... 50

3.3.4.2 Implementation ............................................................................................ 51

3.3.5 Root-Raised Cosine Filter.................................................................................... 52

3.3.5.1 Design .......................................................................................................... 52

3.3.5.2 Implementation ............................................................................................ 53

3.3.6 Composite Filter Response ..................................................................................54

3.4 Simulated ACS, Blocking and EVM Performance.................................................. 55

3.5 Output Formatting Blocks........................................................................................ 57

4 DFE Performance............................................................................................................. 58

4.1 DUC Performance.................................................................................................... 58

4.1.1 Transmit Mask ..................................................................................................... 58

4.1.2 Occupied Bandwidth............................................................................................ 59

4.1.3 Adjacent Channel Leakage Ratio......................................................................... 59

4.1.4 Error Vector Magnitude....................................................................................... 60

4.1.5 DUC Delay........................................................................................................... 60

4.2 DDC Performance.................................................................................................... 61

4.2.1 Adjacent Channel Selectivity and Blocking ........................................................ 61

4.2.2 DDC Delay........................................................................................................... 62

4.3 Shared DUC and DDC components ........................................................................ 63

4.3.1 Spurious-Free Dynamic Range and Wideband Noise ......................................... 63

4.4 Performance Summary............................................................................................. 64

5 Interface Information ....................................................................................................... 65

5.1 DUC Library Blocks ................................................................................................ 65

5.1.1 DUC_OUT Block ................................................................................................ 65


5.1.1.1 Interface Description.................................................................................... 65

5.1.1.2 Mask Parameters.......................................................................................... 66

5.1.2 DUC Mixer Block................................................................................................ 67


5.1.3 TD-SCDMA DUC (6 Channels) Block ............................................................... 68


5.1.3.2 Mask Parameters.......................................................................................... 71

5.1.3.3 Gain Profile Interface................................................................................... 72

5.2 DUC Baseband Input Blocks ................................................................................... 75

5.2.1 DUC Baseband Input Formats .............................................................................75

5.2.1.1 Parallel I/Q................................................................................................... 76

5.2.1.2 Interleaved, Parallel I/Q............................................................................... 76

5.2.1.3 Serial, Interleaved I/Q.................................................................................. 77

5.2.1.4 Time-Division Multiplexed, Parallel I/Q..................................................... 78

5.2.1.5 ‘System Generator’ Interface....................................................................... 79

5.2.1.6 Transmit Enable Signal Interface.................................................................79

5.2.2 Using the DUC Baseband Input Blocks............................................................... 79

5.2.3 Specifying the Port Prefixes................................................................................. 80

5.3 DDC Library Blocks ................................................................................................ 81

5.3.1 DDC_IN Block .................................................................................................... 81


5.3.1.2 Mask Parameters.......................................................................................... 82

5.3.2 DDC 1/4-Rate Mixer Block ................................................................................. 83


5.3.3 DDC Mixer Block................................................................................................ 84


5.3.4 TD-SCDMA DDC (6 Channels) Block ............................................................... 85



5.3.4.2 Mask Parameters.......................................................................................... 87

5.4 DDC Baseband Output Blocks ................................................................................ 88

5.4.1 DDC Baseband Output Formats .......................................................................... 89

5.4.1.1 Parallel I/Q................................................................................................... 89

5.4.1.2 Interleaved, Parallel I/Q............................................................................... 90

5.4.1.3 Serial, Interleaved I/Q.................................................................................. 91

5.4.1.4 Time-Division Multiplexed, Parallel I/Q..................................................... 92

5.4.1.5 ‘System Generator’ Interface....................................................................... 93

5.4.2 Using the DDC Baseband Output Blocks............................................................ 93

5.4.3 Specifying the Output Port Prefix........................................................................ 95

5.5 Shared DDC/DUC Library Blocks .......................................................................... 95

5.5.1 Local Oscillator Block ......................................................................................... 95


5.5.2 Control Constant Block........................................................................................ 97


5.5.2.2 Mask Parameters.......................................................................................... 98

5.5.3 IF_DATA_CE and BB_DATA_CE Blocks ........................................................ 99


5.5.3.2 Mask Parameters.......................................................................................... 99

6 Resource Summary ........................................................................................................ 101

6.1 Resource Estimates for the Main Library Blocks ..................................................101

6.2 Resource Estimates for Example DFE Configurations..........................................103

References.............................................................................................................................. 105

Appendix A – Library Overview ........................................................................................... 106

Appendix B – Example Designs ............................................................................................ 112

B.1 Example 18-Channel DDC Design........................................................................ 112


B.2 Example 18-Channel DUC Design........................................................................ 115

B.3 Changing the Simulation Target ............................................................................ 117

Appendix C – Full-Speed DFE Demonstration Application ................................................. 118

C.1 Introduction............................................................................................................ 118

C.2 Prerequisites........................................................................................................... 118

C.3 Running the Full-Speed Design ............................................................................. 119

C.4 Further Information................................................................................................ 119


List of Abbreviations

ACLR Adjacent channel leakage ratio

ACS Adjacent channel selectivity

ADC Analogue-to-digital converter

AEAE An example abbreviation entry

BS Base station

BW Bandwidth

DAC Digital-to-analogue converter

DDC Digital down-converter

DDS Direct digital synthesiser

DFE Digital front-end

DSP Digital signal processing

DUC Digital up-converter

EVM Error vector magnitude

FDD Frequency-division duplex

FIR Finite impulse response

FPGA Field-programmable gate array

IF Intermediate frequency

I/O Input/output

IP Intellectual property

I/Q In-phase/quadrature

LO Local oscillator

LUT Lookup table

MAC Multiply-accumulate

PRBS Pseudo-random binary sequence

RAM Random-access memory

RF Radio frequency


RMS Root-mean-square

ROM Read-only memory

RRC Root-raised cosine

TD-SCDMA Time division synchronous code division multiple access

TxEn Tansmit enable

SFDR Spurious-free dynamic range

TDD Time-division duplex

TDM Time-division multiplexed


1 Introduction

This document describes the time division synchronous code division multiple access (TD-

SCDMA) digital front-end (DFE) library for System Generator for DSP (System Generator)

that Multiple Access Communications Ltd (MAC Ltd) has developed under contract for

Xilinx.

1.1 Digital Front-End Architecture

A conceptual view of a simple, multi-channel DFE is shown in Figure 1. A multi-channel

analogue front-end interfaces a multi-element antenna array to the DFE implemented in one

or more Xilinx field-programmable gate arrays (FPGAs). The DFE can be subdivided into

two sections; down-conversion and decimation of the received, digitised signals is performed

by the digital down-converter (DDC); interpolation, up-conversion and combining of the

transmit data is performed by the digital up-converter (DUC). Modulation and demodulation

is performed by a separate digital baseband processor.

Digital Front-End (DFE)

Digital Up-Converter (DUC)

Digital Down-Converter (DDC)AnalogueFront-End

DAC

ADC

Rx

Cha

nnel

sTx

Cha

nnel

s

Multi-ElementAntenna Array

Figure 1 High-level, conceptual view of a multi-channel DFE.


1.2 Performance Summary

Table 1 lists some of the key features/characteristics of the TD-SCDMA DFE library design.

Parameter Value Notes

IF sample rate 76.8 MSps DDC real/DUC complex

Baseband sample rate 1.28 MSps Complex

System clock frequency 307.2 MHz

Internal signal path resolution 18 bits

Maximum number of carriers per antenna 6 Single DUC/DDC solution

Carrier raster 200 kHz

IF bandwidth 9.6 MHz

IF tuning resolution <0.1 Hz

IF DDS SFDR > 100 dBc fLO = 16 MHz

IF DDS wideband noise < -145 dBc/Hz fLO = 16 MHz

DUC occupied bandwidth >99.9% 3GPP spec’: The power in a 1.6 MHz band must exceed 99% of the total Tx power

DUC adjacent-channel leakage ratio (ACLR) >80 dB

3GPP spec’: The ACLR must exceed 40 dB in the first adjacent channel

DUC in-band filter ripple < ±0.01 dB f = ±0.4992 MHz

DUC EVM 1.6% RMS 3GPP spec’: EVM must be less than 12.5%

DUC signal path delay 15.2 µs Incl. serial input format

DDC adjacent-channel selectivity (ACS) > 75 dB 3GPP spec’: 49 dB

DDC blocking > 80 dB 3GPP spec’: 64 dB

DDC in-band filter ripple -0.02/+0.01 dB f = ±0.4992 MHz

DDC EVM < 0.2% RMS Simulated

DDC signal path delay 14.9 µs Incl. serial output format

1.3 Target Platform

The DFE is implemented as a ‘library’ of System Generator intellectual property (IP) blocks.

System Generator is a blockset that extends The MathWorks’ Simulink product and enables

Table 1 DFE performance summary.


Xilinx FPGA designs to be developed and tested rapidly. Completed designs can then be

synthesised and ‘built’ directly, all from within the Simulink environment. The DFE library

is optimised for implementation in Xilinx’s high-performance Virtex-4 SX digital signal

processing (DSP) family of FPGAs.

1.4 Development Tools

Implementation and development of the TD-SCDMA DFE library was completed using

Matlab Version 7.2 (R2006a), Simulink Version 6.4 (R2006a) and Xilinx System Generator

for DSP Version 8.1.01. In addition, the full-speed demonstration design was developed

using Xilinx ISE Version 8.1.03i and Version 6.0 of the FUSE Toolbox for Matlab.

1.5 Library Installation

The DFE library is supplied either as a compressed ZIP file or on CDROM. The structure of

the library files is described in Appendix A. To use the library, extract the contents of the

ZIP file or copy the contents of the CDROM to a suitable working location on a local hard

drive.

For designs instantiating blocks from the DFE library it is necessary for the dfe_library and

dfe_library\low level directories to be added to the Matlab path. This can be achieved by

browsing to the dfe_library directory from within Matlab and running addLibraryToPath.m

(ie, type addLibraryToPath at the Matlab command line). Alternatively, add the directories

manually using Matlab’s ‘pathtool’ utility (invoked by typing pathtool at the Matlab

command prompt).

Once present on the Matlab path, the top-level library blocks should appear in the ‘Simulink

Library Browser’.

If the DFE library is no longer required, the library directories may be removed from the

Matlab path using the pathtool utility.

1.6 Nomenclature

In the subsequent discussions, we use the term channel to describe the signals required to

support a single radio frequency (RF) carrier. Therefore, when discussing complex baseband

signals, a ‘channel’ consists of two real data streams, ie, in-phase (I) and quadrature (Q)


components. Thus, a single-channel filter operating at baseband, for example, actually

incorporates two separate data paths.


1.7 Document Formatting Conventions

This document uses a number of formatting conventions to help distinguish different entities.

The formatting conventions followed are summarised in Table 2.

Style Simulink signal or block name

Filename or directory name Matlab command-line text

1.8 Document Structure

The design and implementation of the DUC is discussed in Section 2 and Section 3 discusses

the design and implementation of the DDC. In Section 4 examples of the measured

performance of the final solution are presented for some of the key performance criteria.

Section 5 lists the top-level library blocks and provides detailed descriptions of the interfaces

to these blocks. Finally, in Section 6 resource estimates are presented for the main library

blocks together with a couple of examples showing how to use these values to generate

resource estimates for typical design configurations.

The structure of the library files, as supplied, is described in Appendix A. A brief overview

of the example designs supplied with the library is provided in Appendix B and an

introduction to the full-speed demonstration application is provided in Appendix C.

Table 2 Document formatting conventions.


2 Digital Up-Converter

The purpose of the DUC is to translate a sequence of complex baseband data samples at the

TD-SCDMA chip rate (fCHIP = 1.28 Mcps) to a digital intermediate frequency (IF). The DUC

also applies the necessary pulse-shaping characteristics and combines up to six waveforms to

generate a composite multi-channel signal that can be converted into a quadrature analogue

waveform by digital-to-analogue converters (DACs). Each channel occupies a nominal

bandwidth of 1.6 MHz and so, assuming that the separation between each channel is

1.6 MHz, the maximum composite signal bandwidth is 9.6 MHz. To simplify up conversion

and the filtering functions that follow the DAC, the composite IF signal is translated en-

masse to a centre frequency (typically in the region of 19.2 MHz). This centre frequency

may either be fixed at one-quarter of the DAC sampling rate, fDAC = 76.8 MHz, or, by the

inclusion of a digital mixer, may be programmable.

To accommodate the wider bandwidth of the IF signal, compared to the baseband signal, the

up-conversion process must also include interpolation so that the sampling rate obeys the

Nyquist criterion with respect to the composite IF signal. The design presented in this

document assumes a fixed interpolation rate of 60, ie, the output sample rate is 76.8 MSps.

This interpolation process is implemented in several stages as this reduces the overall

complexity of the required filters.

To maximise the efficiency with which the design utilises the resources within the FPGA, the

DFE design is designed to operate with a system clock frequency four times fDAC, ie,

307.2 MHz. This corresponds to 240 clock cycles per complex input sample.

The basic building block of the DUC is a six-channel block, which accepts six baseband

inputs, interpolates and applies burst gain profiling, mixes each channel to its allotted

frequency, combines the six channels into one composite signal and interpolates the

composite signal to the DAC sampling rate. This block includes an optional ‘quarter-rate’

complex mixer to mix the composite signal to 19.2 MHz. Alternatively an external mixer

block may be used to mix the composite signal to any arbitrary IF. These processes are

illustrated in the block diagram shown in Figure 2. In the following sections we will describe

each stage of the process in detail, covering the background requirements, a summary of the

implementation and the measured performance.


2.1 Six-Channel DUC Subsystem

The six-channel DUC subsystem is implemented in the dfe_library/DUC Blocks/TD-SCDMA

DUC (6 Channels) block. The contents of this block are reproduced in Figure 3. The baseband

input to each channel consists of interleaved I/Q data sampled at the chip rate. These inputs

operate at the system clock rate, ie, 307.2 MHz. Valid I and Q input data are flagged using a

Freq. Offset(±4.0 MHz)

IF Mixer

Gain Profile, Intermediate Mixer and Combiner

IF Frequency

Sync.


Sync.

Channel 6Complex I/Q(1.28 MSps)

2


IF I/Q Output(76.8 MSps)

Local Oscillator

InputFormat

InputFormat

3RRC

3RRC

5

2Σ DAC

5

RAM

Gain ProfileData

RAM

Gain ProfileData

Tx Enable(TxEN)

Figure 2 Six-channel DUC block diagram.

2Q Out

1I Out

sysgend

enqz-1

Register Q

sysgend

enqz-1

Register I

Intermediate6-Ch DUC Mixer(With Combiner)

IQ(1)

IQ(2)

IQ(3)

IQ(4)

IQ(5)

IQ(6)

Rdy

Is Q

TxEn

Sync

Freq(1)

Freq(2)

Freq(3)

Freq(4)

Freq(5)

Freq(6)

Gain_Addr

Gain_Data

Gain_WE

I

Q

Rdy

Intermediate 6-Ch DUC Mixer (With Combiner)

IQ In

Enable

IQ Out

Gate Channel 6

IQ In

EnableIQ Out

Gate Channel 5

IQ In

Enable

IQ Out

Gate Channel 4

IQ In

Enable

IQ Out

Gate Channel 3

IQ In

EnableIQ Out

Gate Channel 2

sysgen↓4z-1

sysgen↓4z-1

DUCFilter 4

(Post Mixer)

I In

Q In

Rdy In

Sync

I Out

Q Out

Rdy Out

DUC Fi lter 4 (Post Mixer)

DUCFilter 3

(Post Mixer)

I In

Q In

Rdy In

I Out

Q Out

Rdy Out

DUC Fi lter 3 (Post Mixer)

DUCFilter 2

IQ In

Rdy In

Is Q In

TxEn In

IQ Out

Rdy Out

Is Q Out

TxEn Out

DUC Fi lter 2Channel 6

DUCFilter 2

IQ In

Rdy In

Is Q In

TxEn In

IQ Out

Rdy Out

Is Q Out

TxEn Out


DUCFilter 2

IQ In

Rdy In

Is Q In

TxEn In

IQ Out

Rdy Out

Is Q Out

TxEn Out


DUCFilter 2

IQ In

Rdy In

Is Q In

TxEn In

IQ Out

Rdy Out

Is Q Out

TxEn Out


DUCFilter 2

IQ In

Rdy In

Is Q In

TxEn In

IQ Out

Rdy Out

Is Q Out

TxEn Out


DUCFilter 2

IQ In

Rdy In

Is Q In

TxEn In

IQ Out

Rdy Out

Is Q Out

TxEn Out


DUCFil ter 1

IQ In

Rdy In

Is Q In

TxEn In

IQ Out

Rdy Out

Is Q Out

TxEn Out

DUC Fil ter 1Channel 6

DUCFil ter 1

IQ In

Rdy In

Is Q In

TxEn In

IQ Out

Rdy Out

Is Q Out

TxEn Out


DUCFil ter 1

IQ In

Rdy In

Is Q In

TxEn In

IQ Out

Rdy Out

Is Q Out

TxEn Out


DUCFil ter 1

IQ In

Rdy In

Is Q In

TxEn In

IQ Out

Rdy Out

Is Q Out

TxEn Out


DUCFil ter 1

IQ In

Rdy In

Is Q In

TxEn In

IQ Out

Rdy Out

Is Q Out

TxEn Out


DUCFil ter 1

IQ In

Rdy In

Is Q In

TxEn In

IQ Out

Rdy Out

Is Q Out

TxEn Out


17Gain_WE

16Gain_Data

15Gain_Addr

14Freq6

13Freq5

12Freq4

11Freq3

10Freq2

9Freq1

8Sync

7TxEn

6IQBus 6

5IQBus 5

4IQBus 4

3IQBus 3

2IQBus 2

1IQBus 1

<IQ>

<Rdy >

<Is Q>

<IQ>

<Rdy >

<Is Q>

<IQ>

<Rdy >

<Is Q>

<IQ>

<Rdy >

<Is Q>

<IQ>

<Rdy >

<Is Q>

<IQ>

<Rdy >

<Is Q>

<Enable>

<Enable>

<Enable>

<Enable>

<Enable>

<Enable>

Figure 3 The six-channel DUC subsystem.


ready signal, Rdy, and a framing strobe, Is Q. For convenience, these signals, together with

the I/Q data on IQ and a channel enable signal, Enable, are combined into six Simulink

‘buses’, one for each input channel. This logical grouping of signals greatly simplifies the

top level implementation of DFE designs.

The input data are interpolated by a factor of three and have the necessary pulse-shaping

characteristic applied by the pulse-shaping filter (DUC Filter 1 *). A second interpolation stage

(DUC Filter 2 *) then interpolates the data by a further factor of five. These filters are

replicated for all six channels. At the output of the second filter for channels two to six, there

is a Gate Channel * subsystem, which consists of an AND gate controlled by the Enable input

signal. The purpose of this block is to enable the implementation tools to remove the logic

associated with any unused input channels. This simplifies the use of the library as it frees the

user from the need to manually remove the unused logic. Unused input channels can be

optimised out of the design by tying Enable low, which can be performed using the Unused BB

Input block.

Burst gain profiling and frequency mixing are applied to each channel before all six channels

are summed together in the Intermediate Mixer (With Combiner) block. This block supports the

application of a user-defined scaling factor to prevent overflow. This factor must be specified

at build time and is applied prior to the channel summation. The I and Q sample data are

deinterleaved within the intermediate mixer. Thus the output from this block consists of

separate I and Q data buses. The composite output from the mixer is passed through two

further interpolation filter stages (implemented by the DUC Filter 3 (Post Mixer) and DUC Filter 4

(Post Mixer) blocks, respectively), which are both half-band filters. An optional quarter-rate

mixer stage is incorporated in the final filter stage to centre the output spectrum on

19.2 MHz. By default this mixer stage is disabled, ie, the output is centred on DC.

Finally, the I and Q signals are registered, so that the output of the TD-SCDMA DUC (6

Channels) block consists of the I and Q buses running at the IF sample rate, ie, 76.8 MSps.

See Section 5.1.3 for further information on the interface of this block.

2.1.1 Root-Raised Cosine Filter

The purpose of the root-raised cosine (RRC) filter is to provide pulse-shaping of the input

data symbols that, in turn, determines the spectral characteristics of the transmitted signal.

Consequently, the performance requirements of this filter are driven by four factors; the


spectrum mask, the adjacent channel leakage ratio (ACLR), the error vector magnitude

(EVM) and the group delay.

2.1.1.1 Spectrum Mask Requirements

The spectrum mask requirements are a function of the base station (BS) transmit power.

Section 6.6.2.1.2 of 3GPP specification TS 25.105 [1] specifies the mask requirements for

three ranges of BS transmit power, P; P < 26 dBm, 26 dBm ≤ P < 34 dBm, P ≥ 34 dBm. For

reference, the spectrum mask requirements for P ≥ 34 dBm are repeated in Table 3. The

requirements for other BS power levels are no more restrictive than this and so can be

ignored for the purposes of this analysis. We note that the measurements are specified at

bandwidths (BWs) of 30 kHz and 1 MHz and that these are both different to the bandwidth

over which the wanted signal power, P, is spread. So, to derive the necessary filter

attenuation from this table we must normalise the signal and measurement bandwidths. The

wanted channel power, P, is spread over the channel bandwidth, which for the purposes of

this calculation we can assume to be 1.28 MHz. Thus, taking P = 34 dBm, the power per unit

bandwidth is 34 − 10×log10 (1.28×106) = -27 dBm/Hz. Normalising the spectrum emission

masks to their measurement bandwidths yields the figures shown in Table 4, in which the

final column shows the difference between the normalised signal power and the normalised

emission limits.

Frequency Offset, fOffset (MHz) Maximum Emission (dBm) Measurement BW

0.815 ≤ fOffset < 1.015 -20 30 kHz

1.015 ≤ fOffset < 1.815 -20 – 10 × (fOffset – 1.015) 30 kHz

1.815 ≤ fOffset < 2.300 -28 30 kHz

2.300 ≤ fOffset < ∆fMax -13 1 MHz

Table 3 Table 6.3A of TS 25.105 [1]. Spectrum emission mask limits for BS output power, P > 34 dBm.


Frequency Offset, fOffset (MHz) Normalised Maximum Emission (dBm/Hz)

Filter Requirement (dB)

0.815 ≤ fOffset < 1.015 -65 -38

1.015 ≤ fOffset < 1.815 -65 to -73 -38 to -46

1.815 ≤ fOffset < 2.300 -73 -46

2.300 ≤ fOffset < ∆fMax -73 -46

We note that the specified emission limits are specified as absolute values and we have

calculated the filter requirements on the basis of P = 34 dBm. If P is greater than 34 dBm

then the filter requirements will increase by 1 dB for every dB that P exceeds 34 dBm.

Furthermore we must allow some margin for distortion in the analogue components, which

will cause some bandwidth expansion, and so our final filter requirements should be set,

perhaps, 20 dB tighter than the limits shown in Table 4.

2.1.1.2 Adjacent Channel Leakage Ratio

ACLR is another transmitter requirement that is affected by the root-raised cosine filter

characteristic. As its name implies, ACLR is the amount of power emitted by a BS in an

adjacent channel compared to the power emitted in the intended channel. The specification

for this can be found in Section 6.6.2.2 of TS 25.105 [1]. For convenience the limits are

reproduced in Table 5.

BS Adjacent Channel Offset Below the First or Above the Last Carrier Frequency Used ACLR Limit

1.6 MHz 40 dB

3.2 MHz 45 dB

The specified method of measuring ACLR is to apply the transmitted signal to a matched

root-raised cosine filter tuned first to the frequency of the intended channel and then to the

adjacent channel frequencies and to measure the filtered power in each case. Since the

measurement bandwidth is the same when measuring the intended signal and the adjacent

channel leakage, we can take the values in Table 5 as the direct requirements for the root-

raised cosine filter. Since the values in Table 5 are less than the values determined by the

Table 4 Normalised spectrum emission mask requirements.

Table 5 BS ACLR specification, reproduced from Table 6.7A of TS 25.105 [1].


spectrum emission mask requirement, it may seem that the ACLR requirements are met by

meeting the emission mask requirements. However, there are other ACLR specifications

that, although not mandatory, are in practice necessary for reliable system operation. These

specifications, covered in Sections 6.6.2.2.2 and 6.6.2.2.3 of TS 25.105, govern operation

when co-located with other BSs, which may be either other time-division duplex (TDD)

equipment or frequency-division duplex (FDD) equipment. The most restrictive case

requires that emissions at ±1.6 MHz from the centre of the intended channel must be less than

-73 dBm; equivalent to -107 dB compared to a 34 dBm output power. Such a demanding

specification will require an analogue filter operating in combination with a tightly specified

root-raised cosine filter and so we have set the design target for the root-raised cosine filter at

80 dB.

This requirement has the effect of tightening the emissions mask across the adjacent channel,

centred at an offset of 1.6 MHz from the intended channel. Ideally we require that the filter

has greater than 80dB attenuation across the band 1.6 ± 0.64 MHz. However, since the filter

frequency response is not flat over this band we can allow the attenuation to be slightly less

than 80 dB at the edge closest to the intended channel. Consequently we specify that the

attenuation requirement has a linear slope between 1.015 MHz and 1.1 MHz and is flat

thereafter. The composite limit line is shown together with the simulated filter response in

Figure 4.

2.1.1.3 Error Vector Magnitude

EVM is a measure of the distortion in the transmitted waveform compared to a perfect

waveform. Section 6.8.2.1 of TS 25.105 specifies that the EVM must be less than 12.5%. In

practice most of the signal distortion will occur in the analogue domain (primarily as a result

of non-linear distortion in the power amplifier stages) and so the digital system is specified to

produce a signal with an EVM of less than 2.5%. A simple analytical method of converting

from an EVM requirement to a specification of the filter performance does not exist, but

empirical results show that the length of the filter is the most important factor. In practice we

find that a filter that is sufficiently long to meet the emission mask requirements will easily

meet the EVM requirements.


2.1.1.4 Group Delay

The group delay of a linear, finite impulse response (FIR) filter with symmetrical coefficients

is equal to half the length of the filter. A design goal is that the overall delay through the

DUC is no greater than 15 µs. This corresponds to approximately 19 ‘chips’ (a chip period is

approximately equal to 0.78 µs). Obviously the overall delay is affected not only by the

length of the pulse-shaping filter, but also by the other filters. However, this first stage is the

dominant contributor. Determining the optimum filter lengths is an iterative process,

requiring several iterations to find an acceptable trade off between the various measurement

parameters.

2.1.1.5 Design

In the preceding sections we have presented the factors that determine the required

performance characteristics of the root-raised cosine filter. We now turn to consider the

practical aspects of designing a filter to meet these requirements.

In the preamble to Section 2 we stated that the input data must be interpolated by a factor of

60 and that this would be handled in several stages. Cascading several stages of low

interpolation factors is more efficient than a few stages using higher interpolation factors

because the required image rejection filters are simplified in this way. By considering each

of the available options for providing a total interpolation ratio of 60, we decided upon four

stages with interpolation factors of three, five, two and two. Thus, the root-raised cosine

filter is required to interpolate by three.

Another specified factor of the root-raised cosine filter is its rolloff factor, α, which is

specified in TS 25.105 Section 6.8.1 as 0.22. Designing a root-raised cosine filter with

α = 0.22 and an interpolation factor of three to meet the spectrum emission mask

requirements is not a problem. However, designing it to also meet the 80 dB ACLR

requirement demands a filter with several hundred coefficients (which would greatly exceed

the maximum signal path delay design goal). The approach taken to keep the filter to a

manageable length is to apply a window to its coefficients. Windowing the filter’s impulse

response improves its stop band attenuation at the expense of a slight increase in the width of

the pass and transition bands and a slight deterioration in EVM performance. To compensate

for the increase in the width of the pass band we can reduce the rolloff factor slightly

provided that we are careful not to introduce too much distortion into the resulting waveform.


By undertaking an evaluation of a range of filter lengths, rolloff factors and window

functions we concluded that a 97-tap filter, with α = 0.12, and a Kaiser window having a

window parameter of four provided the best compromise.

The simulated floating- and fixed-point responses of the pulse-shaping filter are shown in

Figure 4. The red line represents the mask requirements. The dotted maroon line represents

the ‘ideal’ RRC characteristic. The effects of the windowing and reduction of α can be seen

clearly, although simulation shows that the EVM requirement is still met with a clear margin.

2.1.1.6 Implementation

The RRC filter is implemented by the dfe_library_low_lvl_duc/DUC Filter 1 block. This filter is

implemented using a multiply-accumulate (MAC) architecture. I and Q data are input and

output as interleaved samples. This enables a single DSP48 to be shared between both

channels efficiently.

The filter uses a single dual-port block random-access memory (RAM) to perform the

following functions:

• Store the I and Q sample data

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0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8-0.01

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Figure 4 Root-raised cosine filter characteristic.


• Store the filter coefficients

• Store the mapping between the filter state and the various control signals.

One port of the block RAM is dedicated to the management of the sample data and the other

to the generation of the coefficient and control data. The read-only contents of the block

RAM are defined in the mask initialisation code for the filter.

The state counter used to control the filter and the counters used to generate the read and

write addresses for the sample data are implemented using ‘pseudo-random binary sequence

(PRBS)’ counters rather than conventional binary counters. This design decision was taken

in order to minimise the logic requirements of the various counters. It not only reduces the

size of the filter, but also eases the task of meeting timing by minimising the number of logic

levels within the counters.

The RRC filter implementation also has a Boolean transmit enable (TxEn) signal input and

output that is used for gain profiling (see Section 2.1.3.1). The TxEn signal is delayed to

match the delay through the filter.

Finally, the RRC filter scales the input data by a factor of 1/2 (-6 dB), which is implemented

by scaling the filter coefficients. This scaling factor is required to compensate for overshoot

in the response of the filter, which would otherwise result in clipping of the filter output.

Note that this scaling is not required in the subsequent filters as sufficient headroom is

provided by the scaling factor applied in the RRC filter.

2.1.2 First Interpolation Filter

2.1.2.1 Design

Following the root-raised cosine filter is an interpolation filter with an interpolation rate of

five, taking the sampling rate at its output to 15 times the chip rate, ie, 19.2 MSps. This filter

does not influence the shape of the transmitted signal and its purpose is to remove the signal

images that will be created as a side effect of interpolation. These images will appear at

multiples of the input sampling rate (3.84 MSps) and so the stop band edge is determined by

the need to remove a signal having 1.6 MHz bandwidth centred on 3.84 MHz. Thus, the stop

band must begin at 3.04 MHz. The pass band must be flat over the bandwidth of the

baseband signal, which for the purposes of designing this filter we set at 600 kHz.


The amount of stop band attenuation is determined by the need to prevent any signal images

appearing at the DUC output. Since the dynamic range of a 16-bit data path is 96 dB plus

any processing gain due to over-sampling, which is a function of the DAC sampling rate, we

set the attenuation requirement at 100 dB.

Using Matlab to design a filter to this specification we find that a 40-tap equiripple design,

with a weighting factor of 20 in the stop band comes sufficiently close to our requirement.

The frequency response of the 40-tap filter is shown in Figure 5 together with the filter design

goal (shown in red). From Figure 5 we can see that the fixed point implementation does not

quite meet the design goal at the frequencies corresponding to peaks in the stop band ripple.

However, between these the stop band attenuation exceeds 100 dB and thus the overall

attenuation of the signal images will meet our 100 dB target.


The first interpolation filter is implemented by the dfe_library_low_lvl_duc/DUC Filter 2 block.

The implementation of this filter is similar to the root-raised cosine filter, see Section 2.1.1.6.

However, this filter is not required to scale the input data by 1/2 to compensate for overshoot

in the filter response as sufficient headroom is generated by the preceding root-raised cosine

filter.

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Figure 5 First interpolation filter characteristics.


As with the root-raised cosine filter, the first interpolation filter supports a Boolean transmit

enable signal for use in the implementation of gain profiling (see Section 2.1.3.1). The TxEn

signal is delayed to match the delay through the filter.

2.1.3 Intermediate Mixer (With Combiner)

The Intermediate 6-Ch DUC Mixer (With Combiner) block accepts input data from up to six

channels, ie, from six different sets of RRC and first interpolation filters. This block

performs a number of functions. Firstly, burst gain profiling is applied to each channel. Next

each channel is shifted by a programmable frequency offset. Finally, the channel data are

summed together to produce a composite output signal.

2.1.3.1 Gain Profile Adjustment

To limit out of band emissions caused by rapidly switching the TD-SCDMA signal on and

off, the power profile of each burst must be carefully controlled. The TD-SCDMA frame

format provides a guard interval of eight chips before and after a burst during which the

transmitted power may be smoothly raised and lowered. Figure 6.1A in Section 6.5.2.1.2 of

TS 25.105 [1] specifies the transmit on/off mask that must be adhered to.

The gain profile logic allows the user to apply an amplitude profile to both the I and Q

channels so that the power profile as measured at the antenna meets the specified mask. This

requires an additional input control signal to the intermediate mixer, known as transmit

enable (TxEn), which specifies when the ramp-up and ramp-down profiles should commence.

It is important that TxEn is correctly synchronised with the baseband data samples.

Note that the DUC does not include independent channel gain adjustment in addition to the

gain profile function. However, the gain profile data can be specified on a per-channel basis.

Therefore gain adjustment on a per-channel basis can be emulated by modifying the gain

profile data for each channel. Note that the gain profile data are not double-buffered by the

DUC so extreme caution should be exercised if reprogramming the gain profile data in a

‘live’ system.

2.1.3.2 Frequency Translation and Channel Combining

Following the burst gain profile stage, a complex mixer allows each baseband channel to be

translated to a different IF. The intermediate mixer supports a tuning range of ±4.0 MHz


with a tuning step size of 200 kHz. The mixer output for each channel is summed together to

produce a composite waveform consisting of six TD-SCDMA carriers.

Without careful control of the input data, it is possible for the output of the complex mixer to

exceed the available amplitude range. Although the intermediate mixer includes logic to clip

the output and prevent overflow for small signal excursions, such events will seriously

degrade the quality of the output signal. To prevent clipping the mixer supports the

specification of a fixed scaling factor that is applied to the sample data before they are

combined. (Alternatively, the user has the option of applying a suitable scaling factor to the

input data before they are presented to the DUC.) By default, the gain, which is specified on

the block mask, is set to 1/6. This enables six channels to be summed together without

saturation. If fewer channels are used, the gain factor can be increased as appropriate.


The burst gain profiling, frequency mixing and channel combining are implemented by the

dfe_library_low_lvl_duc/Intermediate 6-Ch DUC Mixer (With Combiner) block. In order to make

efficient use of the FPGA resources it is desirable to share each DSP48 between as many

channels as possible whilst keeping the logic required to support any such resource sharing to

sensible levels. For simplicity the gain adjustment and frequency translation functions have

been kept separate, ie, separate resources are dedicated to each.

Each of the six inputs to the intermediate mixer consists of a 19.2 MSps complex data stream,

ie, 15 times the chip rate, with I and Q data on an interleaved data bus. The first operation is

to interleave the six input data channels onto a single interleaved bus. This enables a single

DSP48 to be used to apply the gain profile to the input data.

A conceptual illustration of the timing of the intermediate mixer with combiner signals is

shown in Figure 6. (Note that this is for illustrative purposes only and does not accurately

portray the latency through the stages of the implemented intermediate mixer block.)


The gain profile logic generates the gain values (G1 to G6) for each input channel. Each

amplitude profile consists of 120 samples for the ramp-up, and 120 samples for the ramp-

down, and these are stored in a dual-port block RAM. The gain profile is applied at a rate of

15 time fCHIP, resulting in a ramp period of 120 / 15 = 8 chips (6.25 µs at 1.28 Mcps), as

defined by the 3GPP specifications. Application of the gain profile is controlled using the

TxEn signal. To enable the user to program the gain-profile waveforms, the second port of

the block RAM is connected to top-level ports. Further details on the gain profiling interface,

including the operation of the TxEn signal, can be found in Section 5.1.3.3.

The output of the first DSP48 is a repeating, interleaved I/Q data stream weighted by the gain

control data for all six channels. Frequency translation for each channel is implemented

using a complex mixer. A full, complex multiply requires four multiplications and two

additions. With 16 clock cycles available, a single DSP48 can support up to four channels;

therefore we require two DSP48s to implement the mixer for six channels. Using two

DSP48s allows the data stream to be de-interleaved into separate I and Q output data streams,

which simplifies the implementation of the filters that follow the intermediate mixer.

The control logic for the direct digital synthesiser (DDS) used to generate the local oscillator

(LO) data for the intermediate mixer is designed to output cosine (Cx) and sine (Sx) data in an

appropriate sequence aligned with the weighted I/Q data, as shown in Figure 6. Using the

I1

G1 G2 G6

I2.G2 I3.G3 I4.G4 I5.G5 I6.G6I1.G1

C2 C3 C4 C5 C6C1

Accumulate values for I output using DSP48 accumulator

Interleaved I/QData

Interleaved GainData

Output of ‘Gain’DSP48

Output of MixerDDS (I)

Output of MixerDDS (Q)

1 / 19.2 MSps

I2 I3 I4 I5 I6 Q1 Q2 Q3 Q4 Q5 Q6

G3 G4 G5 G2 G6G3 G4 G5G1

Q2.G2 Q3.G3 Q4.G4 Q5.G5 Q6.G6Q1.G1

S2 S3 S4 S5 S6S1

-S2 -S3 -S4 -S5 -S6-S1

C2 C3 C4 C5 C6C1

Output of ‘Mixer’multiplier (I) I1.G1.C1 I2.G2.C2 I3.G3.C3 I4.G4.C4 I5.G5.C5 I6.G6.C6

-Q1.G1.S1

-Q2.G2.S2

-Q3.G3.S3

-Q4.G4.S4

-Q5.G5.S5

-Q6.G6.S6

I1.G1.S1 I2.G2.S2 I3.G3.S3 I4.G4.S4 I5.G5.S5 I6.G6.S6Q1.

G1.C1

Q2.G2.C2

Q3.G3.C3

Q4.G4.C4

Q5.G5.C5

Q6.G6.C6

Output of ‘Mixer’multiplier (Q)

Accumulate values for Q output using DSP48 accumulator

Figure 6 Conceptual timing diagram showing the operation of the six-channel gain profiling, intermediate mixer and channel combiner.


separate DSP48s for the mixer, we obtain I and Q outputs by accumulating the output of the

multipliers over all twelve weighted values. The output from the DSP48 is the composite

waveform for all six channels, with each channel translated to its selected IF.

Logic on the output of the mixer DSP48s is provided to detect overflow and clip the output

value if required; however, this operates over a limited range and the output can wrap-around

if the inputs are large enough. To prevent overflow the user must set the scaling factor in the

block mask appropriately according to the number of channels that are being used, and also

ensure that the complex input to the mixer does not have a magnitude greater than unity.

2.1.3.4 DDS for the Intermediate Mixer

The DDS used to generate the LO data for the intermediate mixer is required to support a

tuning range of ±4.0 MHz with a tuning step size of 200 kHz. With a sampling rate of

19.2 MSps, a complete cycle of a 200 kHz sinusoid can be represented by exactly 96

samples. All other frequencies offered by the intermediate mixer can be generated using a

subset of these 96 samples. This means that an efficient, high-performance, multi-channel

DDS can be implemented with minimal block RAM resources and without the need for any

noise-shaping techniques such as phase dithering.

The simulated SFDR performance of the DDS implemented in the intermediate mixer

(assuming no amplitude scaling) is shown in Figure 7. The green line represents the peak

output power for all allowable frequencies in the range ±4.0 MHz and the blue line represents

the peak spurious power (ie, with the fundamental output tone suppressed). As indicated by

the dotted red line, SFDR is greater than 110 dBc. Note that simulation shows that this limit

is imposed by the 18-bit resolution of the data in the DDS lookup table (LUT) only, not the

architecture of the DDS.


The intermediate DUC mixer allows the sample data to be scaled by a constant scaling factor

that can be specified at build time. If the scaling factor specified is not a power of two, the

‘remainder’ is implemented by reducing the amplitude of the DDS output. Note that

reducing the amplitude of the DDS output may have a slight detrimental effect on the SFDR.

A single block RAM is used to store the DDS lookup table. The ROM is organised into four

128-word ‘pages’ storing cos (x), sin (x) and -sin (x) waveforms. The data required by the

multiplier to perform complex LO multiplications can thus be generated by accessing the

different pages of the ROM in the appropriate order. The dual-port nature of the Virtex 4

block RAM means that the same block RAM can be shared between both the I and Q output

channels.

2.1.4 Second Interpolation Filter (Half-Band)

2.1.4.1 Design

The composite signal generated by the mixer and channel combiner is interpolated to the

DAC sampling rate in two further stages, both of which interpolate the input data by a factor

of two. This approach is chosen in preference to a single interpolate-by-four stage because

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Figure 7 Simulated SFDR performance of the intermediate mixer.


interpolation by a factor of two can make use of computationally efficient half-band filters

and the cascading of two such filters requires less processing than the single stage approach.

The requirements for the first half-band filter are determined as follows. The input sampling

rate is 19.2 MSps and so the output rate is 38.4 MSps. The combined six channel signal

occupies a bandwidth of 9.6 MHz, thus the minimum pass band width we require is 4.8 MHz.

For a half-band filter the frequency of the stop band is determined by the choice of pass band

and, as with the first interpolation filter, we set the stop band attenuation requirement at

100 dB. Using the least-squares method (firls in Matlab) to design the half-band filter we

find that 27 taps are required in order to meet the stop band attenuation requirement. The

frequency response of this filter is shown in Figure 8.


The second interpolation filter is implemented by the dfe_library_low_lvl_duc/DUC Filter 3

block. As with the other DUC filters, this filter is implemented using a MAC architecture.

Unlike the first two filter stages, however, I and Q data are processed on separate parallel

buses, with a separate DSP48 operating on each channel. A single block RAM is used to

store the sample data, filter coefficients and control data. The read-only contents of the block

RAM are defined in the mask initialisation code for the filter.

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Figure 8 Second interpolation filter (half-band) characteristics.


Note that the logic used to generate the address for the sample data is carefully designed to

only read data corresponding to non-zero coefficients to be read. This is necessary because

there are not sufficient clock cycles available to be able to also read the data corresponding to

the zero coefficient taps. This complicates the sample data address generation logic compared

to the first two filters which do not have coefficients that are zero.

2.1.5 Third Interpolation Filter (Half-Band)

2.1.5.1 Design

The second half-band interpolating filter is designed in the same way as the first. The input

and output sampling rates are 38.4 MSps and 76.8 MSps, respectively, and the pass band is

4.8 MHz wide and the stop band begins at 33.6 MHz. We find that we can get close to the

100 dB stop band attenuation requirement using an 11-tap filter, the response of which is

shown in Figure 9.


The third interpolation filter is implemented by the dfe_library_low_lvl_duc/DUC Filter 4 block.

The implementation of this filter is similar to the second interpolation filter, see Section

2.1.4.2.

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Figure 9 Third interpolation filter (half-band) characteristics.


The third interpolation filter also implements an optional quarter rate IF mixer, that will

centre the output spectrum on an IF of 19.2 MHz. This can be enabled by selecting the

relevant option in the block mask. The quarter-rate mixer multiplies the input data by a

19.2 MHz complex sinusoid sampled to produce the repeating sequence [+1, j, -1, -j].

The sign change is implemented using the DSP48s, which saves logic resources over using

inverters, and multiplexers on the output of the DSP48s are used to swap the I and Q signals

when multiplying by j. The signals for controlling the sign inversion and multiplexers are

stored in the block RAM and defined in the block mask initialisation code.

As can be seen above, the quarter-rate mixer operates in one of four ‘phases’. To allow

multiple instances (possibly in separate designs) to be synchronised, the third interpolation

filter has a synchronisation input to reset the phase of the quarter-rate mixer.

2.1.6 Composite Filter Response and Output Spectrum

Table 6 summarises the DUC filter stages. As stated previously, the delay of a linear FIR

filter is equal to half the length of its impulse response. Therefore, we find that the

theoretical delay through the DUC filter chain is equal to 49/3.84 + 20.5/19.2 + 14/38.4 +

6/76.8 = 14.27 µs. However, this does not include the delay through the mixers, input/output

stages or any other implementation delays.

Filter Stage Output (MSps)

Length (Taps)

Pass Band (MHz)

Stop Band (MHz)

Ripple (dB Pk-Pk)

Windowed RRC 3.84 97 0.50 - ±0.001

Interpolate-by-five 19.2 40 0.60 3.04 ±0.002

Half-band 1 38.4 27 4.80 14.4 <±0.001

Half-band 2 76.8 11 4.80 33.6 <±0.001

So far we have only considered each of the filter stages in the DUC signal path in isolation.

Figure 10 shows the composite frequency response of all four DUC filters. (Note that for the

purposes of Figure 10 it is assumed that no frequency translation occurs between the second

and third filter stages.) The red line represents the design requirement assumed for the pulse-

shaping filter. It can be seen that all images introduced by the interpolation process are all

attenuated by close to 100 dB. A close up of the pass band shows ripple to be very much less

than ±0.01 dB.

Table 6 DUC filter summary.


Note that Figure 10 shows the theoretical floating- and fixed-point frequency response of the

DUC filters only. In practice, the dynamic range of the 16-bit DUC output would introduce a

noise floor that will obscure all but the strongest aliased images. Moreover, if used with the

external mixer block the noise spectrum of the phase-dithered DDS will further mask the

aliased images.

2.2 IF Mixer and Direct Digital Synthesiser

The last (optional) stage of the DFE DUC signal path is a mixer and local oscillator to

translate the composite six-channel from baseband to an IF frequency. A quarter-rate mixer

built into the final interpolation filter in the 6-channel DUC subsystem can be used to

translate all six carriers en-masse to a centre frequency of 19.2 MHz, with minimal FPGA

resource overhead. Alternatively, if a different or programmable centre frequency is

required, a ‘full’ DUC IF mixer can be used, albeit, with increased FPGA resource utilisation.

Such a mixer is implemented by the dfe_library/DUC Blocks/DUC Mixer block.

This block uses a single DSP48 to implement a complex mixer. The input and output of the

mixer run at the DAC sampling rate (76.8 MHz). As each complex multiply requires four

multiplies and three additions, the mixer runs at the full sample rate, ie, four times the DAC

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Figure 10 Composite DUC filter response.


sampling rate. The system generator ‘up sample’ and ‘down sample’ blocks are used to

implement the rate changes.

The mixer is designed to accept LO data from the Local Oscillator block (see Section 3.2.3).

This interface interleaves sine and cosine magnitude data on a common data bus and uses a

flag to signal when these data should be treated as negative values. This magnitude-plus-sign

format minimises resource utilisation by allowing logic that would otherwise be required on

the output of the sine/cosine lookup table to be merged into the DSP48. The mixer block

implements unbiased rounding at the output of the DSP48 to minimise the introduction of DC

offset. Note that the mixer is configured to mix up by the LO frequency.

2.2.1 Direct Digital Synthesiser

The full IF mixer requires an external source to supply the local oscillator data. A suitable

source is the dfe_library/Shared DDC/DUC Blocks/Local Oscillator block. This block consists of a

32-bit phase accumulator that updates at the IF data rate (ie, once every four clock cycles)

and a sine/cosine lookup table. With a 32-bit phase accumulator, the local oscillator can be

tuned with a resolution finer than 0.02 Hz.

2.2.1.1 Sine/Cosine Lookup Implementation Method

With a 32-bit phase word, the implementation of the sine/cosine lookup table requires careful

consideration. To implement a lookup table with a one-to-one phase mapping, ie, with a

32-bit address, is impossible as such a lookup table would require over one million block

RAM! The simplest solution is to simply truncate the output of the phase accumulator and

use the M most-significant bits to perform the sine/cosine lookup. However, as the size of the

lookup table is reduced, the SFDR reduces also. An example is shown in Figure 11 (middle).

Here the simulated SFDR is shown for all output frequencies in the range 10 to 30 MHz in

200 kHz steps assuming a sine/cosine lookup table with a 13-bit address. The SFDR in this

example is approximately 76.6 dBc. For comparison, Figure 11 (top) models a ‘full’ 32-bit

lookup (with 18-bit LUT data).


Due to the symmetry of a sinewave, it is only necessary to store one-quarter of a sinusoid

when implementing a basic DDS lookup table; the two most-significant bits of the phase can

be used to reconstruct both sine and cosine waveforms from the stored quarter-wave. This

means that the example shown in Figure 11 (middle) with the 13-bit phase lookup would

require just two block RAM. As a rule-of-thumb, SFDR performance can be improved by

approximately 6 dB for every additional bit used to perform the sine/cosine lookup.

Therefore, to achieve a SFDR of better than 100 dBc using phase truncation alone would

require a 17-bit lookup address and a total of 32 block RAM. This is unacceptable.

Two main noise shaping techniques exist for DDS implementations. The first is to use phase

dithering, whereby a random ‘noise’ signal is added to the signal used to address the DDS

LUT to ‘spread’ any spurious power across a wider band, thereby increasing the SFDR. The

second approach is to use mathematical methods, eg, Taylor series correction [2], to

minimise the error introduced by the phase truncation process. The latter, although better in

terms of SFDR and wideband noise performance, is more expensive in terms of the logic

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Pow

er (d

BFS

CW

)

Peak PowerPeak Spurious PowerMeasured SFDR (114.34 dBc)

-30 -20 -10 0 10 20 30

-100

-50

0

Frequency (MHz)

Pow

er (d

BFS

CW

)


-30 -20 -10 0 10 20 30

-100

-50

0

Frequency (MHz)

Pow

er (d

BFS

CW

)


Figure 11 Simulated SFDR performance for a DDS with full phase lookup (top), truncated phase lookup (middle) and dithered phase lookup (bottom) for all frequencies between 10 and 30 MHz in 200 kHz steps. The simulation assumes a 32-bit phase accumulator, 18-bit output data and, where applicable, an 8K sine/cosine lookup table.


resources required; from the Xilinx CORE Generator DDS datasheet [2], “the additional

resources required over the phase truncation DDS are two embedded multipliers, one

constant coefficient multiplier, and four adders”. Given that adequate performance could be

achieved in a more cost-effective manor using the phase dithering method it was decided to

adopt this technique for the purposes of the DFE library.

With phase dithering, spurious performance is traded for increased wideband noise power.

An example is given in Figure 11 (bottom). Here, the eight most-significant bits of a 16-bit

pseudo-random binary sequence (PRBS) generator1 have been added to the output of the

phase accumulator prior to truncation2. This example uses the same 13-bit lookup table used

in the example of Figure 11 (middle). As can be seen, the SFDR has been improved by

almost 30 dB to approximately -105 dBc, but this improvement is at the expense of the

wideband noise spectral density which has also increased. The examples given in Figure 11

were all generated using a 128K-point FFT (which has a bin width of approximately 586 Hz)

weighted using a flat-top window (with an equivalent noise bandwidth of approximately 3.77

bins [3]). Integrating the noise power within ±0.8 MHz of the fundamental output of the

phase dithered DDS produces a wideband noise spectral density of approximately

-146 dBc/Hz.

The DDS implemented in the DFE library is based on the example used to generate

Figure 11 (bottom). Thus, the DDS uses a 13-bit lookup table (requiring two block RAM)

together with a 16-bit PRBS dither generator.

2.2.1.2 Local Oscillator Output Interface

To achieve efficient resource utilisation, the Local Oscillator block outputs the real (ie, cosine)

and imaginary (ie, sine) parts on a common bus. The timing of this interface, which is

inherently linked to the timing of the four times clock enable generated by System Generator,

is shown in Figure 12. The [cos(x), sin(x), sin(x), cos(x)] output sequence of this

block has been designed to make the Local Oscillator block compatible with both DUC Mixer

and DDC Mixer mixer blocks (the DDC Mixer block only uses the first and third output states).

1 A 16-bit PRBS generator can be implemented by combining taps 11, 13, 14 and 16 using an XOR gate. 2 The ‘noise’ signal is weighted such that the most-significant bit aligns with the most-significant truncated bit.


As stated in the previous section, in order to minimise block RAM utilisation, only one-

quarter of a sinusoid is stored in read-only memory (ROM). Ordinarily, this requires an

adder on the output of the ROM to allow negative outputs to be produced. However, we note

that a feature of the DSP48 used in the mixer block is that the sign of the multiplier output

can be controlled dynamically. Effectively, therefore, it is possible to merge the DDS output

logic with the DSP48 in the mixer. As a result, the output of the local oscillator block

actually consists of a data bus, Mag, conveying magnitude data and a Boolean flag, Sign, that

is asserted to indicate that the sign of the magnitude data should be inverted. Both of these

signals are shown in Figure 12. For convenience, these two signals are combined and output

from the Local Oscillator block as a Simulink ‘bus’. This simplifies the construction of the

designs at the top level as there is only a single connection required between the local

oscillator and the mixer(s).

Mag

Sign

1 / 76.8 MSps

LO

CE (×4)

Clk

‘IF Data’

| cos (θ0) |

cos (θ0) < 0

| sin (θ0) |

sin (θ0) < 0

| sin (θ0) |

sin (θ0) < 0

| cos (θ0) |

cos (θ0) < 0

D0

| cos (θ1) |

cos (θ1) < 0

Figure 12 Timing of the Local Oscillator block LO output.


3 Digital Down-Converter

The purpose of the DDC is to translate modulated TD-SCDMA signals superimposed on a

real, digital IF to baseband, apply the necessary pulse-shaping characteristics and output

complex baseband sample data at the chip rate. The basic DDC system can extract up to six

carriers within a 9.6 MHz band from a single IF input.

The DDC is designed to accept IF sample data from an analogue-to-digital converter (ADC)

at 76.8 MSps (ie, 60 times the chip rate). The main six-channel DDC building block accepts

complex input data nominally centred on a zero-IF (note: we subsequently use the term

baseband synonymously with zero-IF). To interface the data from the ADC to this block the

user can add a ‘quarter-rate’ mixer block to translate real IF data centred about 19.2 MHz to

complex baseband. Alternatively, a ‘full’ mixer block can be used together with a local

oscillator block to allow IFs other than 19.2 MHz to be used.

Between the input and the output the sample data are decimated by a factor of 60. This

decimation process is implemented in several stages in order to minimise the complexity of

the individual filter stages. To maximise the efficiency with which the design utilises the

resources within the FPGA, the DFE design is designed to operate with a system clock

frequency four times the input sample rate, ie, 307.2 MHz. This corresponds to 240 clock

cycles per complex output sample.

The general architecture of the DDC is shown in the block diagram of Figure 13. In the

Prog. Gain(×0 - ×1)

5 3RRC×2


Prog. Delay(0 - TCHIP)

IF Mixer

Intermediate Mixer and GainAdjustment Fixed Output Gain

ADC2

IF Frequency

Sync.

Prog. Gain(×0 - ×1)

5 3RRC×2


Sync.

Prog. Delay(0 - TCHIP)


2

×A

×A


Real IF Input(76.8 MSps)

Local Oscillator

OutputFormat

OutputFormat

Figure 13 Six-channel DDC block diagram.


following sections we will describe each stage of the process in detail, covering the

background requirements, a summary of the implementation and the measured performance.

3.1 Data Path Resolution

The resolution of the input data can be up to 16 bits. When less than 16 bits are used, the

input data will be ‘left-justified’ in 16 bits, with zeros used to ‘pad’ the unused bits. Within

the Simulink environment, the input data are always represented as values in the range ±1.0.

The final filter stage of the DDC can be configured at build time to output between eight and

24 bits. In addition, the DDC can be configured to have a fixed gain of between 0 and

+30 dB gain (in 6 dB increments). This feature is useful when using the DDC with a

restricted number of output bits to allow ‘small’ signals to be made visible at the output.

Internally the DDC signal path has 18 bits of precision regardless of the number of input or

output bits. Where the result of an operation exceeds 18 bits rounding is applied before the

data are passed to the next stage. This minimises the introduction of any DC offset at the

output.

Figure 14 illustrates the data resolution along the DDC signal path assuming a 14-bit ADC.

When a signal is oversampled by an ADC and subsequently filtered to its actual bandwidth

an extra bit of useful information is gained for every factor of four that the input data are

oversampled. Thus, approximately three bits resolution can be gained along the DDC signal

path. For the example shown in Figure 14, this means that for channel gains greater than,

say, ×1/8 (-18 dB) an 18-bit signal path is sufficient. As attenuation is increased further, data

will be lost first at the output of the third filter stage and then at the output of the intermediate

mixer with gain stage itself.


Figure 14 shows that, although the output of the DDC can be configured with up to 24 bits, it

is not possible to get more than 19 useful bits of information out of the DDC, due to the width

of the data path into the last filter stage.

3.2 IF Mixer and Direct Digital Synthesiser

The first stage of the DFE DDC signal path is to translate the real IF input data to quadrature

baseband. Note that the IF input will typically be a composite signal with components on

multiple carriers. The DFE DDC can simultaneously down-convert up to six carriers within a

9.6 MHz band. In this scenario, the input signal needs to be translated in frequency such that

the carriers to be extracted are a) within the range ±4.8 MHz and b) are aligned to a 200 kHz

raster. The DFE library includes two variants of mixer that can be used to implement this

frequency translation.

3.2.1 Quarter-Rate IF Mixer

The simplest IF mixer option is the quarter-rate mixer. This is implemented by the

dfe_library/DDC Blocks/DDC 1/4-Rate Mixer block.

The quarter-rate mixer multiplies the input data by a -19.2 MHz complex sinusoid sampled to

produce the repeating sequence [+1, -j, -1, +j]. Thus the quarter-rate mixer operates in

one of four ‘phases’ and can be implemented using adders and registers. The adders in the

2

6

10

14

18

4

8

12

16

0

Dat

a P

ath

Res

olut

ion

(Bits

)

2220

24

Information lost dueto 18-bit internal

signal path

No usefulinformation in

these bits

ADC ×2BB Output(Complex)

IF Mixer Intermediate Mixer and Gain

IF Input(Real)

No usefulinformation in

these bits

Internal signal pathhas 18 bits from the

output of the IF mixer

2 2 5 3×A

+0.50 bit gain(decimate by 2)




×1/1×1/4

×1/16×1/64

0.5-bit ‘lost’ because full-scalesinusoid input has RMS power

of 1/√2 not 1

Additional 0.5-bit ‘lost’ because the power ofthe wanted signal is reduced by 3 dB in the

mixer (the remaining power is mixed to 2×fIF)

A 14-bit ADC is assumed

Ran

ge o

f bits

out

put w

hen

conf

igur

ed w

ith24

-bit

outp

ut a

nd fi

xed

×2 (+

6 dB

) gai

n

Ran

ge o

f bits

out

put w

hen

conf

igur

ed w

ith16

-bit

outp

ut a

nd fi

xed

×16

(+24

dB

) gai

n

Programmable Gain(×0 - ×1)

RRC

Figure 14 DDC signal path data resolution.


implemented design operate at the input sample rate not at the clock rate to avoid timing

issues resulting from the size of the adders.

To allow multiple instances of the mixer (possibly in separate designs) to be synchronised, a

synchronisation input is provided which, when asserted, will reset the phase of the mixer.

The quarter-rate mixer outputs new sample data every four clock cycles, the timing of which

is inherently linked to the ×4 clock enable generated by System Generator. Internally,

therefore the synchronisation signal needs to be aligned with the clock enable. For

convenience, however, it is desirable that the synchronisation input responds to single-cycle

events. Thus some logic to re-time input events to align with the clock enable is required.

The operation of this logic, implemented within the Capture Sync subsystem, is shown in

Figure 15.

3.2.2 ‘Full’ IF Mixer

If the input data are not centred on 19.2 MHz then it is necessary to use a ‘full’ mixer to mix

the input data to baseband using a complex local oscillator signal. Such a mixer is

implemented by the dfe_library/DDC Blocks/DDC Mixer block.

This block uses a single DSP48 to implement the mixer. Like the quarter-rate mixer, the

output operates at the clock rate; a data ready signal is generated to identify when the output

data are valid. The mixer is designed to accept LO data from the Local Oscillator block (see

Section 3.2.3). This interface interleaves sine and cosine magnitude data on a common data

1 / 76.8 MHz

CE (×4)

Clk

1 / 307.2 MHz

Sync event

Sync waiting flag

Re-timed sync event

Figure 15 Re-timing of single-cycle synchronisation events.


bus and uses a flag to signal when these data should be treated as negative values. The mixer

block implements unbiased rounding at the output of the DSP48 to minimise the introduction

of DC offset.

Note that the mixer is configured to mix down by the LO frequency. This is implemented by

negating the sign of the imaginary (ie, sine) part of the LO data.

3.2.3 Direct Digital Synthesiser

The full IF mixer requires an external source to supply the local oscillator data. A suitable

source is the dfe_library/Shared DDC/DUC Blocks/Local Oscillator block. The operation of this

block is described in Section 2.2.1.

3.3 Six-Channel DDC Subsystem

The six-channel DDC subsystem is implemented in the dfe_library/DDC Blocks/TD-SCDMA

DDC (6 Channels) block. The contents of this block are reproduced in Figure 16. Parallel I/Q

input data are decimated by a factor of four by the first two filter stages. Six, gain-adjusted

baseband channels are extracted by the Intermediate DDC Mixer block. These channels are

decimated to the output rate and pulse-shaping is applied by six filter chains operating in

parallel.

6IQBus6

5IQBus5

4IQBus4

3IQBus3

2IQBus2

1IQBus1

IntermediateDDC Mixer

I

Q

Rdy

Sync

Gain(1)

Gain(2)

Gain(3)

Gain(4)

Gain(5)

Gain(6)

Freq(1)

Freq(2)

Freq(3)

Freq(4)

Freq(5)

Freq(6)

DDS Sync

IQ(1)

IQ(2)

IQ(3)

IQ(4)

IQ(5)

IQ(6)

Rdy

Is Q

Sync

Intermediate DDC Mixer

Sy nc

Generate Sync

DDCPS Fil ter

IQ

Rdy

Is Q

Sync

IQ

Rdy

Is Q

DDC PS Filter 6

DDCPS Fil ter

IQ

Rdy

Is Q

Sync

IQ

Rdy

Is Q

DDC PS Filter 5

DDCPS Fil ter

IQ

Rdy

Is Q

Sync

IQ

Rdy

Is Q

DDC PS Filter 4

DDCPS Fil ter

IQ

Rdy

Is Q

Sync

IQ

Rdy

Is Q

DDC PS Filter 3

DDCPS Fil ter

IQ

Rdy

Is Q

Sync

IQ

Rdy

Is Q

DDC PS Filter 2

DDCPS Fil ter

IQ

Rdy

Is Q

Sync

IQ

Rdy

Is Q

DDC PS Filter 1

DDCFilter 3

IQRdyIs QSyncDelay

IQ

Rdy

Is Q

Sync

DDC Filter 3 6

DDCFilter 3

IQRdyIs QSyncDelay

IQ

Rdy

Is Q

Sync

DDC Filter 3 5

DDCFilter 3

IQRdyIs QSyncDelay

IQ

Rdy

Is Q

Sync

DDC Filter 3 4

DDCFilter 3

IQRdyIs QSyncDelay

IQ

Rdy

Is Q

Sync

DDC Filter 3 3

DDCFilter 3

IQRdyIs QSyncDelay

IQ

Rdy

Is Q

Sync

DDC Filter 3 2

DDCFilter 3

IQRdyIs QSyncDelay

IQ

Rdy

Is Q

Sync

DDC Filter 3 1

DDCFilter 2

I

Q

Rdy

Sync

I

Q

Rdy

Sync

DDC Filter 2

DDCFilter 1

I

Q

Rdy

Sync

I

Q

Rdy

Sync

DDC Fil ter 1

sysgenAssert

sysgenAssert

sysgenAssert

22DDS Sync

21Delay 6

20Delay 5

19Delay 4

18Delay 3

17Delay 2

16Delay 1

15Gain 6

14Gain 5

13Gain 4

12Gain 3

11Gain 2

10Gain 1

9Freq 6

8Freq 5

7Freq 4

6Freq 3

5Freq 2

4Freq 1

3Rdy In

2Q In

1I In IQ

Rdy

Is Q

IQ

Rdy

Is Q

IQ

Rdy

Is Q

IQ

Rdy

Is Q

IQ

Rdy

Is Q

IQ

Rdy

Is Q

Figure 16 The six-channel DDC subsystem.


The Generate Sync subsystem produces a single-cycle event every 240 clock cycles. These

events, which are aligned to a chip-rate clock enable generated by System Generator, are used

to synchronise the operation of the decimation filters. Thus, DDC filter chains implemented

across multiple System Generator designs can be synchronised simply by synchronising the

clock enable logic generated by System Generator.

The output of the TD-SCDMA DDC (6 Channels) block comprises six interleaved I/Q data

streams. These interfaces (like all the interfaces to this block) operate at the system clock

rate, ie, 307.2 MHz. Valid I and Q output data are flagged using a ready signal, Rdy, and a

framing strobe, Is Q. For convenience, these signals, together with the I/Q data on IQ are

combined into six Simulink ‘buses’, one for each output channel. This logical grouping of

signals greatly simplifies the top level implementation of DFE designs.

See Section 5.3.4 for further information on the interface of this block.

3.3.1 First Decimation Filter (Half-Band)

3.3.1.1 Design

The first filter must accept new data at a rate of 76.8 MSps. With a system clock rate of

307.2 MHz there are four clock cycles per complex input sample and, with a decimation rate

of two, eight clock cycles per complex output sample.

With the exception of the centre coefficient, every other coefficient in a half-band filter is

equal to zero. Thus, if we dedicate separate DSP48s for the I and Q branches and we assume

that we can perform a multiply/accumulate operation every clock cycle we can theoretically

implement a filter with up to 11 coefficients (ie, seven non-zero coefficients). In order to

implement a filter with more coefficients we would either have to dedicate additional DSP48

resources to the filter or exploit coefficient symmetry to allow two taps to be processed every

clock cycle. Both approaches are relatively expensive, the first in terms of DSP48s and the

second in terms of the logic that would be required to combine data before the multiplier.

(Note that exploiting coefficient symmetry has a further penalty in that it would effectively

reduce the signal path width to 17 bits.)

The DDC is capable of extracting six TD-SCDMA channels in a 9.6 MHz band (ie,

positioned on six adjacent channels). Therefore, the first decimation filter must have a pass

band 4.8 MHz wide. In a half-band filter the width of the stop band is inherently linked to


the width of the pass band. Therefore the stop band must start at 38.4 – 4.8 = 33.6 MHz. So

that performance is not limited by the decimation filters we choose a stop band attenuation

design goal of 100 dB. Figure 17 shows the theoretical floating- and fixed-point frequency

response of the first decimation filter. It can be seen that pass band ripple is very much less

than ±0.01 dB and that stop band attenuation is close to the 100 dB design goal.

Note that this filter is ‘right on the limit’. Increasing its bandwidth is only possible by

increasing its length (and thereby increasing its ‘cost’ dramatically) or by relaxing the stop

band attenuation requirement.


The first DDC decimation filter is implemented by the dfe_library_low_lvl_ddc/DDC Filter 1

block. This filter is implemented using a MAC architecture, with the I and Q channels

processed in parallel, using a separate DSP48 dedicated to each channel. The construction of

this filter follows the same approach as that used for the RRC filter in the DUC and as

described in Section 2.1.1.6.

The main difference to the RRC filter implementation is that the logic used to generate the

address for the sample data is designed to only read data corresponding to non-zero

0 5 10 15 20 25 30 35-120

-100

-80

-60

-40

-20

0

Frequency (MHz)

Gai

n (d

B)


0 5 10 15 20 25 30 35-0.01

0

0.01

Frequency (MHz)

Gai

n (d

B)

Figure 17 First decimation filter (half-band) characteristics.


coefficients to be read. This is necessary because there are insufficient clock cycles available

to be able to also read the data corresponding to the zero coefficient taps.

3.3.2 Second Decimation Filter (Half-Band)

3.3.2.1 Design

The second filter receives data at 38.4 MSps and, like the first filter, is a half-band filter. 16

clock cycles are available to compute each complex output sample.

Dedicating separate DSP48s for the I and Q branches and again assuming that we can

perform a multiply/accumulate operation every clock cycle we can theoretically implement a

filter with up to 27 coefficients (ie, 15 non-zero coefficients).

The second decimation filter has the same pass band requirements as the first filter.

Therefore the stop band must start at 19.2 – 4.8 = 14.4 MHz. As with the first filter we

choose a stop band attenuation design goal of 100 dB. Figure 18 shows the theoretical

floating- and fixed-point frequency response of the second decimation filter. Pass band ripple

is very much less than ±0.01 dB and attenuation exceeds the 100 dB design goal across much

of the stop band (attenuation is approximately -99.78 dB at 14.4 MHz for the fixed-point

model).

0 2 4 6 8 10 12 14 16 18-120

-100

-80

-60

-40

-20

0

Frequency (MHz)

Gai

n (d

B)


0 2 4 6 8 10 12 14 16 18-0.01

0

0.01

Frequency (MHz)

Gai

n (d

B)

Figure 18 Second decimation filter (half-band) characteristics.



The second DDC decimation filter is implemented by the dfe_library_low_lvl_ddc/DDC Filter 2

block. This filter is implemented in a similar fashion to the first, see Section 3.3.1.2.

3.3.3 Gain Adjustment and Intermediate Mixer

The output of the second decimation filter is a 19.2 MSps complex data stream, with I and Q

data on separate buses. The data at this point represent a composite, multi-carrier waveform,

with up to six TD-SCDMA signals within a 9.6 MHz bandwidth. The next stage in the signal

path is responsible for replicating and multiplexing the sample data to produce six,

interleaved I/Q data streams and then to adjust the amplitude and apply a programmable

frequency translation to each channel. Thus the output of this stage consists of up to six,

gain-adjusted TD-SCDMA waveforms centred on baseband, ready for final decimation and

pulse-shaping. The gain adjustment function and the intermediate mixer are implemented in

the dfe_library_low_lvl_ddc/Intermediate DDC Mixer block.

3.3.3.1 Gain Adjustment and Intermediate Mixer Implementation

In order to make efficient use of the FPGA resources it is desirable to share a DSP48 between

as many channels as possible whilst keeping the logic required to support any such resource

sharing to sensible levels. For simplicity the gain adjustment and frequency translation

functions are kept separate, ie, separate resources are dedicated to each.

Although the data first pass through the gain adjustment stage it is helpful to begin by

considering the operation of the intermediate mixer. A full, complex multiply requires four

multiplications and two additions. In order to share a DSP48 between N channels, we ideally

need to compute all N I output data and then all N Q output data (to simplify the task of

demultiplexing the N interleaved I/Q data streams at the output). With 16 clock cycles

available, each DSP48 can theoretically support up to four channels. This means that we

have to use two DSP48s if we want to process six channels. Finally, to simplify the control

logic we choose to share the processing load equally, ie, so each DSP48 processes three

channels.

A conceptual timing diagram of the six-channel gain adjustment and intermediate mixer is

shown in Figure 19. (Note that this is for illustrative purposes only and does not accurately

portray the latency through the stages of the implemented intermediate mixer block.) The


process begins by interleaving the I/Q input data and the gain control data (G1 to G3). Thus,

the output of the first DSP48 is a repeating, interleaved I/Q data stream weighted by the gain

control data. The control logic for the mixer DDS is designed to output sine (Sx) and cosine

(Cx) data in an appropriate sequence aligned with the weighted I/Q data. By accumulating

over consecutive clock periods, the I and Q output data for all three channels are generated.

A tapped delay-line on the output of the final DSP48 is used to demultiplex the three

channels and present the output data simultaneously. This is repeated for channels four to

six.

3.3.3.2 DDS for the Intermediate Mixer

The implementation of the DDS for the DDC intermediate mixer is similar in concept to the

DDS used in the DUC intermediate mixer (see Section 2.1.3.4), with a single dual-port block

RAM used to store four complete 96-sample sinusoids.

The intermediate DDC mixer DDS requires six modulo-96 phase accumulators. These are

implemented as two, three-channel phase accumulators, with one dedicated to each half of

mixer. Each consists of a single seven-bit adder, logic to implement the modulo-96 function

and an SRL16-based delay element to store the phase data for each channel.

3.3.3.3 Optional Fixed Gain of Two

The root-mean-square (RMS) power of a full-scale input is 3 dB below that of a full-scale

complex signal (because the imaginary part of the signal is missing). Moreover, after mixing

to baseband, a further 3 dB is ‘lost’ because only half of the input power ends up at baseband

(the other half ends up centred of 2×fIF). Thus, once the image introduced by the mixer has

I Q I Q I Q I Q I Q I Q I Q I Q

G1 G2 G3

Q.G1 I.G2 Q.G2 I.G3 Q.G3I.G1

C1 S2 C2 S3 C3S1 -S1 C2 -S2 C3 -S3C1

G1 G2 G3

Q.G1 I.G2 Q.G2 I.G3 Q.G3I.G1

G1(I.S1+Q.C1)

I.G2.S2G2(I.S2+Q.C2)

I.G3.S3G3(I.S3+Q.C3)

I.G1.S1G1(I.C1-Q.S1)

I.G2.C2G2(I.C2-Q.S2)

I.G3.C3G3(I.C3-Q.S3)

I.G1.C1

Accumulate Ifor Channel 1



Accumulate Qfor Channel 1



Interleaved I/Q Data

Interleaved Gain Data

Output of ‘Gain’ DSP48

Output of Mixer DDS

Output of ‘Mixer’ DSP48

1 / 19.2 MSps

Figure 19 Conceptual timing diagram showing the operation of the six-channel gain adjustment and intermediate mixer.


been removed by filtering, the maximum signal power is -6 dBFSCW. In other words, the

most-significant data bit effectively becomes redundant and implies an unnecessary 6 dB

reduction in dynamic range. To compensate for this, the gain adjustment and intermediate

mixer block includes an optional fixed gain of two at the output of the gain adjustment

DSP48 (as shown in Figure 14). This maximises the dynamic range available in the

remainder of the signal path. When constructing designs using the six-channel DDC building

block, this optional fixed gain stage is automatically included when the fixed signal path gain

is configured to be greater than or equal to two.

3.3.4 Third Decimation Filter

3.3.4.1 Design

Following the intermediate mixer, the wanted TD-SCDMA signal should be centred on 0 Hz,

ie, the signal path no longer has to support multiple channels. Data are output from the

intermediate mixer at 19.2 MSps; these data need to be pulse-shaped and decimated by a

further factor of 15. This process is handled by two further filtering stages. The first of these

two filters decimates the sample data by a factor of five.

The sample rate at the output of the third filter stage is 3.84 MSps. The wanted signal will

have a bandwidth of approximately 1.6 MHz. Therefore, the stop band of this filter must

start at approximately 3.84 – 0.8 = 30.4 MHz. In the interests of maximising stop band

attenuation we do not set an absolute pass band requirement; we will rely on the final filter

stage to compensate for any pass band droop. To minimise resource utilisation, we choose to

opt for a single-DSP48 MAC filter architecture, ie, a single DSP48 to compute both I and Q

output data. New I and Q sample data arrive every eight clock cycles (ie, 16 clock cycles per

I/Q pair) and two output samples must be generated every 80 clock cycles. If we reserve one

clock cycle per input sample to ‘store’ data we are left with up to 37 clock cycles with which

to calculate each output sample. Thus the third filter stage can have up to 37 coefficients.

Given this upper limit we note that we need to keep the number of taps to a minimum in

order to minimise the delay through the DDC. We find that we can achieve 100 dB stop band

attenuation with a 31-tap filter. The floating- and fixed-point frequency responses of this

filter are shown in Figure 20. Note that this filter has an insertion loss of approximately

1.5 dB at 0.5 MHz.



The third DDC decimation filter is implemented by the dfe_library_low_lvl_ddc/DDC Filter 3

block. As with the other DDC filters, this filter is implemented using a MAC architecture.

Unlike the first two filter stages, however, I and Q data are input and output as interleaved

samples. This enables a single DSP48 to be shared between both channels efficiently.

As with the other filters a single block RAM is used to store the sample data, filter

coefficients and control data. The read-only contents of the block RAM are defined in the

mask initialisation code for the filter.

Compared to the half-band filters, generation of the sample data address is slightly more

straightforward because more ‘spare’ clock cycles are available so special treatment of the

centre tap data is not necessary.

An additional function of this filter is the programmable signal path delay. This is

implemented by using a delayed version of the ‘write pointer’ to initialise the ‘read pointer’.

The delay is implemented using an addressable shift register and so is relatively efficient in

terms of resources used.

0 1 2 3 4 5 6 7 8 9-120

-100

-80

-60

-40

-20

0

Frequency (MHz)

Gai

n (d

B)


0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

-1.5

-1

-0.5

0

Frequency (MHz)

Gai

n (d

B)

Figure 20 Third decimation filter characteristics.


3.3.5 Root-Raised Cosine Filter

3.3.5.1 Design

The final filter stage in the DDC applies pulse-shaping to the output data. It also decimates

the sample data by a factor of three, bringing the overall decimation rate to 60.

The length of this final filter must be kept as short as possible in order to minimise the delay

through the DDC. This poses an interesting challenge. There is a three-way trade off

between the filter length, the implementation error of the root-raised cosine characteristic and

the attenuation of adjacent channel signals; an acceptable compromise is required. In

general, reducing the length of the filter will deteriorate the rejection of adjacent channel

signals. This can be addressed to a certain degree by ‘weighting’ the filter’s impulse

response. However, too much windowing and the error between the resulting filter

characteristic and the ideal RRC response will increase. Note that in addition to

implementing the root-raised cosine filter characteristic, this filter must also compensate for

the pass band droop of the preceding filter stage (see Figure 20).

An acceptable filter design was achieved using a 95-tap filter, the characteristics of which are

shown in Figure 21. Here, the red line represents the ideal RRC characteristic adjusted to

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8-120

-100

-80

-60

-40

-20

0

Frequency (MHz)

Gai

n (d

B)


0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

0

0.5

1

1.5

Frequency (MHz)

Gai

n (d

B)

Figure 21 Root-raised cosine filter characteristic.


compensate for the droop of the third decimation filter. The effect of this compensation

characteristic can be seen clearly in the close-up of the pass band in Figure 21 (bottom).

The frequency response of the root-raised cosine filter is relatively meaningless when viewed

in isolation. It is necessary to consider the composite response of this filter with the

preceding decimate-by-five filter stage. This is shown in Figure 22. The red line represents

the response of an ‘ideal’ pulse-shaping filter. The frequency response above 1.92 MHz has

been ‘folded back’ to represent the decimation within the decimate-by-five filter. A close up

of the pass band shows that ripple is less than ±0.02 dB below 0.4992 MHz and less than

±0.01 dB below 0.474 MHz (ie, 95% of the nominal pass band).

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8-120

-100

-80

-60

-40

-20

0

Frequency (MHz)

Gai

n (d

B)


0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8-0.02

0

0.02

Frequency (MHz)

Gai

n (d

B)

Figure 22 Combined response of the third decimation filter and the root-raised cosine filter.


The root-raised cosine filter is implemented by the dfe_library_low_lvl_ddc/DDC PS Filter block.

This filter is implemented in a similar fashion to the third decimation filter, with a single

block RAM and DSP48 shared between both channels.

Compared to the third filter, the data addressing logic for this filter is simplified because the

programmable signal path delay feature is not required.


This filter incorporates a configurable fixed gain stage and output data precision. These

features, which are controlled via the block mask, are implemented by configuration of the

MAC subsystem output. To prevent overflow when a fixed gain of greater than one is

enabled, clipping logic implemented using standard System Generator blocks is included on

the output.

Note that this filter includes output registers on the data and I/Q framing signals. This means

that I/Q data remain valid between events on the data ready output and simplifies the design

of subsequent signal path stages.

3.3.6 Composite Filter Response

Table 7 summarises the DDC filter stages. The theoretical delay through the DDC filter

chain is equal to 6/76.8 + 14/38.4 + 16/19.2 + 48/3.84 = 13.78 µs. However, this does not

include the delay through the mixers, input/output stages or any other implementation delays.

Filter Stage Input (MSps)

Length (Taps)

Pass Band (MHz)

Stop Band (MHz)

Ripple (dB Pk-Pk)

Half-band 1 76.8 11 4.80 33.6 <±0.001

Half-band 2 38.4 27 4.80 14.4 <±0.001

Decimate-by-five 19.2 31 - 3.04 -

Windowed RRC 3.84 95 0.50 - <±0.02* * When combined with the decimate-by-five filter stage.

So far we have only considered each of the filter stages in the DDC signal path in isolation.

Figure 23 shows the composite frequency response of all four DDC filters. (Note that for the

purposes of Figure 23 it is assumed that no frequency translation occurs between the second

and third filter stages.) The red line represents the response of an ‘ideal’ pulse-shaping filter.

A close up of the pass band shows that ripple is less than ±0.01 dB over the central 95% and

less than ±0.02 dB between ±0.4992 MHz.

Table 7 DDC filter summary.


Note that Figure 23 shows the theoretical floating- and fixed-point frequency response of the

DDC filters only. In practice, if used with the ‘full’ mixer block the noise spectrum of the

phase-dithered DDS will introduce a wideband noise floor relative to the power of the IF

input.

3.4 Simulated ACS, Blocking and EVM Performance

Having computed the theoretical DDC frequency response we are now in a position to

consider adjacent channel selectivity (ACS), blocking and EVM performance. The TD-

SCDMA ACS and blocking requirements (Sections 7.4.1.2 and 7.5.0.2 of 3GPP specification

TS 25.105 [1]) require that adjacent-channel signals must be attenuated by more than 49 dB

in the first adjacent channel and by more than 64 dB in subsequent channels3. There is no

specific EVM requirement for TD-SCDMA receiving equipment although it provides a

useful metric to give a measure of the quality of the implemented pulse-shaping filter.

3 More stringent blocking requirements are given for out-of-band CW signals and for co-location with GSM systems. However, these requirements can only be met by filtering in the analogue domain and are not considered further in this discussion.

-8 -6 -4 -2 0 2 4 6 8-120

-100

-80

-60

-40

-20

0

Frequency (MHz)

Gai

n (d

B)


-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1-0.02

0

0.02

Frequency (MHz)

Gai

n (d

B)

Figure 23 Composite DDC filter response.


We calculate ACS/blocking performance by calculating the ratio of power in the wanted

signal to that in an adjacent channel signal at the output of the DDC filter chain. When

modelling the DDC filter chain for the purposes of simulating the ACS/blocking performance

it is vital to also model the performance of the dithered phase accumulator used as part of the

IF mixer. The effect of the phase dithering is to generate wideband noise relative to the total

power of IF input signal. Thus, the total interference power is not only the sum of the power

‘leaking’ through the decimation filters but is the combination of this and the wideband noise

power mixed in-band by the IF mixer. An example is shown in Figure 24. Here a TD-

SCDMA signal has been passed through a model of the IF DDC mixer and shifted to

represent, in turn, the wanted signal and interfering signals in the first and second adjacent

channels. This is shown in Figure 24 (top). The noise power introduced by the mixer is

clearly visible.

In Figure 24 (bottom), the input waveforms have all been filtered using a model of the DDC

filter chain. Integrating the total output power for each input waveform we find that the

signal in the first adjacent channel is attenuated with respect to the wanted signal by

approximately 77 dB and that the signal in the second adjacent channel is attenuated by

approximately 83 dB. The rejection offered to the signal in the second adjacent channel is

-2.4 -1.6 -0.8 0 0.8 1.6 2.4 3.2 4 4.8 5.6 6.4 7.2

-100

-50

0

Frequency (MHz)

Pow

er (d

B)

Wanted Signal + NCO Noise1st Adj. Ch. Signal + NCO Noise2nd Adj. Ch. Signal + NCO NoiseComposite DDC Filter Response

-2.4 -1.6 -0.8 0 0.8 1.6 2.4 3.2 4 4.8 5.6 6.4 7.2

-100

-50

0

Frequency (MHz)

Pow

er (d

B)

Wanted Signal (Filtered)1st Adj. Ch. Signal (Filtered)2nd Adj. Ch. Signal (Filtered)Composite DDC Filter Response

Figure 24 Simulated ACS/blocking performance.


limited by the wideband noise power. Therefore it is reasonable to conclude that signals in

subsequent adjacent channels will not be attenuated any further. We conclude that the DDC

filter chain exceeds the minimum ACS requirement by almost 30 dB and the blocking

requirement by almost 20 dB.

Having considered ACS/blocking performance we move to consider the EVM performance.

The signal trajectory generated by simulation of the DDC filter chain is shown in Figure 25.

The test signal consists of a repeating 256-symbol TD-SCDMA waveform conditioned using

an ‘ideal’ transmit filter. Calculating the RMS EVM (at the optimal sampling points)

produces an EVM of approximately 0.1%. In other words, the pulse-shaping characteristic

applied by the DDC filter closely models the ideal filter response.

3.5 Output Formatting Blocks

The output of the DDC can be output in a number of formats. These output formats and the

blocks used to implement them are discussed in Section 5.4.

-2 -1.5 -1 -0.5 0 0.5 1 1.5 2-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

EVM = 0.1135%

Figure 25 Simulated signal trajectory and EVM measurement using a repeating, 256-symbol data sequence.


4 DFE Performance

This section summarises the key performance measurements of the DUC and DDC.

4.1 DUC Performance

The key DUC performance characteristics were measured and verified using an example

DUC design built for hardware co-simulation. The results of these tests are presented in the

following sections.

4.1.1 Transmit Mask

The transmit spectrum mask requirements defined by the 3GPP standards are given in

Section 2.1.1.1. Figure 26 shows the power spectrum mask measured during the tests. The

mask limits are denoted by the red line, and the measured mask is shown by the blue line.

The spectrum mask measurements are performed by generated random bi-polar input data for

eight users as per the 3GPP specifications. The power spectrum is derived by using an FFT

to obtain the power spectrum of the DUC output, and then applying a Gaussian window to

-2.4 -2.2 -2 -1.8 -1.6 -1.4 -1.2 -1 -0.8-120

-110

-100

-90

-80

-70

-60

-50

-40

Frequency offset (MHz)

Pow

er in

30k

Hz

rela

tive

to T

x po

wer

(dB

c) Transmit Emission Mask (Single carrier, IF = 19.2 MHz, Lower Side)

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4-120

-110

-100

-90

-80

-70

-60

-50

-40

Frequency offset (MHz)

Pow

er in

30k

Hz

rela

tive

to T

x po

wer

(dB

c) Transmit Emission Mask (Single carrier, IF = 19.2 MHz, Upper Side)

Figure 26 DUC transmit spectrum mask for single output carrier.


emulate the effect of a spectrum analyser IF filter, also required by the specifications. The

window has its 3 dB points at +/- 15 kHz relative to the centre of the window.

As can be seen in Figure 26, the DUC meets the transmit mask requirements by a significant

margin. At a frequency offset of 815 kHz, the power measured is -85 dB relative to the

transmit power. This is 31 dB below the mask limit of -54 dB. The design margin was 20 dB

below the mask limit, to allow for bandwidth expansion due to distortion in the analogue

components.

4.1.2 Occupied Bandwidth

The occupied bandwidth test requires that 99% of the transmitted power lies within a

bandwidth of less than 1.6 MHz centred on the carrier frequency. For ease of testing we

prove this by showing that more than 99% of the transmitted power lies within a l.6 MHz

band. When transmitting a single carrier, the ratio of in-band power, ie, the power in 1.6 MHz

band centred on the carrier, to the total DUC output power exceed 99.999%. This exceeds

the design target of 99%.

4.1.3 Adjacent Channel Leakage Ratio

The ACLR is measured by analysing the power spectrum from the DUC and applying an

ideal TD-SCDMA pulse shaping filter to simulate the response of a receiver. Firstly, the

filter is centred on the transmit carrier, and, secondly, it is centred on the adjacent carrier.

The power in the main and adjacent carriers is computed by summing the power over a

bandwidth of 1.6 MHz on each carrier, and the ACLR is the difference between these powers.

A plot illustrating the ACLR measurement can be seen in Figure 27.

The blue trace shows the receiver spectrum with a pulse shaping filter centred on the transmit

carrier at 19.2 MHz and the red trace shows the receiver spectrum with the pulse shaping

filter centred on the adjacent carrier above 19.2 MHz. The computed ACLR is 82 dB which

exceeds the design requirement of 80 dB.

Note that the ACLR measurements were performed using the quarter-rate mixer in the DUC.

This does not produce any wideband noise, as a quarter-rate sinusoid can be represented

perfectly with no phase truncation. When using the full mixer tuned to a frequency that

produces jitter in the DDS, wideband noise will be present at the output of the full mixer.


This will be compounded when more than one carrier is enabled, and consequently will

degrade ACLR performance. With six active carriers the ACLR will be -77 dB.

4.1.4 Error Vector Magnitude

The EVM measured using hardware co-simulation for the DUC is 1.6% RMS, which exceeds

the design goal of 2.5% RMS. This allows a generous margin for EVM degradation in the

analogue components, as Section 6.8.2.1 of TS 25.105 specifies that the EVM must be less

than 12.5%.

4.1.5 DUC Delay

The measured delay through the DUC is 14.78 µs. This is slightly higher than the theoretical

delay of 14.27 µs, which is the minimum possible delay with the designed filters, due to

implementation delays. However, it meets the maximum design target of 15 µs.

Note that using the DUC with the serial input block increases the delay to 15.17 µs. It is not

possible to reduce this without compromising the performance of the DUC.

17.6 18.4 19.2 20 20.8 21.6 22.4-140

-120

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-60

-40

-20

0

20

Frequency (MHz)

Pow

er (d

Bc)

Adjacent Carrier Leakage Plot (Single carrier, IF = 19.2 MHz, Upper Side)

Reference Carrier SpectrumAdjacent Carrier Spectrum

Figure 27 DUC ACLR measurement for a single carrier.


4.2 DDC Performance

The key DDC performance characteristics were measured and verified using an example

DDC design built for hardware co-simulation. The results of these tests are presented in the

following sections.

4.2.1 Adjacent Channel Selectivity and Blocking

The TD-SCDMA standard specifies that adjacent-channel signals must be attenuated by more

than 49 dB in the first adjacent channel and by more than 64 dB in subsequent channels.

Simulation of the DDC design prior to implementation (see Section 3.4) indicated that these

requirements should be exceeded with ease.

Figure 28 shows the effectiveness of the DDC at attenuating adjacent channel signals. Here,

a six-channel DDC design is subjected to a TD-SCDMA test signal (shown in Figure 28

(top)). Two of the DDC channels are tuned to the input signal. The remaining channels are

configured for one- and two-channel offsets. The output spectrum for each channel is shown

in Figure 28 (bottom). By calculating the total power on each output the ACS and blocking

performance can be evaluated. It was found that the input signal is attenuated by

approximately 78 dB in the first adjacent channel and 84 dB in the second adjacent channel.

-4 -3.2 -2.4 -1.6 -0.8 0 0.8 1.6 2.4 3.2 4

-100

-50

0

Frequency (MHz)

Pow

er In

(dB

FSC

W)

TD-SCDMA Input SignalDDC Frequency Response (Ch. 5)

-4 -3.2 -2.4 -1.6 -0.8 0 0.8 1.6 2.4 3.2 4

-100

-50

0Ch. 1

(2nd Adj. Ch.)

Ch. 2(1st Adj. Ch.)

Ch. 3 and 4(Wanted Channel)

Ch. 5(1st Adj. Ch.)

Ch. 6(2nd Adj. Ch.)

Frequency (MHz)

Pow

er O

ut (d

BFS

CW

)

Figure 28 Measured DDC ACS and blocking performance.


These results compare favourably to the simulation results presented in Section 3.4.

It can be seen from Figure 28 (bottom) that ACS in the first adjacent channel is limited by

signal power leaking into Channel 5 from Channel 4 and into Channel 2 from Channel 3.

This manifests itself in the form of an asymmetrical ‘hump’ in the output of Channels 2 and

5. The mechanism by which this leakage occurs is aliasing due to the decimation process.

This can be illustrated by overlaying the combined DDC frequency response for Channel 5,

shown by the grey line in Figure 28, before (top) and after (bottom) decimation. After

decimation, the filtered input signal over the frequency range highlighted in green is folded in

band, adding to the output power of Channel 5, as shown in Figure 28 (bottom).

4.2.2 DDC Delay

The DDC was designed with a signal path delay design goal of no greater than 15 µs. This

requirement primarily imposed constraints on the lengths of the various filter stages.

Characterisation of the final design (with the programmable signal path delay set to zero)

reveals a DDC signal path delay of 14.89 µs. Note that this figure includes the delay through

the input gateway block, full IF mixer, six-channel DDC subsystem and serial output

formatting blocks.

0 5 10 15 20 25 30 35 40 45 50-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

Time (μs)

Am

plitu

de

DDC Input (fIF = 0 Hz)

DDC Output (Real Part)

14.89 μs

Figure 29 DDC delay.


The delay though the DDC is illustrated in Figure 29. Here, a composite input signal

consisting of a number of sinusoids has been input to the DDC on a zero-IF. This test signal

is shown by the blue line in Figure 29. The (real) DDC output data are shown by the red

markers (the red dotted line has been added in the interests of clarity). A delay of 14.89 µs

can be observed.

4.3 Shared DUC and DDC components

4.3.1 Spurious-Free Dynamic Range and Wideband Noise

The performance of the local oscillator used to drive the full IF mixer affects the overall

performance of the DDC. Figure 30 shows the measured output spectrum of the IF DDS

when configured with a fundamental output frequency of 16 MHz. The measured SFDR is

almost 105 dBc and the noise spectral density (measured in a 10 MHz band centred on

16 MHz) is equal to -146 dBc/Hz. These figures comfortably exceed the design goals of a

100 dBc SFDR and a noise spectral density better than -130 dBc/Hz.

-30 -20 -10 0 10 20 30

-140

-120

-100

-80

-60

-40

-20

0

Frequency (MHz)

Pow

er (d

BFS

CW

)

DDS Output (Normalised)Noise SpectrumMeasured SFDR (104.71 dBc)

Figure 30 DDC IF mixer DDS output spectrum when configured with a fundamental output frequency of 16 MHz.


4.4 Performance Summary

3GPP Parameter 3GPP Requirement

Measured Performance Margin

Occupied bandwidth1 99% 99.99998% >0.999%

ACLR 40 dB Single carrier any IF 82 dB Six-carriers 19.2 MHz IF 82 dB Six-carriers other IF 77 dB

42 dB 42 dB 37 dB

EVM 12.5 % 1.6% 10.9%

Spectrum Mask 54 dB at 815 kHz

85 dB 31 dB

ACS 49 dB 78 dB 29 dB

Blocking 64 dB 84 dB 20 dB 1. The occupied bandwidth test is proved by showing that the power in 1.6 MHz exceeds 99% of the total. This

provides an equivalent result, but using a slightly different method to that described in the 3GPP BS conformance specification [4].

Table 8 Summary of TD-SCDMA DFE performance measurements.


5 Interface Information

In the following sections the top level DFE library blocks are listed and the interface to each

block defined. The input and output ports to the blocks are summarised in tabular form under

the headings ‘Input’, ‘Mask Name’, ‘Type’, ‘Period’ and ‘Description’. The ‘Input’ and

‘Description’ columns are self explanatory. The ‘Mask Name’ column gives the name as the

port appears on the block mask (note that this is not necessarily the name given to the port

underneath the block mask). The ‘Type’ column defines the signal data type expected by the

port and the ‘Period’ column defines the expected signal sample period (in clock cycles).

Thus, an input port with the type “Fix_16_15” and period “×4” expects a signed, 16-bit signal

with a sample period of four clock cycles and with the binary point between bits 14 and 15

(ie, with values in the range -1 to (almost) +1).

5.1 DUC Library Blocks

The following blocks can be used to construct DUC designs.

5.1.1 DUC_OUT Block

The DUC_OUT block provides a convenient method of adding a complex output gateway to

DUC designs for driving a DAC. The input of this block is compatible with the TD-SCDMA

DUC (6 Channels) and DUC Mixer blocks.

5.1.1.1 Interface Description

The symbol for the DUC_OUT block is shown in Figure 31. The inputs to this block are

defined in Table 9 and the outputs in Table 10.

DUC IF Output(2×16-bit)

I

Q

I

Q

DUC_OUT

Figure 31 The DUC_OUT block.


Input Mask Name Type Period Description

1 I fix_x_y ×4

2 Q fix_x_y ×4

Quadrature IF input data. Input data should be in the range -1 to (almost) +1, (ie, y = x – 1). This input is compatible with the output of the the TD-SCDMA DUC (6 Channels) block, or the DUC Mixer block.

Output Mask Name Type Period Description

1 I fix_16_15 ×4

2 Q fix_16_15 ×4

Quadrature IF output data. This is the input data rounded to 16-bits and registered. The output is in the range -1 to (almost) +1.

5.1.1.2 Mask Parameters

The DUC_OUT block embeds separate System Generator Gateway Out blocks for I and Q

sample data. The names assigned to these gateways (and hence the names assigned to the

corresponding ports when the design is built) are, by default, derived from the name given to

the instantiated DUC_OUT block. Alternatively, by clearing the ‘Use block name to set

gateway prefix’ checkbox, an expression that evaluates to a string can be entered in the

‘Gateway prefix’ edit box. When naming the output gateways the ‘_I’ and ‘_Q’ suffices are

added to the gateway prefix. For example, if the DUC_OUT block is renamed DAC 1 then, by

default, the final design will have a corresponding output ports DAC_1_I and DAC_1_Q.

Table 9 DUC_OUT inputs.

Table 10 DUC_OUT outputs.

Figure 32 Mask for the DUC_OUT block.


5.1.2 DUC Mixer Block

The DUC Mixer block implements a ‘full’ complex mixer to translate the quadrature IF data

from the output of the DUC, which is centred around a zero-IF, to programmable IF. This

block is designed to be driven using the Local Oscillator block. The input of this block is

compatible with the TD-SCDMA DUC (6 Channels) block. The output is compatible with the

DUC_OUT block.


The symbol for the DUC Mixer block is shown in Figure 33. The inputs to this block are



1 I fix_x_y ×4

2 Q fix_x_y ×4

Quadrature input data. This input is compatible with the output of the the TD-SCDMA DUC (6 Channels) block (ie, signal type of fix_18_17).

LO Simulink Bus

• Mag fix_18_17 ×1 3

• Sign bool ×1

Local oscillator data (interleaved). This input is compatible with the output of the Local Oscillator block.


1 I fix_16_15 ×4

2 Q fix_16_15 ×4

Quadrature IF output data. Compatible with the input of the DUC_OUT block.

DUC Mixer

I

Q

LO

I

Q

DUC Mixer

Figure 33 The DUC Mixer block.

Table 11 DUC Mixer inputs.

Table 12 DUC Mixer outputs.


5.1.3 TD-SCDMA DUC (6 Channels) Block

The TD-SCDMA DUC (6 Channels) block is the main building block for the DUC designs, it

incorporates all the necessary logic to generate an IF waveform composed of six TD-

SCDMA carriers from six quadrature baseband data inputs. The output IF rate is 76.8 MSps

and the carriers must be centred on frequencies in the range ±4 MHz (with a 200 kHz raster).

In addition to pulse-shaping, filtering and up-conversion, this block also allows burst gain

profiling to be applied to each channel. An optional quarter-rate mixer can be enabled to shift

the carriers en-masse from DC to an IF centre frequency of 19.2 MHz.

In designs that do not require the use of all six channels, unused inputs should be connected

to the output of an Unused BB Input block. The logic associated with the unused channels will

be removed by the build tools.


The symbol for the TD-SCDMA DUC (6 Channels) block is shown in Figure 34. The inputs to

this block are defined in Table 13 and the outputs in Table 14.

TD-SCDMA DUC(6 Channels)

IQBus(1)

IQBus(2)

IQBus(3)

IQBus(4)

IQBus(5)

IQBus(6)

TxEn

Sync

Freq(1)

Freq(2)

Freq(3)

Freq(4)

Freq(5)

Freq(6)

Gain_Addr

Gain_Data

Gain_WE

I

Q

TD-SCDMA DUC (6 Channels)

Figure 34 The TD-SCDMA DUC (6 Channels) block.


Input Mask Name Type Period Description IQBus(n) (n = 1…6)

Simulink Bus

• IQ fix_x_y ×1

• Rdy bool ×1

• Is Q bool ×1

• Enable bool ×1

1–6

Quadrature input data (interleaved). I/Q input data are input at the chip rate. The Rdy and Is Q signals control the flow of data, the timing of which is shown in Figure 35. Note that the I data precede the Q data. When asserted the Is Q signals denotes that the data bus is set to the Q value. The Enable signal is used to indicate that the input is in use and should be tied high. Setting this input low will deactivate the input. Input 1 must always be enabled, but other inputs are optional. The input data for all six channels are registered within the TD-SCDMA DUC (6 Channels) subsystem when Rdy on input 1 is asserted. IQ and Is Q are don’t care inputs when Rdy is not asserted. Rdy should be asserted for a single clock cycle every 120 clock cycles, otherwise the output data will not be valid. All DUC inputs must be synchronous to one another. As Rdy is only used on input 1, other Rdy inputs can be connected to the same signal or tied low. The Is Q input signal must be identical for all channels. The width of the input data, x, can be up to 18-bits. Input data are in the range -1 to (almost) +1 (ie, y = x – 1). The magnitude of the input data should not exceed unity, ie, lie outside the unit circle, otherwise the output of the intermediate mixer in the DUC may be clipped. The DUC inputs can be connected to the DUC_IN input blocks, which enable input data in several different formats. See section X for further details.

7 TxEn bool ×1

Transmit enable signal for controlling the burst gain profiling (active high). This signal should be asserted eight chips before the start of a TD-SCDMA burst, and de-asserted at the end of the burst. TxEn should be set to the same value for both I and Q sample pairs. See Section 5.1.3.3 for further information. TxEn can be tied high when gain profiling


Input Mask Name Type Period Description is not used. TxEn is sampled when Rdy is asserted.

8 Sync bool Any Resets the phase accumulators in the intermediate and quarter-rate mixer (if enabled). Active high.

9–14 Freq(n) (n = 1…6)

fix_6_0 Any

Intermediate mixer DDS frequency for channel n. The intermediate mixer can be tuned over the range -4.0 to +4.0 MHz in steps of 200 kHz. If the signal of interest is centred on fIF at the input to the mixer then

Freq(*) = fIF / 0.2 MHz

Note that the intermediate mixer mixes down by the DDS output frequency.

15 Gain_Addr ufix_11_0 or ufix_8_0 Any

Gain profile RAM address. Either an 11-bit or 8-bit address depending on block mask parameters. See Section 5.1.3.3 for further details on the address map of the gain profile RAM.

16 Gain_Data ufix_16_16 Any Gain profile RAM data bus. Unsigned value representing a linear gain between zero and (almost) one.

17 Gain_WE bool Any

Gain profile RAM write enable signal (active high). When asserted, the current value on the Gain_Data bus will be written the Gain_Addr address in block RAM during the following clock cycle.


1 I fix_18_17 ×4

IF parallel data output (I). Data are in the range -1 to (almost) +1. Output spectrum is centred around a zero-IF unless the ‘Enable quarter-rate mixer’ option is selected in the block mask, in which case the output spectrum is centred around an IF of 19.2 MHz.

2 Q fix_18_17 ×4 IF parallel data output (Q). See notes on I output.

Table 13 TD-SCDMA DUC (6 Channels) inputs.

Table 14 TD-SCDMA DUC (6 Channels) outputs.


I0 Q0IQ

Rdy

Is Q

1 / 1.28 MSps

IQB

us(n

)

Clk

I1

120 ClockCycles

120 ClockCycles


The TD-SCDMA DUC (6 Channels) block mask is shown in Figure 36.

The mixer gain parameter allows the gain applied by the intermediate mixer in the DUC to be

specified. The gain value will be fixed at build time. By default, the gain is set to 1/6

Figure 35 Timing of the IQ, Rdy and Is Q inputs of the TD-SCDMA DUC (6 Channels) block.

Figure 36 Mask for the TD-SCDMA DUC (6 Channels) block.


(-15.5 dB) to allow a full-scale input on all six input channels without clipping occurring in

the intermediate DUC mixer. If fewer channels are required, or the scaling is applied by the

user at the inputs, then the gain value can be increased. In these scenarios, increasing the

gain will increase the available dynamic range of the DUC. For example, if only a single

channel is required, or a scaling factor of 1/6 is applied by the user to all six baseband data at

the input to the DUC, then the gain value can be set to 1. For further information, see section

2.1.3.2.

The gain of the root-raised filter in the DUC is fixed at 1/2, to compensate for overshoot in

the response of the DUC filters (see Section 2.1.1.6). Consequently, the overall gain on each

DUC channel is the mixer gain multiplied by 1/2, ie, the default DUC gain is 1/12 (-21.5 dB).

The ‘Enable quarter-rate mixer’ option in the block mask will enable the quarter-rate mixer

implemented in the DUC. This will translate the centre frequency of the output spectrum

from a zero IF to 19.2 MHz. If this option is enabled, the DUC Full Mixer block is not

necessary and should not be used on the output of the DUC.

The ‘Use common gain profile for all channels’ block mask option will apply the same gain

profile data to all six input channels, rather than allowing separate gain profiles to be applied

to each channel. Enabling this option will reduce the block RAM resources required by the

DUC, since the block RAM only needs to store the data for one gain profile waveform rather

than six gain profile waveforms. This reduces the width of the Gain_Addr input from 11 bits

to 8 bits.

5.1.3.3 Gain Profile Interface

Each gain profile waveform consists of 120 samples for the ramp-up, and 120 samples for the

ramp-down, which are stored in block RAM within the six-channel DUC subsystem. The

gain profile is applied at a rate of 15·Fc, resulting in a ramp period of 120 / 15 = 8 chips

(6.25 µs at 1.28 Mcps). This period matches the delay specified in the mask defined in the

3GPP specifications (see TS 25 105 Section 6.5.2.1.2). The gain profiling operation is shown

by the lower waveform in Figure 37.


The application of the gain profile coefficients is controlled using the transmit enable (TxEn)

signal, which is an input to the six-channel DUC subsystem, shown by the upper waveform in

Figure 37. TxEn should be asserted eight chip periods before the first valid chip of a

TD-SCDMA burst, and de-asserted at the end of the last valid chip of the burst. The TxEn

input is common to all six channels, and is sampled at the same time as the baseband data at

the input to the DUC. When TxEn is asserted, the ramp-up profile is applied, and the last gain

value in the profile is held until TxEn is de-asserted. Following this, the ramp-down profile is

applied, and again the final value in the ramp-down profile is held until TxEn is asserted

again.

A separate gain profile waveform can be defined for each of the six channels. In most

applications, the gain profile waveform will have the same shape, but may be scaled by a

different factor for each channel to control the gain on a per-channel basis. This can be used

to compensate for frequency dependent gain variations in the analogue stages of the

transmitter, as each channel utilises a different transmit frequency. If separate gain profile

waveforms are not required on each channel, the ‘Use common gain profile for all channels’

option can be enabled in the 6-channel DUC subsystem mask. This reduces the amount of

block RAM resources required by the DUC by two BRAMs.

By default, all samples in the gain profile waveforms for the ramp-up and the ramp-down

sections are set to unity. Therefore, the TxEn signal has no effect, since the same gain value

is always applied. If it is desired to change the gain value only, then all 120 samples for the

TxEn

Output gain

Ramp-upperiod

8 chips

Downlink time slot(TD-SCDMA burst)

Ramp-downperiod

8 chips

Ramp-upsample 0

Ramp-upsample 119 (held)

Ramp-downsample 0

Ramp-downsample 119 (held)

Figure 37 DUC gain profiling operation and timing relative to TxEn input.


ramp-up section and the ramp-down section should be set to the same gain value. To use

power ramping, the user must set the gain profile values with a monotonically increasing

function (between zero and the full-power gain value) for the ramp-up section, and a

monotonically decreasing function (between the full-power gain value and zero) for the

ramp-down section. Selection of the ramp profile function must be made by the user as it is

dependent upon the behaviour of the complete transmitter chain.

The gain profile waveforms can be programmed using the gain profile data bus inputs to the

six-channel DUC subsystem (consisting of the Gain_Addr, Gain_Data and Gain_WE signals).

The 11-bit address map for gain profiling is shown in Figure 38. Gain_Data is a 16-bit

unsigned value (UFix_16_16) representing a gain value between zero and (almost) unity. To

write to a location in gain profile RAM, the address and gain value should be asserted on the

Gain_Addr and Gain_Data inputs at the same time as the Gain_WE is asserted (this signal is

active high).

The gain profile data bus can operate up to the full system clock rate at the input to the six-

channel DUC subsystem. However, to ease the timing constraints on the design it is

recommended that these signals be set to operate at a reduced sample rate, eg, by increasing

the sample period of the input gateways. It is the user’s responsibility to implement

additional address decoding logic if it is necessary to be able to address the gain profile data

in multiple DUC subsystems independently using a common address bus (alternatively use

separate write enable signals). Note that it is not possible to read values back from the gain

profile data RAM.

Ramp-up profile(120 samples)

0x00

0x780x80

Ramp-down profile(120 samples)

0xF80xFF

Channel 1

Channel 2

Channel 3

Channel 4

Channel 5

Channel 6

0x000

0x100

0x200

0x300

0x400

0x500

0x600

Offset

0x7FF

Absolute Address

Figure 38 DUC gain-profile address map. The ramp-up and ramp-down profiles are repeated for each channel. Unused regions are indicated in grey.


If the ‘Use common gain profile for all channels’ option is selected in the six-channel DUC

subsystem block mask, then a single ramp-up and ramp-down profile is shared by all

channels. In this scenario, the address bus size is reduced from 11 bits to eight bits.

5.2 DUC Baseband Input Blocks

The inputs to the TD-SCDMA DUC (6 Channels) block consists of six Simulink buses, each

carrying interleaved I/Q sample data and the associated framing signals. The DUC input

blocks, shown in Figure 39, can be used to convert a range of data formats into the format

used by the inputs of the DUC. The supported input formats and the use of the input

formatting blocks are discussed in the following sections. The width of the input data is

determined by the ‘Width of input data’ parameter in the mask of each input block.

5.2.1 DUC Baseband Input Formats

The DUC supports parallel I/Q, interleaved I/Q, serial I/Q and time-division multiplexed I/Q

input formats. A special ‘System Generator’ interface is also provided to simplify

interfacing with user-defined input logic implemented within System Generator.

All DUC input blocks implement a master interface, ie, the DUC generates the clock and

timing strobes. Consequently, the user logic must act as a slave and generate data that is

synchronous to the clock and timing strobes provided by the DUC input blocks.

DUC InParallel(TxEn)

TxEnTxEn

DUC_TXEN_IN

DUC InTDM

(Data)IQ

IQBus(1)

IQBus(2)

IQBus(3)

IQBus(4)

IQBus(5)

IQBus(6)

DUC_TDM_IN_DATA

DUC InTDM(Ctrl)

FS

DCLK

DUC_TDM_IN_CTRL

DUC InSysGen

I

QIQBus

DUC_SYSGEN_IN

DUC InSerial(Data)

IQ IQBus

DUC_SER_IN_DATA

DUC InSerial(Ctrl)

FS

DCLK

DUC_SER_IN_CTRL

DUC InParallel(Data)

I

QIQBus

DUC_PAR_IN_DATA

DUC InParallel

(Ctrl)DCLK

DUC_PAR_IN_CTRL

DUC InInterl 'd(Data)

IQ IQBus

DUC_INT_IN_DATA

DUC InInterl 'd(Ctrl)

FS

DCLK

DUC_INT_IN_CTRL

Figure 39 The DUC baseband input blocks.


5.2.1.1 Parallel I/Q

The most basic input format is parallel I/Q. The timing of this input format is shown in

Figure 40. Here, I and Q sample data are input on separate buses, with the data changing on

the rising edge of the data clock provided by the DUC. The DUC samples the input data on

the falling edge of the data clock (as highlighted in red in Figure 40). Parallel I/Q input data

ports are added to a design by instantiating the dfe_library/DUC Baseband Input

Blocks/DUC_PAR_IN_DATA block. The data clock is added by instantiating the dfe_library/DUC

Baseband Input Blocks/DUC_PAR_IN_CTRL block. The data clock generated by the

DUC_PAR_IN_CTRL block is intended to drive devices that are external to the DFE.

5.2.1.2 Interleaved, Parallel I/Q

An alternative to the parallel I/Q input format is the interleaved, parallel I/Q input format.

Here, I and Q sample data share the same parallel data bus and a framing strobe signal is

generated in addition to a data clock to allow the sample data to be decoded correctly. The

timing of this input format is shown in Figure 41. Note that I data precede the Q data and

that the framing strobe is asserted to identify the I data. I/Q data ports for this input format

are added to a design by instantiating the dfe_library/DUC Baseband Input

Blocks/DUC_INT_IN_DATA block. The data clock and framing strobe signal outputs are added

by instantiating the dfe_library/DUC Baseband Output Blocks/DUC_INT_IN_CTRL block. The

data clock generated by the DUC_INT_IN_CTRL block is intended to drive devices that are

external to the DFE.

1 / 1.28 MHz

I0

Q0

I1

Q1

I2

Q2

*_I[]

*_DCLK

*_Q[]

DUC Sample Point

TxEn(Optional/Common)

I3

Q3

Figure 40 Parallel I/Q input format.


5.2.1.3 Serial, Interleaved I/Q

Using parallel data buses for multiple input channels quickly consumes a considerable

number of input/output (I/O) resources. A more resource-efficient method of supplying data

is to use a serial data format. Here, I and Q sample data share a common data signal; a data

clock and framing strobe generated by the DUC allows the data to be interpreted correctly by

the receiver. The timing of this output format is shown in Figure 42.

Each ‘frame’ consists of 60 bits. The I data are output first and are ‘left-justified’, most-

significant bit first, in the first 30 bits. The Q data are left-justified in the last 30 bits. The

framing strobe signal is asserted by the DUC the first clock cycle before the first bit in each

frame (ie, the most-significant bit of the I data). Data ports for this input format are added to

a design by instantiating the dfe_library/DUC Baseband Input Blocks/DUC_SER_IN_DATA block.

I-1 I1 Q1 I2 Q2*_IQ[]

*_DCLK

*_FS

Q0I0

1 / 1.28 MHz

1 / 2.56 MHz


DUC Sample Point

Q-1

Figure 41 Interleaved, parallel I/Q input format.

N+29

I0(MSB)TxEn

(Optional)Q0(MSB)

TxEn(Optional)

I1(MSB) I1(MSB-1)

0 29N-1 30 59 10

*_IQ

*_DCLK

*_FS

STATE

I0(LSB)

N

Q0(LSB)

N+30

1 / 76.8 MHz

1 / 1.28 MHz

5958


DUC Sample Point

Figure 42 Serial, interleaved I/Q input format.


The data clock and framing strobe output signals are added by instantiating the

dfe_library/DUC Baseband Output Blocks/DUC_SER_IN_CTRL block.

The DUC gain profiling logic requires a transmit enable signal (TxEn), which is described in

Section 5.1.3.3. If desired, this signal can be included in the serial data stream, in which case

the TxEn bit immediately follows the least-significant bit of the I and Q data values in the

serial data frame. This bit should be set to the correct value for a particular I/Q sample pair.

If it is desired to include the TxEn bit in the serial data stream, the ‘Include ‘TxEn’ output’

option should be selected in the block mask of the DUC_SER_IN_DATA block. This also adds

a TxEn output port to the DUC_SER_IN_DATA block in the design. Alternatively, a dedicated

TxEn signal can be provided using the DUC_TXEN_IN block (see Section 5.2.1.6).

5.2.1.4 Time-Division Multiplexed, Parallel I/Q

An alternative to the serial input format for saving I/O resources is to interleave multiple

channels on a common parallel data bus. This is the time-division multiplexed (TDM),

parallel I/Q data format, which supports up to six interleaved I/Q channels in a fixed frame

structure. The timing of this input format is shown in Figure 43. Note that I data for all six

channels (A to F) precede the Q data. The framing strobe is asserted to identify the I data for

Channel A. I/Q data ports for this input format are added to a design by instantiating the

dfe_library/DUC Baseband Input Blocks/DUC_TDM_IN_DATA block. The data clock and framing

strobe output signals are added by instantiating the dfe_library/DUC Baseband Input

Blocks/DUC_TDM_IN_CTRL block.

DUC Sample Point

IA0 IB0 IC0 IF0 QF0 IA1 IB1*_IQ[]

*_DCLK

*_FS

QA0 QD0 QE0

1 / 1.28 MHz

1 / 15.36 MHz


QF-1QE-1

Figure 43 TDM I/Q input format.


5.2.1.5 ‘System Generator’ Interface

The input formats discussed in the previous sections all assume that the user wants to

interface the inputs of the DUC to logic/peripherals outside of the System Generator

environment. Sometimes it might be desirable to implement some additional processing of

the DUC input data within System Generator. To simplify this task the dfe_library/DUC

Baseband Input Blocks/DUC_SYSGEN_IN block is provided. This block interleaves and

registers the I and Q on separate parallel data buses, which are running at the chip rate, ie, to

signals with a clock enable period of 240 clock cycles.

5.2.1.6 Transmit Enable Signal Interface

The DUC gain profiling logic requires a transmit enable signal (TxEn), which is described in

Section 5.1.3.3. This input signal is synchronous to the baseband input data to signify the

start and end of a TD-SCDMA burst. To facilitate the use of the TxEn signal, the

dfe_library/DUC Baseband Input Blocks/DUC_TXEN_IN block can be used to add an input port to

a user design. The TxEn input is always sampled at the same time that the first data value is

sampled within a frame (typically on the second falling edge of *_DCLK following the

assertion of *_FS). A parameter in the DUC_TXEN_IN block mask allows the user to match the

TxEn input to the input data format in use, and can be used with the parallel, interleaved,

serial and TDM input data formats. The timing of the TxEn signal is shown in the sections

that describe each baseband input format, with the sampling point highlighted in red.

5.2.2 Using the DUC Baseband Input Blocks

The DUC baseband input blocks are summarised in Table 15. The data signals and control

signals for each interface type are implemented using separate blocks. This way it is possible

to share one set of control signals between multiple input channels. The DUC_SYSGEN_IN

block is a special block that can be used to convert parallel in-phase and quadrature signals

operating at the chip rate into the input format used by the TD-SCDMA DUC (6 Channels)

block. Thus, this block can be used to interface user-defined logic implemented within

System Generator to the input of the DUC.


Format Data / Control Block Embedded Gateway Suffix

Data DUC_PAR_IN_DATA I data input (_I port suffix) Q data input (_Q port suffix) Parallel

I/Q Control DUC_PAR_IN_CTRL Data clock output (_DCLK port suffix)

Data DUC_INT_IN_DATA I/Q data input (_IQ port suffix) Interleaved

I/Q Control DUC_INT_IN_CTRL

Data clock output (_DCLK port suffix) Framing strobe output (_FS port suffix)

Data DUC_SER_IN_DATA I/Q data input (_IQ port suffix) Serial I/Q

Control DUC_SER_IN_CTRL Data clock output (_DCLK port suffix) Framing strobe output (_FS port suffix)

Data DUC_TDM_IN_DATA I/Q data input (_IQ port suffix) TDM

Control DUC_TDM_IN_CTRL Data clock output (_DCLK port suffix) Framing strobe output (_FS port suffix)

Parallel, interleaved, serial, TDM

Data DUC_TXEN_IN Transmit enable input (gateway with no suffix)

‘System Generator’ Data DUC_SYSGEN_IN

I data (no embedded gateways) Q data (no embedded gateways)

5.2.3 Specifying the Port Prefixes

With the exception of the DUC_SYSGEN_IN block, DUC input formatting blocks all embed

System Generator gateway blocks. The DUC_*_IN_DATA blocks embed Gateway In blocks, and

the DUC_*_IN_CTRL blocks embed Gateway Out blocks. The names assigned to these

gateways (and hence the name assigned to the corresponding ports when the design is built)

are, by default, derived from the name given to the instantiated block. Alternatively, by

clearing the ‘Use block name to set gateway prefix’ checkbox in the block’s mask, an

Table 15 DUC baseband port suffixes.


expression that evaluates to a string can be entered in the ‘Gateway prefix’ edit box. As an

example, the mask for the DUC_SER_IN_CTRL block is shown in Figure 44.

When naming a gateway, a suitable suffix is added to the gateway prefix to identify the

function of the signal. The suffixes used are given in Table 15. For example, if a

DUC_SER_IN_CTRL block is added to a design and renamed DUC_IN then, when built, the

final design will include two output ports called DUC_IN_FS and DUC_IN_DCLK.

5.3 DDC Library Blocks

The following blocks can be used to construct DDC designs.

5.3.1 DDC_IN Block

The DDC_IN block provides a convenient method of adding an input gateway to DDC

designs. The output of this block is compatible with the DDC 1/4-Rate Mixer and DDC Mixer

blocks.


The symbol for the DDC_IN block is shown in Figure 45. The input to this block are defined

in Table 16 and the output in Table 17.

Figure 44 Mask for the DUC_SER_IN_CTRL block.

DDC IF Input(14-bit)

DDC_IN

Figure 45 The DDC_IN block.



1 - double ×4 IF input data. This block accepts input data in the range -1 to (almost) +1.


1 - fix_x_y ×4

Registered IF input data. The width of the output data, x, is specified through the block mask. Data are always output in the range -1 to (almost) +1 (ie, y = x – 1).


The width of the input gateway can be set withon the range eight to 16 bits. To change the

port width, edit the ‘Width of input port’ subsystem mask field, shown in Figure 46. Note

that the current port width is displayed on the mask icon (see Figure 45).

The DDC_IN block embeds a System Generator Gateway In block. The name assigned to this

gateway (and hence the name assigned to the corresponding port when the design is built) is,

by default, derived from the name given to the instantiated DDC_IN block. Alternatively, by

clearing the ‘Use block name to set gateway prefix’ checkbox, an expression that evaluates to

a string can be entered in the ‘Gateway prefix’ edit box. When naming the input gateway the

‘_D’ suffix is added to the gateway prefix. For example, if the DDC_IN block is renamed IF 1

then, by default, the final design will have a corresponding input port IF_1_D.

Table 16 DDC_IN inputs.

Table 17 DDC_IN outputs.

Figure 46 Mask for the DDC_IN block.


5.3.2 DDC 1/4-Rate Mixer Block

The DDC 1/4-Rate Mixer block implements a quarter-rate mixer to translate real IF input data

to quadrature baseband. This block offers a reduced logic resource alternative to using the

Local Oscillator and DDC Mixer blocks when fine-tuning of the IF is not required. The input to

this block is compatible with the DDC_IN block. The output is compatible with the TD-

SCDMA DDC (6 Channels) block.


The symbol for the DDC 1/4-Rate Mixer block is shown in Figure 47. The inputs to this block

are defined in Table 18 and the outputs in Table 19.


1 IF fix_x_y ×4

IF input data. This input is compatible with the output of the DDC_IN block (ie, signal types in the range fix_8_7 to fix_16_15).

2 Sync bool Any Mixer synchronisation input. Asserting this input from one or more clock cycles will cause the state of the mixer to be reset.


1 I fix_18_17 ×1

2 Q fix_18_17 ×1

3 Rdy bool ×1

Quadrature output data. New I/Q data are output every four clock cycles with the in-phase data output on the I port and the quadrature data output on the Q port. Rdy is asserted once every four clock cycles to signal when the output data are valid.

DDC Mixer(1/4-Rate)

IF

Sync

I

Q

Rdy

DDC 1/4-Rate Mixer

Figure 47 The DDC 1/4-Rate Mixer block.

Table 18 DDC 1/4-Rate Mixer inputs.

Table 19 DDC 1/4-Rate Mixer outputs.


5.3.3 DDC Mixer Block

The DDC Mixer block implements a ‘full’ mixer to translate real IF input data to quadrature

baseband. This block is designed to be driven using the Local Oscillator block. The input to

this block is compatible with the DDC_IN block. The output is compatible with the TD-

SCDMA DDC (6 Channels) block.


The symbol for the DDC Mixer block is shown in Figure 48. The inputs to this block are



1 IF fix_x_y ×4 IF input data. This input is compatible with the output of the DDC_IN block (ie, signal types in the range fix_8_7 to fix_16_15).

LO Simulink Bus

• Mag fix_18_17 ×1 2

• Sign bool ×1

Local oscillator data (interleaved). This input is compatible with the output of the Local Oscillator block.


1 I fix_18_17 ×1

2 Q fix_18_17 ×1

3 Rdy bool ×1

Quadrature output data. New I/Q data are output every four clock cycles with the in-phase data output on the I port and the quadrature data output on the Q port. Rdy is asserted once every four clock cycles to signal when the output data are valid.

DDC Mixer

IF

LO

I

Q

Rdy

DDC Mixer

Figure 48 The DDC Mixer block.

Table 20 DDC Mixer inputs.

Table 21 DDC Mixer outputs.


5.3.4 TD-SCDMA DDC (6 Channels) Block

The TD-SCDMA DDC (6 Channels) block is the main building block for the DDC designs, it

incorporates all the necessary logic to extract up to six TD-SCDMA carriers from a single,

complex 76.8 MSps input. The carriers to be extracted must be centred on frequencies in the

range ±4 MHz (with a 200 kHz raster). In addition to down-conversion, filtering and down-

sampling, this block also allows the gain and signal path delay to be adjusted on a per-

channel basis.

In designs that do not require the use of all six channels, unused outputs should be terminated

using the Simulink Terminator block found in the standard Simulink library. The logic

associated with the unused channels will be removed by the build tools.

TD-SCDMA DDC(6 Channels)

I

Q

Rdy

Freq(1)

Freq(2)

Freq(3)

Freq(4)

Freq(5)

Freq(6)

Gain(1)

Gain(2)

Gain(3)

Gain(4)

Gain(5)

Gain(6)

Delay(1)

Delay(2)

Delay(3)

Delay(4)

Delay(5)

Delay(6)

Sync

IQBus(1)

IQBus(2)

IQBus(3)

IQBus(4)

IQBus(5)

IQBus(6)

TD-SCDMA DDC (6 Channels)

Figure 49 The TD-SCDMA DDC (6 Channels) block.



The symbol for the TD-SCDMA DDC (6 Channels) block is shown in Figure 49. The inputs to

this block are defined in Table 22 and the outputs in Table 23.


1 I fix_18_17 ×1

2 Q fix_18_17 ×1

3 Rdy bool ×1

Quadrature input data. New I/Q data are expected every four clock cycles. The in-phase data should be input on the I port and the quadrature data should be input on the Q port. Rdy should be asserted once every four clock cycles to signal when the input data are valid.

4–9 Freq(*) (* = 1…6)

fix_6_0 Any

Intermediate mixer DDS frequency. The intermediate mixer can be tuned over the range -4.0 to +4.0 MHz in steps of 200 kHz. If the signal of interest is centred on fIF at the input to the mixer then

Freq(*) = fIF / 0.2 MHz

Note that the intermediate mixer mixes down by the DDS output frequency.

10–15 Gain(*) (* = 1…6)

ufix_16_16 Any

Signal path attenuation. The gain of the DDC can be adjusted on a per-channel basis. The programmable element can be adjusted over the range zero to (almost) 1. Note that the programmable gain is in addition to any fixed signal path gain specified at build time.

16–21 Delay(*) (* = 1…6)

ufix_4_0 Any

Signal path delay. The signal path delay can be increased in increments of 1/15 of a chip period, up to a maximum of 1 chip period.

22 Sync bool Any

DDS synchronisation input. Asserting this input from one or more clock cycles will cause the intermediate mixer DDSs to be reset. Note that due to the signal path delay, it will take approximately 30 µs for the filter chain to be fully flushed following a synchronisation event.

Table 22 TD-SCDMA DDC (6 Channels) inputs.


Output Mask Name Type Period Description IQBus(*) (* = 1…6)

Simulink Bus

• IQ fix_x_y ×1

• Rdy bool ×1

• Is Q bool ×1 1–6

Quadrature output data (interleaved). I/Q output data are output at the chip rate. The Rdy and Is Q signals control the flow of data, the timing of which is shown in Figure 50. Note that the I data precede the Q data and that the output data are registered within the TD-SCDMA DDC (6 Channels) subsystem. This means that IQ remains valid between events on Rdy. The width of the output data, x, is specified through the block mask. Data are always output in the range -1 to (almost) +1 (ie, y = x – 1).


The output data resolution and nominal gain of the six-channel DDC subsystem is

configurable. The output data resolution can be set between eight and 24 bits in increments

of two and the signal path gain can be set between ×1 (0 dB) and ×32 (+30 dB) in increments

of 6 dB. These parameters can be configured through the subsystem mask, shown in

Figure 51. Note that these parameters are used to configure the DDC subsystem at build

time, ie, these are not programmable settings that can be modified in an operating FPGA.

Table 23 TD-SCDMA DDC (6 Channels) outputs.

Q-1 I0 Q0IQ

Rdy

Is Q

1 / 1.28 MSps

IQB

us(*

)

Clk

I1

120 ClockCycles

120 ClockCycles

Figure 50 Timing of the IQ, Rdy and Is Q outputs of the TD-SCDMA DDC (6 Channels) block.


The output word size is implemented at the output of the final filter stage. The DDC filters

are implemented as MAC filters. Adjusting the output word size parameter simply changes

the number of bits extracted from the output accumulator. Note that the MAC module

incorporates basic data rounding to minimise the introduction of DC offset. The ‘rounding

constant’ is adjusted accordingly when the output word size is adjusted.

As shown in Figure 14, the fixed DDC signal path gain is applied in two places. An optional

fixed gain of two is implemented at the output of the programmable gain stage. The

remaining gain adjustment is applied at the output of the final filter stage. Clipping logic is

included in the design to prevent wrapping on data overflow.

5.4 DDC Baseband Output Blocks

The output of the TD-SCDMA DDC (6 Channels) block consists of six Simulink buses, each

carrying interleaved I/Q sample data and the associated framing signals. The DDC output

blocks, shown in Figure 52, can be used to convert the output from the DDC to a more

system-friendly format. The supported output formats and the use of the output formatting

blocks are discussed in the following sections. Note that in all cases, the width of the output

data is determined by the output configuration of the preceding TD-SCDMA DDC (6 Channels)

block.

Figure 51 Mask for the TD-SCDMA DDC (6 Channels) block.


5.4.1 DDC Baseband Output Formats

The DDC supports parallel I/Q, interleaved I/Q, serial I/Q and time-division multiplexed I/Q

output formats. A special ‘System Generator’ interface is also provided to simply the

interfacing with post-DDC, user-defined logic implemented within System Generator.

5.4.1.1 Parallel I/Q

The most basic output format is parallel I/Q. Here, I and Q sample data are output on

separate buses together with a data clock with the rising edge aligned with the centre of the

data window. The timing of this output format is shown in Figure 53. Parallel I/Q data ports

are added to a design by instantiating the dfe_library/DDC Baseband Output

Blocks/DDC_PAR_OUT_DATA block. The data clock is added by instantiating the

dfe_library/DDC Baseband Output Blocks/DDC_PAR_OUT_CTRL block.

UnusedDDC TDMChannel

Unused TDMChannel

DDC OutTDM

(Data)IQ

IQBus(1)

IQBus(2)

IQBus(3)

IQBus(4)

IQBus(5)

IQBus(6)

DDC_TDM_OUT_DATA

DDC OutTDM(Ctrl)

FS

DCLKIQBus

DDC_TDM_OUT_CTRL

DDC Out(Sys Gen)

I

QIQBus

DDC_SYSGEN_OUT

DDC OutSerial(Data)

IQIQBus

DDC_SER_OUT_DATA

DDC OutSerial(Ctrl)

FS

DCLKIQBus

DDC_SER_OUT_CTRL

DDC OutParallel(Data)

I

QIQBus

DDC_PAR_OUT_DATA

DDC OutParallel

(Rdy)RdyIQBus

DDC_PAR_OUT_CTRL2

DDC OutParallel

(Ctrl)DCLKIQBus

DDC_PAR_OUT_CTRL

DDC OutInterl 'd(Data)

IQIQBus

DDC_INT_OUT_DATA

DDC OutInterl 'd

(Rdy+IsQ)

Is Q

RdyIQBus

DDC_INT_OUT_CTRL2

DDC OutInterl 'd(Ctrl)

FS

DCLKIQBus

DDC_INT_OUT_CTRL

Figure 52 The DDC baseband output blocks.


The data clock generated by the DDC_PAR_OUT_CTRL block is intended to drive logic

external to the host FPGA. If interfacing the output of the DDC to user-defined logic

implemented within the same FPGA as the DDC, a data ready signal is more useful. Such a

signal can be added by instantiating the dfe_library/DDC Baseband Output

Blocks/DDC_PAR_OUT_CTRL2 block. The timing of the parallel I/Q interface when using this

configuration is shown in Figure 54.

5.4.1.2 Interleaved, Parallel I/Q

An alternative to the parallel I/Q output format is the interleaved, parallel I/Q output format.

Here, I and Q sample data share the same parallel data bus and a framing strobe signal is

generated in addition to a data clock to allow the sample data to be decoded correctly. The

timing of this output format is shown in Figure 55. Note that I data precede the Q data and

that the framing strobe is asserted to identify the I data. I/Q data ports for this output format

are added to a design by instantiating the dfe_library/DDC Baseband Output

Blocks/DDC_INT_OUT_DATA block. The data clock and framing strobe signals are added by

instantiating the dfe_library/DDC Baseband Output Blocks/DDC_INT_OUT_CTRL block.

1 / 1.28 MHz

I3

Q3

I0

Q0

I1

Q1

I2

Q2

*_I[]

*_DCLK

*_Q[]

Figure 53 Parallel I/Q output format.

1 / 1.28 MHz

Q1Q0

I0*_I[]

*_RDY

*_Q[]

I1

CLK

1 / 307.2 MHz

Figure 54 Alternative parallel I/Q output format.


The data clock generated by the DDC_INT_OUT_CTRL block is intended to drive logic external

to the host FPGA. If interfacing the output of the DDC to user-defined logic implemented

within the same FPGA as the DDC, a data ready signal is more useful. Such a signal can be

added by instantiating the dfe_library/DDC Baseband Output Blocks/DDC_INT_OUT_CTRL2

block. The timing of the interleaved, parallel I/Q interface when using this configuration is

shown in Figure 56. Note that in this configuration the framing strobe signal is replaced with

an ‘is Q’ signal and that this signal is asserted to identify the Q data. This is consistent with

the low level interface used between the DFE library blocks.

5.4.1.3 Serial, Interleaved I/Q

Using parallel data buses to output the data from multiple channels quickly consumes a

considerable number of I/O resources. A more resource-efficient method of outputting data

is to use a serial data format. Here, I and Q sample data share a common data signal; a data

clock and framing strobe generated by the DDC allows the data to be interpreted correctly by

the receiver. The timing of this output format is shown in Figure 57. Each ‘frame’ consists

of 60 bits. The I data are output first and are ‘left-justified’, most-significant bit first, in the

first 30 bits. The Q data are left-justified in the last 30 bits. The framing strobe signal is

Q3I0 Q0

1 / 1.28 MHz

I3I1 Q1 I2 Q2*_IQ[]

*_DCLK

*_FS

1 / 2.56 MHz

Figure 55 Interleaved, parallel I/Q output format.

1 / 2.56 MHz

I0*_IQ[]

*_RDY

*_IS_Q

Q0

CLK

1 / 307.2 MHz

Figure 56 Alternative interleaved, parallel I/Q output format.


asserted to identify the first bit in each frame (ie, the most-significant bit of the I data). Data

ports for this output format are added to a design by instantiating the dfe_library/DDC Baseband

Output Blocks/DDC_SER_OUT_DATA block. The data clock and framing strobe signals are

added by instantiating the dfe_library/DDC Baseband Output Blocks/DDC_SER_OUT_CTRL

block.

5.4.1.4 Time-Division Multiplexed, Parallel I/Q

An alternative to the serial output format for saving I/O resources is to interleave multiple

channels on a common parallel data bus. This is the time-division multiplexed (TDM),

parallel I/Q data format, which supports up to six interleaved I/Q channels in a fixed frame

structure. The timing of this output format is shown in Figure 58. Note that I data for all six

channels (A to F) precede the Q data. The framing strobe is asserted to identify the I data for

Channel A. I/Q data ports for this output format are added to a design by instantiating the

dfe_library/DDC Baseband Output Blocks/DDC_TDM_OUT_DATA block. (Note that unused inputs

to the DDC_TDM_OUT_DATA block can be tied off using the dfe_library/DDC Baseband Output

Blocks/Unused TDM Channel block.) The data clock and framing strobe signals are added by

instantiating the dfe_library/DDC Baseband Output Blocks/DDC_TDM_OUT_CTRL block.

1 / 76.8 MHz

1 / 1.28 MHz

I0(MSB) I0(MSB-1) I0(LSB) Q0(MSB) Q0(MSB-1) Q0(LSB) I1(MSB) I1(MSB-1) I1(MSB-2)

10 29N-1 3130 59N+29 10 2

*_IQ

*_DCLK

*_FS

STATE

Figure 57 Serial, interleaved I/Q output format.


5.4.1.5 ‘System Generator’ Interface

The output formats discussed in the previous sections all assume that the user wants to

interface the output of the DDC to logic/peripherals outside of the System Generator

environment. Sometimes it might be desirable to implement some additional processing of

the DDC output data within System Generator. To simplify this task the dfe_library/DDC

Baseband Output Blocks/DDC_SYSGEN_OUT block is provided. This block deinterleaves and

registers the I and Q data output from the DDC and down-samples these data to the chip rate

(ie, to signals with a clock enable period of 240 clock cycles).

5.4.2 Using the DDC Baseband Output Blocks

The DDC baseband output blocks are summarised in Table 24. The data signals and control

signals for each interface type are implemented using separate blocks. This way it is possible

to share one set of control signals between multiple output channels. Note that an alternative

control interface is provided for both the parallel and interleaved data formats. These are

designed to be used when implementing a DDC design for inclusion as a ‘black box’ within a

larger FPGA design. The DDC_SYSGEN_OUT block is a special block that can be used to

convert the output of the TD-SCDMA DDC (6 Channels) block into parallel in-phase and

quadrature signals operating at the chip rate. Thus, this block can be used to interface the

output of the DDC to user-defined logic implemented within System Generator. An

additional block, Unused TDM Channel, is also provided. This block may be used to tie off

unused inputs to the DDC_TDM_OUT_DATA block.

IA0 IB0 IC0 IF0 QF0 IA1 IB1 IC1

1 / 1.28 MHz

*_IQ[]

*_DCLK

*_FS

QA0 QD0 QE0

1 / 15.36 MHz

Figure 58 TDM I/Q output format.


Format Data / Control Block Outputs

(Embedded Gateway Suffix)

Data DDC_PAR_OUT_DATA I data (_I port suffix) Q data (_Q port suffix)

Control DDC_PAR_OUT_CTRL Data clock (_DCLK port suffix) Parallel

I/Q

Control (Alternative)

DDC_PAR_OUT_CTRL2 Data ready strobe (_RDY port suffix)

Data DDC_INT_OUT_DATA I/Q data (_IQ port suffix)

Control DDC_INT_OUT_CTRL Data clock (_DCLK port suffix) Framing strobe (_FS port suffix)

Interleaved I/Q

Control (Alternative)

DDC_INT_OUT_CTRL2 Data ready strobe (_RDY port suffix) Q data flag (_IS_Q port suffix)

Data DDC_SER_OUT_DATA I/Q data (_IQ port suffix) Serial I/Q

Control DDC_SER_OUT_CTRL Data clock (_DCLK port suffix) Framing strobe (_FS port suffix)

Data DDC_TDM_OUT_DATA I/Q data (_IQ port suffix) TDM

Control DDC_TDM_OUT_CTRL Data clock (_DCLK port suffix) Framing strobe (_FS port suffix)

‘System Generator’ Data DDC_SYSGEN_OUT

I data (no embedded gateways) Q data (no embedded gateways)

The input to the DDC baseband output blocks is a Simulink bus containing three signals, IQ, Is Q

and Rdy. Ordinarily, IQ should only be considered valid when Rdy is asserted. However, in the

interests of minimising flip-flop usage, the DDC_PAR_OUT_DATA, DDC_SER_OUT_DATA,

DDC_TDM_OUT_DATA and DDC_SYSGEN_OUT blocks all sample the IQ signal in the clock cycle after

Rdy is asserted. This behaviour is acceptable because the TD-SCDMA DDC (6 Channels) block has

been designed so that IQ remains valid between events on Rdy.

Table 24 DDC baseband output port suffixes.


5.4.3 Specifying the Output Port Prefix

With the exception of the DDC_SYSGEN_OUT block, DDC output formatting blocks all

embed System Generator Gateway Out blocks. The names assigned to these gateway (and

hence the name assigned to the corresponding ports when the design is built) is, by default,

derived from the name given to the instantiated block. Alternatively, by clearing the ‘Use

block name to set gateway prefix’ checkbox in the block’s mask, an expression that evaluates

to a string can be entered in the ‘Gateway prefix’ edit box. As an example, the mask for the

DDC_SER_OUT_CTRL block is shown in Figure 59.

When naming an output gateway a suitable suffix is added to the gateway prefix to identify

the function of the signal. The suffixes used are given in Table 24. For example, if a

DDC_SER_OUT_CTRL block is added to a design and renamed DDC_OUT then, when built, the

final design will include two output ports called DDC_OUT_FS and DDC_OUT_DCLK.

5.5 Shared DDC/DUC Library Blocks

The following blocks can be used in the construction of both DUC and DDC designs.

5.5.1 Local Oscillator Block

The Local Oscillator block implements a DDS with an output that is compatible with the

DUC Mixer and DDC Mixer blocks. Note that one Local Oscillator block may be used to drive

multiple mixer blocks.


The symbol for the Local Oscillator block is shown in Figure 60. The inputs to this block are


Figure 59 Mask for the DDC_SER_OUT_CTRL block.



1 Freq ufix_32_x Any

Frequency control word. The local oscillator can be tuned over the range 0 to 76.8 MHz with a resolution of approximately 0.02 Hz. If the wanted IF is fIF then

Freq = 232 × fIF / 76.8 MHz

Note that the Local Oscillator block always interprets Freq as an ufix_32_0 signal.

2 Sync bool Any

Synchronisation input. Asserting this input for one or more clock cycles will reset the phase accumulator to zero and restart the dither generator.


LO Simulink Bus

• Mag fix_18_17 ×1 1

• Sign bool ×1

Local oscillator data (interleaved). The real and imaginary parts of the local oscillator output are output as interleaved, sign plus magnitude data. The timing of these outputs is shown in Figure 61.

LocalOscil lator

Freq

SyncLO

Local Oscil lator

Figure 60 The Local Oscillator block.

Table 25 Local Oscillator inputs.

Table 26 Local Oscillator outputs.


Mag

Sign

1 / 76.8 MSps

LO

CE (×4)

Clk

‘IF Data’

| cos (θ0) |

cos (θ0) < 0

| sin (θ0) |

sin (θ0) < 0

| sin (θ0) |

sin (θ0) < 0

| cos (θ0) |

cos (θ0) < 0

D0

| cos (θ1) |

cos (θ1) < 0

Figure 61 Timing of the Mag and Sign outputs of the Local Oscillator block.

5.5.2 Control Constant Block

The Control Constant block can be used as a convenient method of ‘tying-off’ unused control

ports in DUC and DDC designs.


The symbol for the Control Constant block is shown in Figure 62. The outputs to this block

are defined in Table 27.


1 - Various ×1 Control output. The type and function of this output is dependent on the mask parameters.

LO Freq.19.200 MHz

Control Constant

Figure 62 The Control Constant block.

Table 27 Control Constant outputs.



The mode of operation of the Control Constant block can be set via a drop-down box provided

on the block mask, shown in Figure 63. The visibility of the remaining mask controls is

dependent on the control ‘type’ selected. Table 28 lists the supported control types and

defines the range of valid input values together with the output signal type for each mode.

Constant Type Description Range Type

LO frequency Use to tie off the Freq input to Local Oscillator block. The IF frequency is specified in MHz.

Unrestricted ufix_32_0

Intermediate LO frequency

Use to tie off Freqx inputs to the TD-SCDMA DUC (6 Channels) block and Freq(x) inputs to the TD-SCDMA DDC (6 Channels) block. Available settings are presented as a drop-down list.

±4.0 MHz fix_6_0

Gain (as linear value)

Use to tie off Gain(x) inputs to the TD-SCDMA DDC (6 Channels) block. The gain is specified as a linear value.

0.0 – 1.0 ufix_16_16

Gain (as dB value) As above but with the gain specified as a dB value. ≤ 0 dB ufix_16_16

DDC delay

Use to tie off the Delay input to the TD-SCDMA DDC (6 Channels) block. This allows the DDC signal path delay to be increased in multiples of 1/15 chip period.

0 – 15 ufix_4_0

Tie ‘Phase Acc’ sync low Use to tie Sync inputs to zero. - bool

Figure 63 Mask for the Control Constant block.

Table 28 Supported ‘control constants’.


5.5.3 IF_DATA_CE and BB_DATA_CE Blocks

The IF_DATA_CE block can be used to add an IF data clock enable output to a design, ie, one

event every four clock cycles. The BB_DATA_CE block, on the other hand, adds a clock

enable output that operates at twice the chip rate, ie, one event every 120 clock cycles.


The symbols for the IF_DATA_CE and BB_DATA_CE blocks are shown in Figure 64. The

outputs to these blocks are defined in Table 29 and Table 30.


1 - bool ×1 IF data clock enable output. This output is asserted once every four clock cycles.


1 - bool ×1 Baseband data clock enable output. This output is asserted once every 120 clock cycles, ie, two events every chip period.


The IF_DATA_CE and BB_DATA_CE blocks embed a System Generator Gateway Out block.

The name assigned to this gateway (and hence the name assigned to the corresponding port

when the design is built) is, by default, derived from the name given to the instantiated block.

Alternatively, by clearing the ‘Use block name to set gateway name’ checkbox in the block’s

mask, an expression that evaluates to a string can be entered in the ‘Gateway name’ edit box.

The mask for the IF_DATA_CE block is shown in Figure 65.

IF DataStrobe

IF_DATA_CE

BB DataStrobe

BB_DATA_CE

Figure 64 The IF_DATA_CE block (left) and BB_DATA_CE block (right).

Table 29 IF_DATA_CE outputs.

Table 30 BB_DATA_CE outputs.


Figure 65 Mask for the IF_DATA_CE block.


6 Resource Summary

6.1 Resource Estimates for the Main Library Blocks

Resource estimate data were generated by compiling and building the main library blocks

using the ‘bitstream’ compilation target. An example of the models used to generate the

resource estimate data is shown in Figure 66. Input and output gateway blocks are added as

appropriate to the device under test; the inputs are all tied to zero and the outputs terminated.

Table 31 summarises the resource estimates for those blocks which are common to both DUC

and DDC designs. Table 32 and Table 33 summarise the resource estimates for the main

DUC and DDC library blocks, respectively. The indented entries represent low level blocks.

Note that all the estimates have been generated independently of each other. This means that

the resource estimates for the top level blocks do not necessarily equal the sum of the relevant

low level blocks. Estimates are included for both the TD-SCDMA DUC (6 Channels) and TD-

SCDMA DDC (6 Channels) blocks when fewer than six channels are utilised. Although unused

logic is optimised away from these blocks at build time, it will be noted that these blocks are

most resource efficient when all six channels are used.

Library Block FFs LUTs Slices BRAM DSP48s

Local Oscillator 130 103 89 2 0

Dithered Phase Accumulator 105 90 73 0 0

2-Ch DDS LUT 26 24 14 2 0

In

Sync In

LocalOscil lator

Freq

SyncLO

Local Oscil lator

Out LO Sign

Out LO Mag

In

Freq In

0

0

Sy stemGenerator

<Mag>

<Sign>

Figure 66 Example resource estimate model.

Table 31 DFE library shared block resource estimates.


Library Block FFs LUTs Slices BRAM DSP48s TD-SCDMA DUC (6 Channels) (All channels used) 1599 676 905 17 19

DUC Filter 1 (6 instances) 86 28 49 1 1

DUC Filter 2 (6 instances) 80 28 46 1 1 Intermediate 6-Ch DUC Mixer

(With Combiner) 277 208 154 3 3

DUC Filter 3 (Post Mixer) 134 48 71 1 2

DUC Filter 4 (Post Mixer) 133 82 72 1 2 TD-SCDMA DUC (6 Channels) (Four channels used) 1263 552 717 13 15

TD-SCDMA DUC (6 Channels) (Three channels used) 1095 490 623 11 13

TD-SCDMA DUC (6 Channels) (Two channels used) 927 428 529 9 11

DUC Mixer 130 38 84 0 1

Library Block FFs LUTs Slices BRAM DSP48s TD-SCDMA DDC (6 Channels) (All channels used) 1435 1047 802 15 20

DDC Filter 1 62 51 33 1 2

DDC Filter 2 68 57 41 1 2

Intermediate DDC Mixer 409 310 221 1 4

DDC Filter 3 (6 instances) 61 35 34 1 1

DDC PS Filter (6 instances) 97 98 72 1 1 TD-SCDMA DDC (6 Channels) (Four channels used) 1131 831 632 11 16

TD-SCDMA DDC (6 Channels) (Three channels used) 843 624 479 9 12

TD-SCDMA DDC (6 Channels) (Two channels used) 691 516 395 7 10

DDC 1/4-Rate Mixer 43 71 41 0 0

DDC Mixer 65 4 35 0 1

Table 32 DFE library DUC block resource estimates.

Table 33 DFE library DDC block resource estimates.


6.2 Resource Estimates for Example DFE Configurations

We can use the resource estimates presented in the previous section to generate first-order

estimates of the resources used by other DFE configurations. Two configurations are

considered here, a 12-channel DUC/DDC configured for three carriers on four antennas and

an 18-channel DUC/DDC configured for six carriers on three antennas.

The resource estimate calculations for the 12-channel example are presented in Table 34.

The DUC subsystem is constructed using four TD-SCDMA DUC (6 Channels) blocks. In this

configuration only three of the six TD-SCDMA DUC (6 Channels) channels are used and each

output is mixed to the output IF using a separate DUC Mixer block, with a single Local

Oscillator block used to generate the LO data. A similar architecture is used for the DDC

subsystem. From Table 34 it can be seen that this design will use approximately half the

slices of an SX25 and a third of the slices of an SX35. Note that these estimates are for the

core of the DFE design only, additional interfacing logic, which will typically be application-

specific, is not taken into account.

Design Description Slices BRAM DSP48s

DUC (4 antennas, 3 carriers) 2917 46 56

TD-SCDMA DUC (6 Channels) (×4 (3 channels)) 2492 44 52

DUC Mixer (×4) 336 0 4

Local Oscillator (×1) 89 2 0

DDC (4 antennas, 3 carriers) 2145 38 52

TD-SCDMA DDC (6 Channels) (×4 (3 channels)) 1916 36 48

DDC Mixer (×4) 140 0 4


Total 5062 84 108

SX25 Utilisation 49% 66% 84%


Table 35 shows the equivalent figures for the 18-channel example. Note that in this example

all six TD-SCDMA DUC (6 Channels) and TD-SCDMA DDC (6 Channels) block channels are used.

The improved efficiency of these blocks when all six channels are used is reflected in the

Table 34 Resource estimates for a 12-channel DUC/DDC configured with four inputs and four outputs.


slice estimates; although the number of channels has increased by 50% compared to the

previous example, the slice count due to the TD-SCDMA DDC (6 Channels) blocks has

increased by only 26%. The corresponding figure for the TD-SCDMA DUC (6 Channels) blocks

is less than 10%. Overall, this design will use approximately 55% of the slices of an SX25

and just under 40% of the slices of an SX35. However, this design uses virtually all of the

DSP48s in an SX25. Therefore, whilst this design fits into an SX25 on paper, careful

constraining of the design might be required to meet timing in the lowest speed grade device

because of the potential routing delays. As in the previous example, these estimates are for

the core of the DFE design only and do not include any allowance for used-implemented

interfacing logic.

Design Description Slices BRAM DSP48s

DUC (3 antennas, 6 carriers) 3056 53 60

TD-SCDMA DUC (6 Channels) (×3 (6 channels)) 2715 51 57

DUC Mixer (×3) 252 0 3


DDC (3 antennas, 6 carriers) 2600 47 63

TD-SCDMA DDC (6 Channels) (×3 (6 channels)) 2406 45 60

DDC Mixer (×3) 105 0 3


Total 5656 100 123



Note that data presented in these sections are estimates and, as such, should be treated with some

caution. The final numbers in a real design may be affected by a number of factors including the

design configuration, other logic in the device, the size of the target device, the choice of synthesis

tool (the estimates provided here were all generated using Xilinx’s XST) and the configuration of

the tools used during the build process.

Table 35 Resource estimates for an 18-channel DUC/DDC configured with three inputs and three outputs.


References

1. ETSI, Universal Mobile Telecommunications System (UMTS); UTRA (BS) TDD: Radio transmission and reception (3GPP TS 25.105 version 5.2.0 Release 5), ETSI TS 125 105, version 5.2.0, September 2002

2. Xilinx, LogiCore DDS v5.0, product specification, DS246, version 2.1, 28 April 2005

3. Harris, F J, “On the Use of Windows for Harmonic Analysis with the Discrete Fourier Transform”, PROC IEEE, vol 66, no 1, pp 51-83, January 1978

4. ETSI, Universal Mobile Telecommunications System (UMTS); UTRA (BS) TDD: Base station conformance testing (3GPP TS 25.142 version 5.2.0 Release 5), ETSI TS 125 105, version 5.2.0, September 2002


Appendix A – Library Overview

The DFE library is supplied either as a compressed ZIP file or on CDROM. The structure of

the library files is described below and the main files are identified. Before blocks from the

DFE library can be used in new designs it is necessary to add the dfe_library and

dfe_library\low level directories to the Matlab path. This can be achieved by browsing to the

dfe_library directory from within Matlab and running addLibraryToPath.m. Alternatively,

add the directories manually using Matlab’s ‘pathtool’ utility (invoked by typing pathtool at

the Matlab command prompt). Note that once present on the Matlab path, the top-level

library blocks should appear in the ‘Simulink Library Browser’.

dfe_library – This directory contains the implementation files for the DFE library.

dfe_library.mdl – Simulink library file containing the top-level DFE library blocks. New designs may be constructed using blocks from this library.

dfe_library_test_utilities.mdl – Additional blocks that may be used to simplify the construction of test bench models. Some of these blocks are also used in the example design testbenches and the conformance test models. Note that this library of blocks is provided “as is” and is not supported.

slblocks.m – Function to integrate the library with the ‘Simulink Library Browser’.

addLibraryToPath.m – Utility function to add the library directories (ie, this directory and the low level subdirectory) to the Matlab path and then save the modified path.

low level

*.* – Additional library implementation files. It should not normally be necessary to access these files directly.


dfe_example_designs – This directory contains example DDC and DUC designs.

ddc

dfe_18x_ddc_design_lib.mdl – Simulink library file containing an example 18-channel DDC design. This design is configured to extract six RF carriers from three IF inputs.

dfe_18x_ddc_design.mdl – Simulink model used to build the design contained in dfe_18x_ddc_design_lib.mdl for hardware co-simulation.

netlist_* – Hardware co-simulation files for the dfe_18x_ddc_design.mdl model. The library is supplied with files for use with the XtremeDSP (PCI/USB interface) and ML402 (point-to-point Ethernet) development platforms. Each directory includes some or all of the following.

dfe_18x_ddc_design_hwcosim_lib.mdl – Simulink library file containing the hardware co-simulation block.

dfe_18x_ddc_design_cw.bit – Hardware configuration file.

dfe_18x_ddc_design_cw_bd.bmm – Block RAM initialisation file (Xilinx ML402 hardware co-simulation target only).

dfe_18x_ddc_testbench.mdl – Simulink model used to exercise the example design. This model is supplied configured with the ML402 (point-to-point Ethernet) hardware co-simulation target.

dfe_18x_ddc_testbench_init.m – Script used to initialise workspace variables required by dfe_18x_ddc_testbench.mdl called as the model is loaded and on initialisation.

dfe_18x_ddc_testbench_start.m – Script used to configure shared-memory registers implemented in the dfe_18x_ddc_testbench.mdl model called when the simulation starts.

dfe_18x_ddc_testbench_stop.m – Script used to analyse output of the dfe_18x_ddc_testbench.mdl model called when the simulation stops.

*.* – Additional files used to run the example testbench.


dfe_example_designs (continued…)

duc

dfe_18x_duc_design_lib.mdl – Simulink library file containing an example 18-channel DUC design. This design is configured to up-convert six RF carriers onto three complex IF outputs.

dfe_18x_duc_design.mdl – Simulink model used to build the design contained in dfe_18x_duc_design_lib.mdl for hardware co-simulation.

netlist_* – Hardware co-simulation files for the dfe_18x_duc_design.mdl model. The library is supplied with files for use with the XtremeDSP (PCI/USB interface) and ML402 (point-to-point Ethernet) development platforms. Each directory includes some or all of the following.

dfe_18x_duc_design_hwcosim_lib.mdl – Simulink library file containing the hardware co-simulation block.

dfe_18x_duc_design_cw.bit – Hardware configuration file.

dfe_18x_duc_design_cw_bd.bmm – Block RAM initialisation file (Xilinx ML402 hardware co-simulation target only).

dfe_18x_duc_testbench.mdl – Simulink model used to exercise the example design. This model is supplied configured with the ML402 (point-to-point Ethernet) hardware co-simulation target.

dfe_18x_duc_testbench_init.m – Script used to initialise workspace variables required by dfe_18x_duc_testbench.mdl called as the model is loaded and on initialisation.

dfe_18x_duc_testbench_start.m – Script used to configure shared-memory registers implemented in the dfe_18x_duc_testbench.mdl model called when the simulation starts.

dfe_18x_duc_testbench_stop.m – Script used to analyse output of dfe_18x_duc_testbench.mdl model called when the simulation stops.

*.* – Additional files used to run the example testbench.


dfe_fullspeed_design – This directory contains files associated with the full-speed demonstration application for the XtremeDSP card. As well as the files for the GUI, the source files for the design are provided also.

dfe_fullspeed_gui

dfeFullSpeedGUI.m – Main function for the full-speed GUI.

dfe_fullspeed_gui_help.htm – Help file for the full-speed GUI.

dfe_fullspeed_gui_help_files

*.gif – Image files required by dfe_fullspeed_gui_help.htm.

download_files

*.bit – Configuration files required by the full-speed GUI. (Note that these include copies of the ext_clock_2v80.bit and osc_clock_2v80.bit files supplied with the XtremeDSP development kit.)

*.* – Additional files used by the full-speed GUI application.

ddc_subsystem

dfe_12x_ddc_subsystem.mdl – Simulink model implementing the DDC subsystem incorporated into the full-speed demonstration FPGA.

ngc_netlist

dfe_12x_ddc_subsystem_cw.ngc – Synthesised netlist.

duc_subsystem

dfe_12x_duc_subsystem.mdl – Simulink model implementing the DUC subsystem incorporated into the full-speed demonstration FPGA.

ngc_netlist

dfe_12x_duc_subsystem_cw.ngc – Synthesised netlist.


dfe_fullspeed_design (continued…)

dfe_fullspeed_design_fpga

dfe_fullspeed_design_fpga.ise – Xilinx ISE project file.

dfe_fullspeed_design_fpga.vhd – Top-level VHDL source file.

dfe_fullspeed_design_fpga.bit – FPGA configuration file.

*.* – Additional files.

dfe_clock_fpga

dfe_clock_fpga.ise – Xilinx ISE project file.

dfe_clock_fpga.vhd – Top-level VHDL source file.

dfe_clock_fpga.bit – Clock FPGA configuration file.


dfe_conformance_tests – This directory includes HTML reports generated by publishing the top-level conformance test scripts for both the DDC and DUC. The source for the conformance tests is supplied also.

ddc

ddc_conformance_tests.m – Top-level DDC conformance tests script.

html

ddc_conformance_tests.html – DDC conformance tests summary.


netlist_* – Hardware co-simulation files used by the conformance tests.



dfe_conformance_tests (continued…)

duc

duc_conformance_tests.m – Top-level DUC conformance tests script.

html

duc_conformance_tests.html – DUC conformance tests summary.


netlist_* – Hardware co-simulation files used by the conformance tests.


20-136 TD-SCDMA Digital Front-End - Requirements Specification.pdf – Requirements specification document.

20-144 TD-SCDMA Digital Front-End - Acceptance Test Specification.pdf – Acceptance test specification document.

21-029 TD-SCDMA Digital Front-End - Design Description.pdf – Design description document (this document).


Appendix B – Example Designs

The DFE library is supplied with two example designs, an 18-channel DDC and an

18-channel DUC. Both designs assume three IF inputs/outputs and six carrier frequencies

and are supplied with example hardware co-simulation files.

B.1 Example 18-Channel DDC Design

A block diagram of the 18-channel DDC design is shown in Figure B-1. The input data from

three, real IF inputs (with amplitudes in the range -1 to +1) are mixed to quadrature baseband

using full mixers before being filtered and decimated to produce 18 quadrature baseband

outputs. DDC_SER_OUT_DATA blocks are used to output the filtered and decimated baseband

signals serially. A single DDC_SER_OUT_CTRL block is used to output the associated data

clock and framing strobe signals.

The example design can be exercised using the dfe_18x_ddc_testbench.mdl model. Before

starting simulation, this model calls the dfe_18x_ddc_testbench_init.m script to initialise

various workspace variables, including the input data. As supplied, this script generates a

mixture of sinusoidal and modulated input waveforms, as summarised in Table B-1.

'ADC'SerialOutput(Data)

SerialOutput(Data)

'ADC'SerialOutput(Data)

SerialOutput(Data)

'ADC'4

ddc_in_a_d16

ducFreq

32

ducFreq1

ddcDelayA1

SerialOutput(Data)

ddc_out_a1_iq24

4

15

6

ddcGainA1

16

ducFreq6

ddcDelayA6

SerialOutput(Data)

ddc_out_a6_iq24

4

15

6

ddcGainA6

16

SerialOutput(Ctrl)

ddc_out_dclk

ddc_out_fs

TD-SCDMA DDC (6 Channels)

Local Oscillator

DDC Mixer

ddc_out_c6_iq

ddc_out_c1_iqddc_in_c_d

Figure B-1 Example 18-channel DDC design.


Carrier Input A Input B Input C

1 100 kHz sinusoid 100 kHz sinusoid TD-SCDMA signal

2 100 kHz sinusoid - TD-SCDMA signal

3 100 kHz sinusoid TD-SCDMA signal TD-SCDMA signal

4 100 kHz sinusoid TD-SCDMA signal TD-SCDMA signal

5 100 kHz sinusoid - TD-SCDMA signal

6 100 kHz sinusoid 100 kHz sinusoid TD-SCDMA signal

Once loaded, the dfe_18x_ddc_testbench_start.m script is called to configure shared-memory

registers embedded in the example design. These shared-memory registers are used to

configure the device under test with the correct carrier frequencies, channel gains and channel

delays.

During simulation, the time-domain outputs may be viewed on the Simulink scope blocks. A

separate scope is included for each of the six carrier frequencies. Each scope has three

displays, one for each IF input (A = top, B = middle and C = bottom). The yellow trace

represents the real (ie, in-phase) output and the magenta trace the imaginary (ie, quadrature)

output.

At the end of simulation Simulink will call dfe_18x_ddc_testbench_stop.m. This scripts

analyses the logged output data and generates seven figures. The first shows the spectrum of

the input waveforms. The remaining figures show the output for each carrier frequency in the

following ways; time-domain, frequency-domain, constellation and a normalised

constellation. An example of this is shown in Figure B-2.

Table B-1 Input stimuli for the 18-channel DDC testbench.


0 50 100 150 200 250 300-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

Time Domain

Time (μs)

Am

plitu

de

-0.6 -0.4 -0.2 0 0.2 0.4 0.6

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

Frequency Domain

Frequency (MHz)

Pow

er (d

BFS

CW

)

-1 -0.5 0 0.5 1

-1

-0.5

0

0.5

1

Constellation

I

Q

-1.5 -1 -0.5 0 0.5 1 1.5-1.5

-1

-0.5

0

0.5

1

1.5

Constellation (Rotated and Scaled)

I

Q

Re{A1}Im{A1}Re{B1}Im{B1}Re{C1}Im{C1}Discarded

A1 (Peak: -17.85 dB @ +0.102 MHz)B1 (Peak: -17.85 dB @ +0.102 MHz)C1 (Peak: -32.01 dB @ -0.516 MHz)

A1B1C1

A1 (EVM: -)B1 (EVM: -)C1 (EVM: 0.12%)

Figure B-2 Example figure generated by the DDC testbench showing the time- and frequency-domain output of the DUT together with scaled and unscaled I/Q plots.


B.2 Example 18-Channel DUC Design

A block diagram of the 18-channel DUC design is shown in Figure B-3. The design is

configured to up-convert six carriers onto three quadrature IF data streams. Each stream is

processed by a separate TD-SCDMA DUC (6 channel) block. By default the six carriers are

spaced by 1.6 MHz centred around 19.2 MHz.

The input data to the DUC are complex baseband sample pairs in the range -1 to 1,

represented by 16-bit signed values. The design accepts serial input data using

DUC_SER_IN_DATA blocks and a single DUC_SER_IN_CTRL block is instantiated at the top

level to output the associated data clock and framing strobe signals. Complex IF data are

output in parallel using the DUC_OUT block. Again, these data are 16-bit signed values in the

range -1 to 1. To prevent clipping resulting from overshoot in the pulse shaping filters, each

carrier is scaled by a half at the input to prevent overflow. Also, as six carriers are summed

together in the mixer, each carrier is scaled by 1/6 in the mixer. Therefore the overall carrier

gain through the DUC design is 1/12. Finally, an arbitrary linear gain between zero and

(almost) one can be applied to each carrier in the example by modifying the gain profile data

written to each channel.

The example DUC design can be exercised using the dfe_18x_duc_testbench.mdl model.

This model uses the dfe_18x_duc_testbench_init.m script to initialise various workspace

variables, including the input data. As supplied, this script generates random data on the

inputs of three carriers. Scope blocks are provided to display the output waveforms, with a

duc_in_c1_iq

duc_in_c6_iq

ddc_out_c_i/q'DAC'Serial Input(Data)

Serial Input(Data)

'DAC'Serial Input(Data)

Serial Input(Data)

'DAC'4

ddc_out_a_i/q16

ducFreq

32

ddcFreq1

Serial Input(Data)duc_in_a1_iq

16 15

6

gain_data

ddcFreq6

Serial Input(Data)duc_in_a6_iq

16 15

6Serial Input

(Ctrl)duc_in_fs TD-SCDMA DUC (6 Channels)

Local Oscillator

DDC Mixer

duc_in_dclk

RAM

RAMgain_addrgain_we

Figure B-3 Example 18-channel DUC design.


separate scope for each IF data stream. After the simulation is completed, the model calls the

dfe_18x_duc_testbench_stop.m script, which analyses the output data and produces plots of

the output spectrum, eye diagram and modulation constellation. An example of this is shown

in Figure B-4. EVM measurements on the three channels are also displayed in the MATLAB

console.

0 10 20 30 40 50 60 70 80 90-2

-1

0

1

2Time Domain

Time (us)

Am

plitu

de

-2 -1 0 1 2-2

-1

0

1

2Vector Diagram

0 0.5 1 1.5-2

-1

0

1

2Eye Diagram

Time (us)

Am

plitu

de

-1 -0.5 0 0.5 1-150

-100

-50

0

Spectrum (With Hanning Window)

Frequency (MHz)

Am

plitu

de (d

B)

Figure B-4 Example figure generated by the DUC testbench showing the time- and frequency-domain output of the DUT together with normalised I/Q plot and ‘eye’ diagram.


B.3 Changing the Simulation Target

The example designs can be found in subdirectories of the dfe_example_designs directory.

Each design is implemented as an unmasked subsystem in a Simulink library file and is

accompanied by a model that can be used to build the design for hardware co-simulation as

well as pre-compiled hardware co-simulation targets and the testbench models described in

the previous sections. If necessary, the default simulation target may be replaced by

completing the following steps:

1. Open the test bench model (eg, dfe_18x_ddc_testbench.mdl).

2. Delete the simulation target (eg, dfe_18x_ddc_design hwcosim).

3. Copy and paste the wanted simulation target from its library file into the test bench

model (eg, the dfe_18x_ddc block from dfe_18x_ddc_design_lib.mdl).

4. Save the test bench file with the new target instantiated.

When running a simulation that uses a hardware co-simulation block, it may be necessary to

modify the path to the FPGA configuration file. This can be achieved by double-clicking on the

instantiated hardware co-simulation block and modifying the ‘Bitstream name’ field as

appropriate.

When opening models that include blocks instantiated from the DFE library a number of warnings

may be generated of the form

Warning: "dfe_18x_ddc_design_lib/dfe_18x_ddc/Carrier Freq 1" is a parameterized link. To view, discard, or propagate the changes for this link, use the "Link Options" menu item. > In general\private\openmdl at 13 In open at 141 In uiopen at 181

These warnings are quite normal and can be ignored safely.


Appendix C – Full-Speed DFE Demonstration Application

C.1 Introduction

The TD-SCDMA digital front end (DFE) library is shipped with a full-speed demonstration

application developed for operation with the Xilinx Virtex 4 XtremeDSP card. The full-

speed design includes a 12-channel digital up-converter (DUC) and a 12-channel digital

down-converter (DDC) and is controlled via a graphical user interface (GUI) that runs within

Matlab. A block diagram showing the configuration of the demonstration design is shown in

Figure C-1.

C.2 Prerequisites

The full-speed demonstration application requires Matlab to be installed on the host PC. In

addition, the full-speed demonstration application requires the FUSE Toolbox for Matlab.

For more information on the FUSE Toolbox please see the documentation that is supplied

with the Xilinx XtremeDSP kit.

Development of the full-speed demonstration application was completed using Matlab

Version 7.2 (R2006a) and Version 6.0 of the FUSE Toolbox for Matlab.

TD-SCDMA DFE Full-Speed Demo FPGA

PC

I Int

erfa

ce IP

Cor

e(S

uppl

ied

with

Xtre

meD

SP

)

DDC Capture Logic

12-Channel DUC(System Generator)

DAC 1

DAC 2

ADC 1

ADC 2

76.8 MHz

40.0 MHz

(×4)

(×1)

Ana

logu

e IF

Inpu

tsAn

alog

ue IF

Out

puts

Inte

rface

to H

ost P

C (P

CI/U

SB)

k = -0.5k = -1.0

k = -0.5k = -1.0

12-Channel DDC(System Generator)

DUC Playback Logic

Deb

ug O

utpu

ts

DUC A(6-Channel DUC)

DUC B(6-Channel DUC)

Output Buffer

Output Buffer

DataBuffer

(8KChips)

Capture ControllerClockManager

Input Buffer

Input Buffer

DDC A(6-Channel DDC)

DDC B(6-Channel DDC)

Playback Controller

Dat

a D

emul

tiple

xer

and

Cha

nnel

Ena

bles

Pro

gram

mab

leD

UC

Out

put D

elay

DataBuffer

(8KChips)

DDC A Ch 1Serial Output

DFE Control Registers(Tuning, gain, delay, etc)

ParallelDebugOutput

Figure C-1 Block diagram of the 12-channel DUC/DDC full-speed demonstration design FPGA.


C.3 Running the Full-Speed Design

Before running the full-speed design GUI, check that the XtremeDSP kit is connected to the

host PC and that it is powered on. Both PCI and USB interfaces are supported, but best

performance will be achieved using the PCI interface due to the bandwidth limitations of

USB.

To invoke the GUI, shown in Figure C-2, browse to the dfe_fullspeed_gui directory and type

dfeFullspeedGUI at the Matlab command prompt.

C.4 Further Information

For further information regarding the operation of the full-speed demonstration application

please refer to the help file provided with the GUI, dfe_fullspeed_gui_help.htm. The help file

can be opened by clicking on ‘Help’ or selecting ‘Help | Help’ from the menu bar from within

the GUI.

Figure C-2 Full-speed demonstration GUI.

td-scdma digital front-end - design...

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