tdr (time domain reflectometer)tera.yonsei.ac.kr/class/2016_1_2/lecture/desing 5 channel... ·...

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1/23 고속 SERIAL INTERFACE 회로 및 시스템 TDR TDR (Time Domain Reflectometer) Pulse generator produces step input with very large period. Scope measures the pulse shape. Analysis of transmission line characteristic. 50Ω Sampler To Ocsilloscope Zo, TD TDR Sampling Module

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Page 1: TDR (Time Domain Reflectometer)tera.yonsei.ac.kr/class/2016_1_2/lecture/Desing 5 Channel... · 2016-05-09 · 고속SERIAL INTERFACE 회로및시스템 1/23 TDR TDR (Time Domain Reflectometer)

1/23고속 SERIAL INTERFACE 회로및시스템

TDR

TDR (Time Domain Reflectometer)

– Pulse generator produces step input with very large period.

– Scope measures the pulse shape.

– Analysis of transmission line characteristic.

50Ω

Sampler

To Ocsilloscope

Zo, TD

TDR Sampling Module

Page 2: TDR (Time Domain Reflectometer)tera.yonsei.ac.kr/class/2016_1_2/lecture/Desing 5 Channel... · 2016-05-09 · 고속SERIAL INTERFACE 회로및시스템 1/23 TDR TDR (Time Domain Reflectometer)

2/23고속 SERIAL INTERFACE 회로및시스템

TDR Load Condition 1

TDR application : resistor load

– Open

– Short

– Matching

T1

Z0 = 50TD = 1n

50

Open 0 1

0.5

0.5

0.5

0.5+0.5

0.5+0.5

V1=0V2=1TD: 1n

Volt 측정

1n 2n 3n 4n 5n

0.5

1Open

T1

Z0 = 50TD = 1n

50

Short 0 1

0.5

-0.5

0.5

0.5-0.5

0.5-0.5

V1=0V2=1TD: 1n

Volt 측정

1n 2n 3n 4n 5n

0.5

1

Short

T1

Z0 = 50TD = 1n

50

50

0 0

0.5

0

0.5

0.5+0

0.5+0

V1=0V2=1TD: 1n

Volt 측정

1n 2n 3n 4n 5n

0.5

1

Matching

Page 3: TDR (Time Domain Reflectometer)tera.yonsei.ac.kr/class/2016_1_2/lecture/Desing 5 Channel... · 2016-05-09 · 고속SERIAL INTERFACE 회로및시스템 1/23 TDR TDR (Time Domain Reflectometer)

3/23고속 SERIAL INTERFACE 회로및시스템

mtline Setting

mtline selection

– Cadence_IC → analogLib → Passives → mtline → symbol

Page 4: TDR (Time Domain Reflectometer)tera.yonsei.ac.kr/class/2016_1_2/lecture/Desing 5 Channel... · 2016-05-09 · 고속SERIAL INTERFACE 회로및시스템 1/23 TDR TDR (Time Domain Reflectometer)

4/23고속 SERIAL INTERFACE 회로및시스템

mtline Setting

– Type of Input : Tline

– Physical length : 1

– Characteristic impedance : 50

– Delay Time : 1n

Page 5: TDR (Time Domain Reflectometer)tera.yonsei.ac.kr/class/2016_1_2/lecture/Desing 5 Channel... · 2016-05-09 · 고속SERIAL INTERFACE 회로및시스템 1/23 TDR TDR (Time Domain Reflectometer)

5/23고속 SERIAL INTERFACE 회로및시스템

TDR Load Condition 1

– V-pulse setting

– Voltage1 : 0V

– Voltage2 : 1V

– Period : 10n

– Rise time : 1p

– Fall time : 1p

– Pulse width : 5n

– Simulation setting

– Trans

– 5n

100T

0

50

Page 6: TDR (Time Domain Reflectometer)tera.yonsei.ac.kr/class/2016_1_2/lecture/Desing 5 Channel... · 2016-05-09 · 고속SERIAL INTERFACE 회로및시스템 1/23 TDR TDR (Time Domain Reflectometer)

6/23고속 SERIAL INTERFACE 회로및시스템

TDR Load Condition 1

Open

Matching

Short

Simulation result

Page 7: TDR (Time Domain Reflectometer)tera.yonsei.ac.kr/class/2016_1_2/lecture/Desing 5 Channel... · 2016-05-09 · 고속SERIAL INTERFACE 회로및시스템 1/23 TDR TDR (Time Domain Reflectometer)

7/23고속 SERIAL INTERFACE 회로및시스템

TDR Load Condition 2

TDR application : resistor load

– 25ohm

– 50ohm

– 100ohm

1n 2n 3n 4n 5n

0.5

1

250.33

0.66

T1

Z0 = 50TD = 1n

50

0 0.333

0.5

-0.16

0.50.5-0.16=0.34

0.5-0.16=0.34

V1=0V2=1TD: 1n

Volt 측정

25

T1

Z0 = 50TD = 1n

50

0 0

0.5

0

0.5

0.5+0

V1=0V2=1TD: 1n

Volt 측정

50

0.5

1n 2n 3n 4n 5n

0.5

1

50

0.33

0.66

T1

Z0 = 50TD = 1n

50

100

0 0.333

0.5

0.16

0.50.5+0.16

=0.660.5+0.16

=0.66

V1=0V2=1TD: 1n

Volt 측정

1n 2n 3n 4n 5n

0.5

1100

0.33

0.66

Page 8: TDR (Time Domain Reflectometer)tera.yonsei.ac.kr/class/2016_1_2/lecture/Desing 5 Channel... · 2016-05-09 · 고속SERIAL INTERFACE 회로및시스템 1/23 TDR TDR (Time Domain Reflectometer)

8/23고속 SERIAL INTERFACE 회로및시스템

TDR Load Condition 2

25ohm

100ohm

50ohm

Simulation result

Page 9: TDR (Time Domain Reflectometer)tera.yonsei.ac.kr/class/2016_1_2/lecture/Desing 5 Channel... · 2016-05-09 · 고속SERIAL INTERFACE 회로및시스템 1/23 TDR TDR (Time Domain Reflectometer)

9/23고속 SERIAL INTERFACE 회로및시스템

TDR Load Condition 3

TDR application : capacitive & inductive load

– Capacitive load

– Inductive load

1n 2n 3n 4n 5n

0.5

1capacitor

T1

Z0 = 50TD = 1n

50V1=0V2=1TD: 1n

Volt 측정

3p

T1

Z0 = 50TD = 1n

50V1=0V2=1TD: 1n

Volt 측정

7.5nH

1n 2n 3n 4n 5n

0.5

1

inductor

Page 10: TDR (Time Domain Reflectometer)tera.yonsei.ac.kr/class/2016_1_2/lecture/Desing 5 Channel... · 2016-05-09 · 고속SERIAL INTERFACE 회로및시스템 1/23 TDR TDR (Time Domain Reflectometer)

10/23고속 SERIAL INTERFACE 회로및시스템

TDR Load Condition 3

Simulation result

Capacitor

Inductor

Page 11: TDR (Time Domain Reflectometer)tera.yonsei.ac.kr/class/2016_1_2/lecture/Desing 5 Channel... · 2016-05-09 · 고속SERIAL INTERFACE 회로및시스템 1/23 TDR TDR (Time Domain Reflectometer)

11/23고속 SERIAL INTERFACE 회로및시스템

TDR Discontinuity 1

TDR application : capacitive & inductive discontinuity

– Capacitive discontinuity

– Inductive discontinuity

T1

Z0 = 50TD = 1n

50V1=0V2=1TD: 1n

Volt 측정

3p

T1

Z0 = 50TD = 1n

Open

1n 2n 3n 4n 5n

0.5

1

capacitor

T1

Z0 = 50TD = 1n

50V1=0V2=1TD: 1n

Volt 측정

T1

Z0 = 50TD = 1n

Open

7.5nH

1n 2n 3n 4n 5n

0.5

1

inductor

Page 12: TDR (Time Domain Reflectometer)tera.yonsei.ac.kr/class/2016_1_2/lecture/Desing 5 Channel... · 2016-05-09 · 고속SERIAL INTERFACE 회로및시스템 1/23 TDR TDR (Time Domain Reflectometer)

12/23고속 SERIAL INTERFACE 회로및시스템

TDR Discontinuity 1

– V-pulse setting

– Voltage1 : 0V

– Voltage2 : 1V

– Period : 10n

– Rise time : 1p

– Fall time : 1p

– Pulse width : 5n

– Simulation setting

– Trans

– 5n

– Conservative

Page 13: TDR (Time Domain Reflectometer)tera.yonsei.ac.kr/class/2016_1_2/lecture/Desing 5 Channel... · 2016-05-09 · 고속SERIAL INTERFACE 회로및시스템 1/23 TDR TDR (Time Domain Reflectometer)

13/23고속 SERIAL INTERFACE 회로및시스템

TDR Discontinuity 1

Capacitor

discontinuity

Inductor

discontinuity

Simulation result

Page 14: TDR (Time Domain Reflectometer)tera.yonsei.ac.kr/class/2016_1_2/lecture/Desing 5 Channel... · 2016-05-09 · 고속SERIAL INTERFACE 회로및시스템 1/23 TDR TDR (Time Domain Reflectometer)

14/23고속 SERIAL INTERFACE 회로및시스템

S-Parameter

S11 simulation condition

– Simulation setting

– Analysis : sp

– Ports : Port0 and Port1 choice

– Sweep variable : frequency

– Sweep range : 10M ~ 5.0G

– Sweep type : Linear (Step size : 10M)

– Direct plot from

– S11 mag

– S11 Z chart

Page 15: TDR (Time Domain Reflectometer)tera.yonsei.ac.kr/class/2016_1_2/lecture/Desing 5 Channel... · 2016-05-09 · 고속SERIAL INTERFACE 회로및시스템 1/23 TDR TDR (Time Domain Reflectometer)

15/23고속 SERIAL INTERFACE 회로및시스템

S-Parameter

Simulation result

S11 mag

S11 Z-chart

2GHz0Hz

Page 16: TDR (Time Domain Reflectometer)tera.yonsei.ac.kr/class/2016_1_2/lecture/Desing 5 Channel... · 2016-05-09 · 고속SERIAL INTERFACE 회로및시스템 1/23 TDR TDR (Time Domain Reflectometer)

16/23고속 SERIAL INTERFACE 회로및시스템

S-Parameter

mtline setting

– Micro-stripe transmission line type

– Type of Input : FieldSolver

– Transmission line type : microstrip

– Model type : wideband

– Real dielectric const of layers : 4.8 (FR4)

– Dielectric layer thickness : 360u (H)

– Signal line width : 625u (W)

– Signal line thickness : 17.78u (T)

– Display Cross-section

0

87 5.98ln

0.81.41r

HZ

W T

Page 17: TDR (Time Domain Reflectometer)tera.yonsei.ac.kr/class/2016_1_2/lecture/Desing 5 Channel... · 2016-05-09 · 고속SERIAL INTERFACE 회로및시스템 1/23 TDR TDR (Time Domain Reflectometer)

17/23고속 SERIAL INTERFACE 회로및시스템

S-Parameter

Simulation condition

– Simulation setting

– Analysis : sp

– Ports : Port0 and Port1 choice

– Sweep variable : frequency

– Sweep range : 10M ~ 20G

– Sweep type : Linear (Step size : 10M)

– Direct plot from

– S11 dB20 & S21 dB20 & S11 Z-chart

– Sweep : length (10m ~ 100m)

Page 18: TDR (Time Domain Reflectometer)tera.yonsei.ac.kr/class/2016_1_2/lecture/Desing 5 Channel... · 2016-05-09 · 고속SERIAL INTERFACE 회로및시스템 1/23 TDR TDR (Time Domain Reflectometer)

18/23고속 SERIAL INTERFACE 회로및시스템

S-Parameter

Simulation result

– Length ↑ - loss↑

– Impedance match

S11 dB20

S11 Z-chart

S21 dB2050ohm

Page 19: TDR (Time Domain Reflectometer)tera.yonsei.ac.kr/class/2016_1_2/lecture/Desing 5 Channel... · 2016-05-09 · 고속SERIAL INTERFACE 회로및시스템 1/23 TDR TDR (Time Domain Reflectometer)

19/23고속

Page 20: TDR (Time Domain Reflectometer)tera.yonsei.ac.kr/class/2016_1_2/lecture/Desing 5 Channel... · 2016-05-09 · 고속SERIAL INTERFACE 회로및시스템 1/23 TDR TDR (Time Domain Reflectometer)

20/23고속 SERIAL INTERFACE 회로및시스템

S-Parameter

– Tperiod : 1/10G

– Seed : 1

– Vlogic_high : 1

– Vlogic_low : 0

– Trise : 10p

– Tfall : 10p

Transient simulation condition

Page 21: TDR (Time Domain Reflectometer)tera.yonsei.ac.kr/class/2016_1_2/lecture/Desing 5 Channel... · 2016-05-09 · 고속SERIAL INTERFACE 회로및시스템 1/23 TDR TDR (Time Domain Reflectometer)

21/23고속 SERIAL INTERFACE 회로및시스템

S-Parameter

Simulation result

– 10Gbps datarate condition

Length : 500m Length : 1200mLength : 100m

Page 22: TDR (Time Domain Reflectometer)tera.yonsei.ac.kr/class/2016_1_2/lecture/Desing 5 Channel... · 2016-05-09 · 고속SERIAL INTERFACE 회로및시스템 1/23 TDR TDR (Time Domain Reflectometer)

22/23고속 SERIAL INTERFACE 회로및시스템

Exercise 1

TDR application : discontinuity

– Derive L and C circuit from the given waveforms.

– Simulate S21 and analyze characteristics of TDR & S-parameter

simulation results.

< TDR > < S11 magnitude >

1GHz

50

T1

Z0 = 50TD = 1n

50V1=0V2=1TD: 1n

Volt 측정

L & C

Circuit

0

1

Page 23: TDR (Time Domain Reflectometer)tera.yonsei.ac.kr/class/2016_1_2/lecture/Desing 5 Channel... · 2016-05-09 · 고속SERIAL INTERFACE 회로및시스템 1/23 TDR TDR (Time Domain Reflectometer)

23/23고속 SERIAL INTERFACE 회로및시스템

Exercise 2

TDR application : discontinuity

– Derive L and C circuit from the given waveforms.

– Simulate S21 and analyze characteristics of TDR & S-parameter

simulation results.

< TDR > < S11 magnitude >

1GHz

50

T1

Z0 = 50TD = 1n

50V1=0V2=1TD: 1n

Volt 측정

L & C

Circuit

0

1

Page 24: TDR (Time Domain Reflectometer)tera.yonsei.ac.kr/class/2016_1_2/lecture/Desing 5 Channel... · 2016-05-09 · 고속SERIAL INTERFACE 회로및시스템 1/23 TDR TDR (Time Domain Reflectometer)

24/23고속 SERIAL INTERFACE 회로및시스템

[email protected]

Q & A