Team M1Enigma Machine

Milestone 7 - 26 March, 2006

Design Manager: Prateek Goenka

Adithya Attawar (M11)Shilpi Chakrabarti (M12)

Mike Sokolsky (M14)

Design Manager: Prateek Goenka

Status• Finished:– Behavioral Verilog and C simulation– Structural Verilog– Logic optimization– Module-level spice delay and power simulations– Floorplan– Top-level schematic testing

• In Progress:– Functional block layout– Simulation of functional blocks

• To do:– Global Layout– Testing– Simulation

STATUS

Layout done: Layout Needed:

Gates ROM

Muxes and Registers RAM

DFF, TFF Flipflops FSM

Add_Mod26 3-bit and 5-bit serial input registers

Wheel Counter Cells Wheel Counter

Design Decisions

• Finalized the SRAM design

• Layout of Add_Mod26

• Layout of 3-bit and 5-bit counter cells

• Updated layout of Wheel Counter

• Floorplan

Initial Floorplan

UPDATED FLOORPLAN

Schematic Delay: 68psExtractedRC Delay: 94ps

Register

Schematic of Add_Mod26

LAYOUT OF ADD_MOD26

LOOKAHEAD MODULE LAYOUT

LOOKAHEAD 2 MODULE LAYOUT

SUBTRACTOR MODULE LAYOUT

3-bit Comparator

3-bit Counter Cell3, 1-bit T Flips Flops Count Logic

3-bit Counter

5-bit Counter Cell5, 1-bit D/T Flips Flops

Count Logic w/Reset at 26

Wheel Counter Plan(Module layout and wire planning)

5-bit Counter Cell

Data from counters

Wheel Select

Wheel Position5-bit Counter Cell